{"id":2232305,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2232305/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260504-nord-tlmm-v4-1-ccaa731ee8b3@oss.qualcomm.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/1.1/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260504-nord-tlmm-v4-1-ccaa731ee8b3@oss.qualcomm.com>","date":"2026-05-04T10:07:25","name":"[v4,1/2] dt-bindings: pinctrl: describe the Qualcomm nord-tlmm","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"bd387aa78a630ad40fee9a6871271be213c45823","submitter":{"id":92196,"url":"http://patchwork.ozlabs.org/api/1.1/people/92196/?format=json","name":"Bartosz Golaszewski","email":"bartosz.golaszewski@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260504-nord-tlmm-v4-1-ccaa731ee8b3@oss.qualcomm.com/mbox/","series":[{"id":502635,"url":"http://patchwork.ozlabs.org/api/1.1/series/502635/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=502635","date":"2026-05-04T10:07:24","name":"pinctrl: qcom: add support for the TLMM controller on Nord platforms","version":4,"mbox":"http://patchwork.ozlabs.org/series/502635/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2232305/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2232305/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=ihFTx8jy;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=Y1L7zw+E;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-gpio+bounces-36035-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"ihFTx8jy\";\n\tdkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"Y1L7zw+E\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=205.220.180.131","smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=oss.qualcomm.com"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g8HRq52npz1yJ9\n\tfor ; Mon, 04 May 2026 20:09:11 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 00F5B302B38F\n\tfor ; Mon, 4 May 2026 10:08:12 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 3FD18392C20;\n\tMon, 4 May 2026 10:07:51 +0000 (UTC)","from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com\n [205.220.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id DB8FD391E7A\n\tfor ; Mon, 4 May 2026 10:07:44 +0000 (UTC)","from pps.filterd (m0279871.ppops.net [127.0.0.1])\n\tby mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 6448fTYe486800\n\tfor ; Mon, 4 May 2026 10:07:41 GMT","from mail-qt1-f197.google.com (mail-qt1-f197.google.com\n [209.85.160.197])\n\tby mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dw8uxn8qr-1\n\t(version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n\tfor ; Mon, 04 May 2026 10:07:41 +0000 (GMT)","by mail-qt1-f197.google.com with SMTP id\n d75a77b69052e-50faf575af4so91991971cf.0\n for ;\n Mon, 04 May 2026 03:07:41 -0700 (PDT)","from brgl-qcom.local ([2a01:cb1d:dc:7e00:56cb:50e1:b507:63d9])\n by smtp.gmail.com with ESMTPSA id\n ffacd0b85a97d-44a986aac01sm23400860f8f.31.2026.05.04.03.07.38\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Mon, 04 May 2026 03:07:39 -0700 (PDT)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1777889269; cv=none;\n b=DXRx4Keq83DdFHInRYUw/YUESpbWQlShzmv4xrrE7n6SKbmLlZJs89P889qg27LQCswRZ9B8xDxFCRgDY0NZqKu98E3z3UyYketXQnTLmsmmiXEMwTo7NnsJWFx685xzkhLbKKh88NfMPo7lmSVVHDsKN4hYPg0F231kEVEisXc=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1777889269; c=relaxed/simple;\n\tbh=trMfGHSt7GP5rCiBhDJR31ViCd04lGLClOnUXczfWAE=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References:\n\t In-Reply-To:To:Cc;\n b=YZTInkcMLSV6By4CCKQuJAg7iZkjYKhNGJIzePYyn4kkNva8fJkshdOxFCFxnmccxEyWgnb+6EJ62geFcXvP15L+mGiMDOXJ41oRZDj6oXCI6ep+6jryo5QCz8rbOw/xmPmPGVqQrVY+63vmbj2pu5Uo29W6BKkJTYv7c32mryE=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com;\n spf=pass smtp.mailfrom=oss.qualcomm.com;\n dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=ihFTx8jy;\n dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=Y1L7zw+E; arc=none smtp.client-ip=205.220.180.131","DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h=\n\tcc:content-transfer-encoding:content-type:date:from:in-reply-to\n\t:message-id:mime-version:references:subject:to; s=qcppdkim1; bh=\n\te9LF3qHhp4wFXOMFNpxuXixlpOU81cJpAtSlm607/ec=; b=ihFTx8jy/PdoYsSj\n\tghIk6DPBV/des2FzmEV18aNDI6iq8VZQVg65A5fWc8HniJ3YkuoDM2kaiQDxVQxW\n\tUXOSMQXZH+JCN2ouQEAvH7MYvbIefQ8+KK8hSWL+hhAMBKu4v4G6GwK4A3SnrniB\n\t8q3I6ZCAT+v7HxWtf27wbb9/q9f6Lus/Wd60A5vS7A733UjEaj0dUNhTQHck9dT1\n\thspHILeIIzI7TvnpcJ9bNpymr8GvV8+QNgnWCIgMurQU4yW0nJkmoApltBxtpocA\n\tWldUazvwrA/cIId10xh4fK47Kuh8qYK+PUR5YZKjmksAo0OVaGMRTEULi+Tsq3xr\n\t/xOPNQ==","v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=oss.qualcomm.com; s=google; t=1777889260; x=1778494060;\n darn=vger.kernel.org;\n h=cc:to:in-reply-to:references:message-id:content-transfer-encoding\n :mime-version:subject:date:from:from:to:cc:subject:date:message-id\n :reply-to;\n bh=e9LF3qHhp4wFXOMFNpxuXixlpOU81cJpAtSlm607/ec=;\n b=Y1L7zw+ES3uU6NHmthwT1lNzFgqezoZl3GTcSNP8ikTphCfcYkUDZ/gGEohcRMHaA7\n VNHD+NIv1Dm4+BCwAjGsVrkHo2Wv1Y0kbmkuOCpUB7NhjIximQ8dy61Ws4q8Nqq1TDNN\n BqJQIIvUe8LFsMAryHCr4oqtDoCLaTUTPvic7MIbBXroE5YcnRez0nr15HZEshOddhnh\n I/vRK318hiM73ifujZzBa8TvrDIUGjqKKSgZr0BKi8nx6Ml1eVt3Yy3njK5GiBRjNCAR\n PB/Qw/GYTGAA4kGLX0rO+uJlnvYkjTo4Mps+zqjo/HXc2+McWch5zQozLh2xkQx9u3og\n yq6A=="],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1777889260; x=1778494060;\n h=cc:to:in-reply-to:references:message-id:content-transfer-encoding\n :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to\n :cc:subject:date:message-id:reply-to;\n bh=e9LF3qHhp4wFXOMFNpxuXixlpOU81cJpAtSlm607/ec=;\n b=TtiaKqhgdcNt09nbaIbasGF3yaLPFKN+dxqPWu097DZG9QrpXmMC8LCmRJiRLrv+ax\n 86J8HodRQVwwBjCWnFySKRE2YPJ0G4aBt/WhDzxtHZvkAsZaRSkXu1h4IEbikH1+5AC9\n KG1CIc3+i61FOMuJFYNZZyf/Vr6baS7axjXqjNFg5uQ++j4DKLPx1yya8+wxk2iIe1fe\n eYL5aHWCsaovTM5IRrekPATTP87WzpEFVeafOHijPwJr1VBbJCJpTnoLj4JRZHCv6O98\n Vqs+Vlmrm1cGg7MhiSyxo1DeIGq7ghmtBsJMXP5UWBzqcPxojV7Sufz9YUxX47VSEi6r\n 57/g==","X-Forwarded-Encrypted":"i=1;\n AFNElJ+FhrODcKcR8ZtlT6HeQuvtfOwMbOST6de7mcv7RGoxoJWF9ihGIhVgAb5uvObanBvNW62kRvPcP8eY@vger.kernel.org","X-Gm-Message-State":"AOJu0YzXfsfMdp1wYx48IhlEQXvSD2T9A4RysWL5Q/8BJiwLLl8f4l3X\n\tKW+v/E/6Oa8ly/UiE9oJ4f07F+4uiLjvvynQXu8h/oC/nhe1zeVefA0AmviKlwglIY0rolCkTa3\n\tQzVe6JGKwCzYWEd2YAq2EkhR2+ek1aM/7K2yOG6x6jVyRbpMZIQIv6N3RiV0vT750","X-Gm-Gg":"AeBDiesU1ZkCFKBh7d5P9zVApMl+krJaaL5xARLYwu6LZ7MHzrthvEEM27sdu54AexX\n\t+cAPFUIUwfEqn3QlZyT6Ob9epkeyTyeoP8fO7u11QetXb2KIYOBW+57lgnwglDcObh7lSmWsmk+\n\tO9O3WgL6dlLKy47ZY8LnzAYKWvLl9bv5nP7dWYhLYkGIL0m9ANMhEXCVnWUm3/sDq5i1AcpOSB+\n\tQS3PdgHVxa86h/G+c4sssgxs720Avaad76xPgTL/vwCNOZDWmOGriKPLsQK/6y+WFLQpbwF9TzL\n\te8zSw8qXX6/UgiitLjBssEi6p1DrV+TnqIgpeP9JRFY96R9u7a48Ft2asRgr3akNNJlVCbqIiIe\n\tZH5sD9NTnlax6NIJuAQeMdbtlP0fRDRlkRhozDsLvDta5DNU3/RaHhcm741HY3A==","X-Received":["by 2002:ac8:5749:0:b0:50e:5cea:a519 with SMTP id\n d75a77b69052e-5104be0e3c4mr121964541cf.12.1777889260379;\n Mon, 04 May 2026 03:07:40 -0700 (PDT)","by 2002:ac8:5749:0:b0:50e:5cea:a519 with SMTP id\n d75a77b69052e-5104be0e3c4mr121964061cf.12.1777889259804;\n Mon, 04 May 2026 03:07:39 -0700 (PDT)"],"From":"Bartosz Golaszewski ","Date":"Mon, 04 May 2026 12:07:25 +0200","Subject":"[PATCH v4 1/2] dt-bindings: pinctrl: describe the Qualcomm\n nord-tlmm","Precedence":"bulk","X-Mailing-List":"linux-gpio@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260504-nord-tlmm-v4-1-ccaa731ee8b3@oss.qualcomm.com>","References":"<20260504-nord-tlmm-v4-0-ccaa731ee8b3@oss.qualcomm.com>","In-Reply-To":"<20260504-nord-tlmm-v4-0-ccaa731ee8b3@oss.qualcomm.com>","To":"Bjorn Andersson , Linus Walleij ,\n Rob Herring ,\n Krzysztof Kozlowski ,\n Conor Dooley ,\n Richard Cochran ,\n Bartosz Golaszewski ,\n Shawn Guo ,\n Arnd Bergmann ,\n Dmitry Baryshkov ","Cc":"linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n netdev@vger.kernel.org,\n Bartosz Golaszewski ,\n Krzysztof Kozlowski ","X-Mailer":"b4 0.14.2","X-Developer-Signature":"v=1; a=openpgp-sha256; l=6088;\n i=bartosz.golaszewski@oss.qualcomm.com; h=from:subject:message-id;\n bh=trMfGHSt7GP5rCiBhDJR31ViCd04lGLClOnUXczfWAE=;\n b=owEBbQKS/ZANAwAKAQWdLsv/NoTDAcsmYgBp+G/lntquQ/FJlrPT2ekNP4Wlia3Jwa71xuKBD\n JtT9StovxWJAjMEAAEKAB0WIQSR5RMt5bVGHXuiZfwFnS7L/zaEwwUCafhv5QAKCRAFnS7L/zaE\n w75GEACoRAvsFoAA+ft0q9vYNbjklsu0fLsrse0mjySd7qXxrVhCRS1gkrGYOwz83y15+BCkaAA\n oMnY7oJt+33SL1v9EX6kGT/fmYIyg6vx67Sqa1tYWyFI59vwWd/y4lZbpMsVJ5Wr4Vo8C85jgwz\n vWx/ZVIzMyyqtjfjvxmKkGcFTjLp6kEx44RlUkcXCM3UL7XRm5KixM6oj9UFgszu3lE8mK6oK58\n akJFOfXSCVec2/6Eb4ES5SS728bQY4UILGviMwuFa5qAYeutn41qAq8jk15/1bgIEQFAPeKj4mu\n i2wDe0Bz1jQdCRiBedP41ql3Kov/PdYu9yGbhVqUKrFUI6YpwdzBhDX00YrvYAkWJyPN/4xr1jz\n fVcdpE76seMhx08QF2uabR980ebynCPas7eIBXdzoONGglUPoQlnUtjD3zyFPt6nBCfwRKf0PcT\n VxgveI2aDZgLyesUI/cSJkqtsBbppirov9ifUacpEx6Syf3nLpGXZtd6B5tP4OL35Yfnuq8+uxc\n K9Xl9rxCAe+qOUOVcxulOGKtjy0qg4rOz5Uj++xwFtVbBFVZI2zQPi7zmTRc4Ceutts9apirqFw\n +o+QwTe/bNFDx2Xr+0ADxQc2DsVkvH+00EEpm6iOs44BrZyfHbaUGW3NuMjDz+t2Mq9T3nmlYH1\n Vm8QyII3jh/Is+Q==","X-Developer-Key":"i=bartosz.golaszewski@oss.qualcomm.com; a=openpgp;\n fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772","X-Proofpoint-ORIG-GUID":"qErVp0K9_suctY_ElAz2WTON5Rnq1Web","X-Authority-Analysis":"v=2.4 cv=QqxuG1yd c=1 sm=1 tr=0 ts=69f86fed cx=c_pps\n a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10\n a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=gEfo2CItAAAA:8\n a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=Ou3KgfM3KP2cLz_BwJkA:9 a=QEXdDO2ut3YA:10\n a=a_PwQJl-kcHnX1M80qC6:22 a=sptkURWiP4Gy88Gu7hUp:22","X-Proofpoint-GUID":"qErVp0K9_suctY_ElAz2WTON5Rnq1Web","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNTA0MDEwNyBTYWx0ZWRfX6JdHeTow9kxs\n TDUmFDn/s1giAyfijaIwrjGDUZt3yIuzOoayrexfOhJzNx7GR+uDJ3H7WO2inqdDhuMxQFmQmyA\n ZVQClosPYIzP2hlMmqnv7dTCfpeqCWBTcTuVusjOEipkpS9/F1enP11+EdA/UDr4xMUIeonvCwD\n gqk1sPcwOs2TQ7p7/tGzWlh5HZIGRIOODViZMb7EZDTWO4ojyT57/sX/bW+7GRHGHwjnbbWwudg\n 8lFzIrHsSgsIe3FBctEG6X/k6N6oukeDL3AoPgWCJa6zdpqsSJGf1StXooykZkixdXxuzZl/XHy\n tH/BlCoUlO7phy/TTOHGotkFEetvIuA9E6ZWkxCjK1O2X3FPNkEENNM0eDYuPtfQwdFXn8+o3D7\n 05NR0CWQKlPOtuYGbFEGZnt7sbMFpESKC52cXL2m/G24uICfB4BRUzYtAvdKUtyT8aEKig7xC6I\n 3tX9255z8dhnqCtGjGg==","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-05-04_03,2026-04-30_02,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n impostorscore=0 bulkscore=0 suspectscore=0 clxscore=1015 phishscore=0\n priorityscore=1501 malwarescore=0 spamscore=0 adultscore=0 lowpriorityscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605040107"},"content":"Add a DT binding document describing the TLMM pin controller available\non the Nord platforms from Qualcomm.\n\nCo-developed-by: Shawn Guo \nSigned-off-by: Shawn Guo \nReviewed-by: Krzysztof Kozlowski \nSigned-off-by: Bartosz Golaszewski \n---\n .../bindings/pinctrl/qcom,nord-tlmm.yaml | 141 +++++++++++++++++++++\n 1 file changed, 141 insertions(+)","diff":"diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml\nnew file mode 100644\nindex 0000000000000000000000000000000000000000..4bb511719f3130fc208011b4a8b45f4cfcde8c9b\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml\n@@ -0,0 +1,141 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/qcom,nord-tlmm.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Qualcomm Technologies, Inc. SA8797P TLMM block\n+\n+maintainers:\n+ - Bartosz Golaszewski \n+\n+description:\n+ Top Level Mode Multiplexer pin controller in Qualcomm SA8797P SoC.\n+\n+allOf:\n+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#\n+\n+properties:\n+ compatible:\n+ const: qcom,nord-tlmm\n+\n+ reg:\n+ maxItems: 1\n+\n+ interrupts:\n+ maxItems: 1\n+\n+ gpio-reserved-ranges:\n+ minItems: 1\n+ maxItems: 90\n+\n+ gpio-line-names:\n+ maxItems: 181\n+\n+patternProperties:\n+ \"-state$\":\n+ oneOf:\n+ - $ref: \"#/$defs/qcom-nord-tlmm-state\"\n+ - patternProperties:\n+ \"-pins$\":\n+ $ref: \"#/$defs/qcom-nord-tlmm-state\"\n+ additionalProperties: false\n+\n+$defs:\n+ qcom-nord-tlmm-state:\n+ type: object\n+ description:\n+ Pinctrl node's client devices use subnodes for desired pin configuration.\n+ Client device subnodes use below standard properties.\n+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state\n+ unevaluatedProperties: false\n+\n+ properties:\n+ pins:\n+ description:\n+ List of gpio pins affected by the properties specified in this\n+ subnode.\n+ items:\n+ oneOf:\n+ - pattern: \"^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|180)$\"\n+ - enum: [ ufs_reset ]\n+ minItems: 1\n+ maxItems: 16\n+\n+ function:\n+ description:\n+ Specify the alternative function to be configured for the specified\n+ pins.\n+\n+ enum: [ aoss_cti, atest_char, atest_usb20, atest_usb21,\n+ aud_intfc0_clk, aud_intfc0_data, aud_intfc0_ws,\n+ aud_intfc10_clk, aud_intfc10_data, aud_intfc10_ws,\n+ aud_intfc1_clk, aud_intfc1_data, aud_intfc1_ws,\n+ aud_intfc2_clk, aud_intfc2_data, aud_intfc2_ws,\n+ aud_intfc3_clk, aud_intfc3_data, aud_intfc3_ws,\n+ aud_intfc4_clk, aud_intfc4_data, aud_intfc4_ws,\n+ aud_intfc5_clk, aud_intfc5_data, aud_intfc5_ws,\n+ aud_intfc6_clk, aud_intfc6_data, aud_intfc6_ws,\n+ aud_intfc7_clk, aud_intfc7_data, aud_intfc7_ws,\n+ aud_intfc8_clk, aud_intfc8_data, aud_intfc8_ws,\n+ aud_intfc9_clk, aud_intfc9_data, aud_intfc9_ws,\n+ aud_mclk0_mira, aud_mclk0_mirb, aud_mclk1_mira, aud_mclk1_mirb,\n+ aud_mclk2_mira, aud_mclk2_mirb, aud_refclk0, aud_refclk1,\n+ bist_done, ccu_async_in, ccu_i2c_scl, ccu_i2c_sda, ccu_timer,\n+ clink_debug, dbg_out, dbg_out_clk,\n+ ddr_bist_complete, ddr_bist_fail, ddr_bist_start, ddr_bist_stop,\n+ ddr_pxi, dp_rx0, dp_rx00, dp_rx01, dp_rx0_mute, dp_rx1, dp_rx10,\n+ dp_rx11, dp_rx1_mute,\n+ edp0_hot, edp0_lcd, edp1_hot, edp1_lcd, edp2_hot, edp2_lcd,\n+ edp3_hot, edp3_lcd,\n+ emac0_mcg, emac0_mdc, emac0_mdio, emac0_ptp, emac1_mcg,\n+ emac1_mdc, emac1_mdio, emac1_ptp,\n+ gcc_gp1_clk, gcc_gp2_clk, gcc_gp3_clk, gcc_gp4_clk, gcc_gp5_clk,\n+ gcc_gp6_clk, gcc_gp7_clk, gcc_gp8_clk, jitter_bist, lbist_pass,\n+ mbist_pass, mdp0_vsync_out, mdp1_vsync_out, mdp_vsync_e,\n+ mdp_vsync_p, mdp_vsync_s,\n+ pcie0_clk_req_n, pcie1_clk_req_n, pcie2_clk_req_n,\n+ pcie3_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux,\n+ prng_rosc0, prng_rosc1, pwrbrk_i_n, qdss, qdss_cti, qspi,\n+ qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, qup0_se5,\n+ qup1_se0, qup1_se1, qup1_se3, qup1_se2, qup1_se4, qup1_se5,\n+ qup1_se6, qup2_se0, qup2_se1, qup2_se2, qup2_se3, qup2_se4,\n+ qup2_se5, qup2_se6,\n+ sailss_ospi, sdc4_clk, sdc4_cmd, sdc4_data, smb_alert,\n+ smb_alert_n, smb_clk, smb_dat, tb_trig_sdc4, tmess_prng0,\n+ tmess_prng1, tsc_timer, tsense_pwm, usb0_hs,\n+ usb0_phy_ps, usb1_hs, usb1_phy_ps, usb2_hs, usxgmii0_phy,\n+ usxgmii1_phy, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl]\n+\n+ required:\n+ - pins\n+\n+required:\n+ - compatible\n+ - reg\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ #include \n+\n+ tlmm: pinctrl@f100000 {\n+ compatible = \"qcom,nord-tlmm\";\n+ reg = <0x0f100000 0xc0000>;\n+ interrupts = ;\n+ gpio-controller;\n+ #gpio-cells = <2>;\n+ interrupt-controller;\n+ #interrupt-cells = <2>;\n+ gpio-ranges = <&tlmm 0 0 181>;\n+ wakeup-parent = <&pdc>;\n+\n+ qup_uart15_default: qup-uart15-default-state {\n+ pins = \"gpio147\", \"gpio148\";\n+ function = \"qup2_se2\";\n+ drive-strength = <2>;\n+ bias-disable;\n+ };\n+ };\n+...\n","prefixes":["v4","1/2"]}