{"id":2232034,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2232034/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260502101319.2364052-5-inochiama@gmail.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.1/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260502101319.2364052-5-inochiama@gmail.com>","date":"2026-05-02T10:13:17","name":"[4/5] dt-bindings: pci: spacemit: Introduce Spacemit K3 PCIe host controller","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"465b1ddfaf01c8410ad5719dc9c0e8dbede25d39","submitter":{"id":89342,"url":"http://patchwork.ozlabs.org/api/1.1/people/89342/?format=json","name":"Inochi Amaoto","email":"inochiama@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260502101319.2364052-5-inochiama@gmail.com/mbox/","series":[{"id":502524,"url":"http://patchwork.ozlabs.org/api/1.1/series/502524/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=502524","date":"2026-05-02T10:13:13","name":"riscv: spacemit: Add PCIe RC controller support for K3","version":1,"mbox":"http://patchwork.ozlabs.org/series/502524/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2232034/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2232034/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=AZKTfUwB;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=104.64.211.4; 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The controller uses the external MSI interrupt\n+ controller.\n+\n+allOf:\n+ - $ref: /schemas/pci/pci-host-bridge.yaml#\n+ - $ref: /schemas/pci/snps,dw-pcie.yaml#\n+\n+properties:\n+ compatible:\n+ const: spacemit,k3-pcie\n+\n+ reg:\n+ items:\n+ - description: DesignWare PCIe registers\n+ - description: Data Bus Interface (DBI) shadow registers\n+ - description: ATU address space\n+ - description: PCIe configuration space\n+ - description: Link control registers\n+\n+ reg-names:\n+ items:\n+ - const: dbi\n+ - const: dbi2\n+ - const: atu\n+ - const: config\n+ - const: link\n+\n+ clocks:\n+ items:\n+ - description: DWC PCIe Data Bus Interface (DBI) clock\n+ - description: DWC PCIe application AXI-bus master interface clock\n+ - description: DWC PCIe application AXI-bus slave interface clock\n+\n+ clock-names:\n+ items:\n+ - const: dbi\n+ - const: mstr\n+ - const: slv\n+\n+ resets:\n+ items:\n+ - description: DWC PCIe Data Bus Interface (DBI) reset\n+ - description: DWC PCIe application AXI-bus master interface reset\n+ - description: DWC PCIe application AXI-bus slave interface reset\n+\n+ reset-names:\n+ items:\n+ - const: dbi\n+ - const: mstr\n+ - const: slv\n+\n+ interrupts:\n+ items:\n+ - description: Interrupt used for port state\n+\n+ interrupt-names:\n+ const: app\n+\n+ msi-parent: true\n+\n+ phys:\n+ minItems: 1\n+ maxItems: 6\n+\n+ phy-names:\n+ minItems: 1\n+ maxItems: 6\n+\n+ spacemit,apmu:\n+ $ref: /schemas/types.yaml#/definitions/phandle-array\n+ description:\n+ A phandle that refers to the APMU system controller, whose regmap is\n+ used in managing resets and link state, along with and offset of its\n+ reset control register.\n+ items:\n+ - items:\n+ - description: phandle to APMU system controller\n+ - description: register offset\n+\n+required:\n+ - clocks\n+ - clock-names\n+ - resets\n+ - reset-names\n+ - interrupts\n+ - interrupt-names\n+ - msi-parent\n+ - spacemit,apmu\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ #include \n+\n+ soc {\n+ #address-cells = <2>;\n+ #size-cells = <2>;\n+\n+ pcie@80000000 {\n+ compatible = \"spacemit,k3-pcie\";\n+ reg = <0x0 0x80000000 0x0 0x00001000>,\n+ <0x0 0x80100000 0x0 0x00001000>,\n+ <0x0 0x80300000 0x0 0x00003f20>,\n+ <0x11 0x00000000 0x0 0x00010000>,\n+ <0x0 0x82900000 0x0 0x00001000>;\n+ reg-names = \"dbi\", \"dbi2\", \"atu\", \"config\", \"link\";\n+ device_type = \"pci\";\n+ #address-cells = <3>;\n+ #size-cells = <2>;\n+ clocks = <&syscon_apmu 89>,\n+ <&syscon_apmu 56>,\n+ <&syscon_apmu 57>;\n+ clock-names = \"dbi\", \"mstr\", \"slv\";\n+ interrupts = <141 IRQ_TYPE_LEVEL_HIGH>;\n+ interrupt-names = \"app\";\n+ msi-parent = <&simsic>;\n+ ranges = <0x01000000 0x00 0x00010000 0x11 0x00010000 0x0 0x00100000>,\n+ <0x02000000 0x0 0x00110000 0x11 0x00110000 0x0 0x7fef0000>,\n+ <0x43000000 0x18 0x00000000 0x18 0x00000000 0x1 0x00000000>;\n+ resets = <&syscon_apmu 76>,\n+ <&syscon_apmu 78>,\n+ <&syscon_apmu 77>;\n+ reset-names = \"dbi\", \"mstr\", \"slv\";\n+ linux,pci-domain = <0>;\n+ spacemit,apmu = <&syscon_apmu 0x1f0>;\n+ };\n+ };\n+\n","prefixes":["4/5"]}