{"id":2231895,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2231895/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/7-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/1.1/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<7-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>","date":"2026-05-01T14:29:16","name":"[7/9] iommu/arm-smmu-v3: Directly encode CMDQ_OP_ATC_INV","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"343c494716fb059ba61ffe764adad1ae7f778c55","submitter":{"id":79424,"url":"http://patchwork.ozlabs.org/api/1.1/people/79424/?format=json","name":"Jason Gunthorpe","email":"jgg@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/7-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com/mbox/","series":[{"id":502465,"url":"http://patchwork.ozlabs.org/api/1.1/series/502465/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/list/?series=502465","date":"2026-05-01T14:29:09","name":"Remove SMMUv3 struct arm_smmu_cmdq_ent","version":1,"mbox":"http://patchwork.ozlabs.org/series/502465/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2231895/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2231895/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n 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header.d=nvidia.com; arc=none"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=uNjJ5QHnutlgt5Uk9IPWdQzl2DOPiAyg06fxlD64Ep0=;\n b=khV++btLMqnYLVeW3aLdYV4itK/Xv60G8nUNi7yVXqx90bjn3bj2ECaZ5pXBDujl7ltQjB9tVh4cb3wh/MVRfuYI4+LX+KE11Gh6QwLEGc3Ah9F+hQri1r9GBhJiaEf+3SnYT5Lm4oX/4DdZtjAP0reX3esRR8Y8LTzWz+i7Ilanh+UopDJewt2hpgrjQfEQVTSxVl8iKIxX0neyoEXBElyNGm6PtVUwjfvpn2B9tQQav0ueDKBTZZjBjU9KfwfGcUqwG0a73Rm3tY/7/QHeBZIwe/oG5mmEcOEA2r6sHFOI/VeA0eiyJTSRhuLWqCVQyxV79jwgJaAABovhxSfmBA==","From":"Jason Gunthorpe ","To":"iommu@lists.linux.dev,\n\tJonathan Hunter ,\n\tJoerg Roedel ,\n\tlinux-arm-kernel@lists.infradead.org,\n\tlinux-tegra@vger.kernel.org,\n\tRobin Murphy ,\n\tThierry Reding ,\n\tKrishna Reddy ,\n\tWill Deacon ","Cc":"David Matlack ,\n\tPasha Tatashin ,\n\tpatches@lists.linux.dev,\n\tSamiullah Khawaja ,\n\tMostafa Saleh ","Subject":"[PATCH 7/9] iommu/arm-smmu-v3: Directly encode CMDQ_OP_ATC_INV","Date":"Fri, 1 May 2026 11:29:16 -0300","Message-ID":"<7-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>","In-Reply-To":"<0-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com>","References":"","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-ClientProxiedBy":"BL1P221CA0039.NAMP221.PROD.OUTLOOK.COM\n (2603:10b6:208:5b5::17) To LV8PR12MB9620.namprd12.prod.outlook.com\n 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9da3e7b2-ecc3-4348-e963-08dea78e09e1","X-MS-Exchange-CrossTenant-AuthSource":"LV8PR12MB9620.namprd12.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"01 May 2026 14:29:22.9672\n (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"43083d15-7273-40c1-b7db-39efd9ccc17a","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n DWk6GsbMv0Ftd2rhPInw2Qtt0CSgcN5NNa/gU1UIjkQcdaxMSpV34MlNiedPJFB8","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"SA1PR12MB8096"},"content":"Add a new command make function and convert all the places using\nATC_INV.\n\nSplit out full invalidation to directly make the cmd instead of\noverloading size=0 to mean full invalidation.\n\nSigned-off-by: Jason Gunthorpe \n---\n drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 59 ++++++++-------------\n drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 27 +++++++---\n 2 files changed, 40 insertions(+), 46 deletions(-)","diff":"diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\nindex f9c25ca9a9e7b8..0cdf0752ff6d62 100644\n--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\n+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c\n@@ -308,14 +308,6 @@ static int arm_smmu_cmdq_build_cmd(struct arm_smmu_cmd *cmd_out,\n \tcase CMDQ_OP_TLBI_EL2_ASID:\n \t\tcmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid);\n \t\tbreak;\n-\tcase CMDQ_OP_ATC_INV:\n-\t\tcmd[0] |= FIELD_PREP(CMDQ_0_SSV, ent->substream_valid);\n-\t\tcmd[0] |= FIELD_PREP(CMDQ_ATC_0_GLOBAL, ent->atc.global);\n-\t\tcmd[0] |= FIELD_PREP(CMDQ_ATC_0_SSID, ent->atc.ssid);\n-\t\tcmd[0] |= FIELD_PREP(CMDQ_ATC_0_SID, ent->atc.sid);\n-\t\tcmd[1] |= FIELD_PREP(CMDQ_ATC_1_SIZE, ent->atc.size);\n-\t\tcmd[1] |= ent->atc.addr & CMDQ_ATC_1_ADDR_MASK;\n-\t\tbreak;\n \tcase CMDQ_OP_CMD_SYNC:\n \t\tif (ent->sync.msiaddr) {\n \t\t\tcmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_IRQ);\n@@ -2371,9 +2363,8 @@ static irqreturn_t arm_smmu_combined_irq_handler(int irq, void *dev)\n \treturn IRQ_WAKE_THREAD;\n }\n \n-static void\n-arm_smmu_atc_inv_to_cmd(int ssid, unsigned long iova, size_t size,\n-\t\t\tstruct arm_smmu_cmdq_ent *cmd)\n+static struct arm_smmu_cmd\n+arm_smmu_atc_inv_to_cmd(u32 sid, int ssid, unsigned long iova, size_t size)\n {\n \tsize_t log2_span;\n \tsize_t span_mask;\n@@ -2395,17 +2386,6 @@ arm_smmu_atc_inv_to_cmd(int ssid, unsigned long iova, size_t size,\n \t * This has the unpleasant side-effect of invalidating all PASID-tagged\n \t * ATC entries within the address range.\n \t */\n-\t*cmd = (struct arm_smmu_cmdq_ent) {\n-\t\t.opcode\t\t\t= CMDQ_OP_ATC_INV,\n-\t\t.substream_valid\t= (ssid != IOMMU_NO_PASID),\n-\t\t.atc.ssid\t\t= ssid,\n-\t};\n-\n-\tif (!size) {\n-\t\tcmd->atc.size = ATC_INV_SIZE_ALL;\n-\t\treturn;\n-\t}\n-\n \tpage_start\t= iova >> inval_grain_shift;\n \tpage_end\t= (iova + size - 1) >> inval_grain_shift;\n \n@@ -2434,24 +2414,25 @@ arm_smmu_atc_inv_to_cmd(int ssid, unsigned long iova, size_t size,\n \n \tpage_start\t&= ~span_mask;\n \n-\tcmd->atc.addr\t= page_start << inval_grain_shift;\n-\tcmd->atc.size\t= log2_span;\n+\treturn arm_smmu_make_cmd_atc_inv(sid, ssid,\n+\t\t\t\t\t page_start << inval_grain_shift,\n+\t\t\t\t\t log2_span);\n }\n \n static int arm_smmu_atc_inv_master(struct arm_smmu_master *master,\n \t\t\t\t ioasid_t ssid)\n {\n \tint i;\n-\tstruct arm_smmu_cmdq_ent cmd;\n+\tstruct arm_smmu_cmd cmd;\n \tstruct arm_smmu_cmdq_batch cmds;\n \n-\tarm_smmu_atc_inv_to_cmd(ssid, 0, 0, &cmd);\n-\n-\tarm_smmu_cmdq_batch_init(master->smmu, &cmds, &cmd);\n-\tfor (i = 0; i < master->num_streams; i++) {\n-\t\tcmd.atc.sid = master->streams[i].id;\n-\t\tarm_smmu_cmdq_batch_add(master->smmu, &cmds, &cmd);\n-\t}\n+\tcmd = arm_smmu_make_cmd_atc_inv_all(0, IOMMU_NO_PASID);\n+\tarm_smmu_cmdq_batch_init_cmd(master->smmu, &cmds, &cmd);\n+\tfor (i = 0; i < master->num_streams; i++)\n+\t\tarm_smmu_cmdq_batch_add_cmd(\n+\t\t\tmaster->smmu, &cmds,\n+\t\t\tarm_smmu_make_cmd_atc_inv_all(master->streams[i].id,\n+\t\t\t\t\t\t ssid));\n \n \treturn arm_smmu_cmdq_batch_submit(master->smmu, &cmds);\n }\n@@ -2650,14 +2631,16 @@ static void __arm_smmu_domain_inv_range(struct arm_smmu_invs *invs,\n \t\t\tarm_smmu_cmdq_batch_add(smmu, &cmds, &cmd);\n \t\t\tbreak;\n \t\tcase INV_TYPE_ATS:\n-\t\t\tarm_smmu_atc_inv_to_cmd(cur->ssid, iova, size, &cmd);\n-\t\t\tcmd.atc.sid = cur->id;\n-\t\t\tarm_smmu_cmdq_batch_add(smmu, &cmds, &cmd);\n+\t\t\tarm_smmu_cmdq_batch_add_cmd(\n+\t\t\t\tsmmu, &cmds,\n+\t\t\t\tarm_smmu_atc_inv_to_cmd(cur->id, cur->ssid,\n+\t\t\t\t\t\t\tiova, size));\n \t\t\tbreak;\n \t\tcase INV_TYPE_ATS_FULL:\n-\t\t\tarm_smmu_atc_inv_to_cmd(IOMMU_NO_PASID, 0, 0, &cmd);\n-\t\t\tcmd.atc.sid = cur->id;\n-\t\t\tarm_smmu_cmdq_batch_add(smmu, &cmds, &cmd);\n+\t\t\tarm_smmu_cmdq_batch_add_cmd(\n+\t\t\t\tsmmu, &cmds,\n+\t\t\t\tarm_smmu_make_cmd_atc_inv_all(cur->id,\n+\t\t\t\t\t\t\t IOMMU_NO_PASID));\n \t\t\tbreak;\n \t\tdefault:\n \t\t\tWARN_ON_ONCE(1);\ndiff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\nindex 10b3d95d9ee660..194f73cabef5c9 100644\n--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\n+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h\n@@ -552,6 +552,25 @@ static inline struct arm_smmu_cmd arm_smmu_make_cmd_pri_resp(u32 sid, u32 ssid,\n \treturn cmd;\n }\n \n+static inline struct arm_smmu_cmd arm_smmu_make_cmd_atc_inv(u32 sid, u32 ssid,\n+\t\t\t\t\t\t\t u64 addr, u8 size)\n+{\n+\tstruct arm_smmu_cmd cmd = arm_smmu_make_cmd_op(CMDQ_OP_ATC_INV);\n+\n+\tcmd.data[0] |= FIELD_PREP(CMDQ_0_SSV, ssid != IOMMU_NO_PASID) |\n+\t\t FIELD_PREP(CMDQ_ATC_0_SSID, ssid) |\n+\t\t FIELD_PREP(CMDQ_ATC_0_SID, sid);\n+\tcmd.data[1] |= FIELD_PREP(CMDQ_ATC_1_SIZE, size) |\n+\t\t (addr & CMDQ_ATC_1_ADDR_MASK);\n+\treturn cmd;\n+}\n+\n+static inline struct arm_smmu_cmd arm_smmu_make_cmd_atc_inv_all(u32 sid,\n+\t\t\t\t\t\t\t\tu32 ssid)\n+{\n+\treturn arm_smmu_make_cmd_atc_inv(sid, ssid, 0, ATC_INV_SIZE_ALL);\n+}\n+\n /* Event queue */\n #define EVTQ_ENT_SZ_SHIFT\t\t5\n #define EVTQ_ENT_DWORDS\t\t\t((1 << EVTQ_ENT_SZ_SHIFT) >> 3)\n@@ -630,14 +649,6 @@ struct arm_smmu_cmdq_ent {\n \t\t\tu64\t\t\taddr;\n \t\t} tlbi;\n \n-\t\tstruct {\n-\t\t\tu32\t\t\tsid;\n-\t\t\tu32\t\t\tssid;\n-\t\t\tu64\t\t\taddr;\n-\t\t\tu8\t\t\tsize;\n-\t\t\tbool\t\t\tglobal;\n-\t\t} atc;\n-\n \t\tstruct {\n \t\t\tu64\t\t\tmsiaddr;\n \t\t} sync;\n","prefixes":["7/9"]}