{"id":2231710,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2231710/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260501101505.3485916-25-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260501101505.3485916-25-peter.maydell@linaro.org>","date":"2026-05-01T10:15:01","name":"[PULL,24/28] target/arm: hvf: pass through CNTHCTL_EL2 and MDCCINT_EL1","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"c372af22d215f63aeb977260439648276eb33ba2","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/1.1/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260501101505.3485916-25-peter.maydell@linaro.org/mbox/","series":[{"id":502437,"url":"http://patchwork.ozlabs.org/api/1.1/series/502437/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502437","date":"2026-05-01T10:14:41","name":"[PULL,01/28] hw/arm/fsl-imx8mp: Do not create redundant unimplemented devices","version":1,"mbox":"http://patchwork.ozlabs.org/series/502437/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2231710/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2231710/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Qiniast3;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g6Rl42t5Bz1xqf\n\tfor ; Fri, 01 May 2026 20:16:00 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wIkuQ-00047B-5y; Fri, 01 May 2026 06:15:46 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wIkuJ-00042y-C6\n for qemu-devel@nongnu.org; Fri, 01 May 2026 06:15:39 -0400","from mail-wm1-x330.google.com ([2a00:1450:4864:20::330])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wIkuH-0000FA-Ml\n for qemu-devel@nongnu.org; Fri, 01 May 2026 06:15:39 -0400","by mail-wm1-x330.google.com with SMTP id\n 5b1f17b1804b1-488ab2db91aso21250545e9.3\n for ; Fri, 01 May 2026 03:15:37 -0700 (PDT)","from lanath.. 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For nested guests, HVF traps accesses to MDCCINT_EL1.\nPass through those accesses to the Hypervisor.framework library.\n\nSigned-off-by: Mohamed Mediouni \n\nReviewed-by: Philippe Mathieu-Daudé \nTested-by: Philippe Mathieu-Daudé \nMessage-id: 20260429190532.26538-12-mohamed@unpredictable.fr\nSigned-off-by: Peter Maydell \n---\n target/arm/hvf/hvf.c | 20 ++++++++++++++++++++\n 1 file changed, 20 insertions(+)","diff":"diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c\nindex ecfe06cd8c..1894be6b0e 100644\n--- a/target/arm/hvf/hvf.c\n+++ b/target/arm/hvf/hvf.c\n@@ -296,6 +296,10 @@ void hvf_arm_init_debug(void)\n #define SYSREG_DBGWVR15_EL1 SYSREG(2, 0, 0, 15, 6)\n #define SYSREG_DBGWCR15_EL1 SYSREG(2, 0, 0, 15, 7)\n \n+/* EL2 registers */\n+#define SYSREG_CNTHCTL_EL2 SYSREG(3, 4, 14, 1, 0)\n+#define SYSREG_MDCCINT_EL1 SYSREG(2, 0, 0, 2, 0)\n+\n #define WFX_IS_WFE (1 << 0)\n \n #define TMR_CTL_ENABLE (1 << 0)\n@@ -1719,6 +1723,14 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint64_t *val)\n case SYSREG_OSDLR_EL1:\n /* Dummy register */\n return 0;\n+ case SYSREG_CNTHCTL_EL2:\n+ if (__builtin_available(macOS 15.0, *)) {\n+ assert_hvf_ok(hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTHCTL_EL2, val));\n+ }\n+ return 0;\n+ case SYSREG_MDCCINT_EL1:\n+ assert_hvf_ok(hv_vcpu_get_sys_reg(cpu->accel->fd, HV_SYS_REG_MDCCINT_EL1, val));\n+ return 0;\n case SYSREG_ICC_AP0R0_EL1:\n case SYSREG_ICC_AP0R1_EL1:\n case SYSREG_ICC_AP0R2_EL1:\n@@ -2007,6 +2019,14 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)\n case SYSREG_OSDLR_EL1:\n /* Dummy register */\n return 0;\n+ case SYSREG_CNTHCTL_EL2:\n+ if (__builtin_available(macOS 15.0, *)) {\n+ assert_hvf_ok(hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_CNTHCTL_EL2, val));\n+ }\n+ return 0;\n+ case SYSREG_MDCCINT_EL1:\n+ assert_hvf_ok(hv_vcpu_set_sys_reg(cpu->accel->fd, HV_SYS_REG_MDCCINT_EL1, val));\n+ return 0;\n case SYSREG_LORC_EL1:\n /* Dummy register */\n return 0;\n","prefixes":["PULL","24/28"]}