{"id":2231043,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2231043/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430093810.2762539-12-peter.maydell@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260430093810.2762539-12-peter.maydell@linaro.org>","date":"2026-04-30T09:37:56","name":"[v2,11/25] hw/core: Update docs for get_phys_addr_{attrs_, }debug","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"8d0826d1a6c7fff8679a278254550cefd5ab912d","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/1.1/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430093810.2762539-12-peter.maydell@linaro.org/mbox/","series":[{"id":502257,"url":"http://patchwork.ozlabs.org/api/1.1/series/502257/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502257","date":"2026-04-30T09:37:47","name":"Handle sub-page granularity in cpu_memory_rw_debug()","version":2,"mbox":"http://patchwork.ozlabs.org/series/502257/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2231043/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2231043/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=TxeOGuD3;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5q6z4RZ4z1yHZ\n\tfor ; Thu, 30 Apr 2026 19:46:03 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wINrE-0005Hc-3n; Thu, 30 Apr 2026 05:38:56 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wINr0-0004nT-4R\n for qemu-devel@nongnu.org; Thu, 30 Apr 2026 05:38:42 -0400","from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wINqm-0002YX-4f\n for qemu-devel@nongnu.org; Thu, 30 Apr 2026 05:38:40 -0400","by mail-wr1-x42a.google.com with SMTP id\n ffacd0b85a97d-44261378651so1184183f8f.0\n for ; Thu, 30 Apr 2026 02:38:27 -0700 (PDT)","from lanath.. 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Iglesias\" ,\n Jiaxun Yang , Nicholas Piggin ,\n Chinmay Rath , Glenn Miles ,\n Palmer Dabbelt ,\n Alistair Francis , Weiwei Li ,\n Daniel Henrique Barboza ,\n Liu Zhiwei ,\n Chao Liu , Ilya Leoshkevich ,\n David Hildenbrand ,\n Mark Cave-Ayland ,\n Artyom Tarasenko , Max Filippov ","Subject":"[PATCH v2 11/25] hw/core: Update docs for get_phys_addr_{attrs_,\n }debug","Date":"Thu, 30 Apr 2026 10:37:56 +0100","Message-ID":"<20260430093810.2762539-12-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260430093810.2762539-1-peter.maydell@linaro.org>","References":"<20260430093810.2762539-1-peter.maydell@linaro.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::42a;\n envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Update the documentation for the get_phys_addr_{attrs_,}debug methods\nand wrapper functions to state that they can handle non-page aligned\naddresses and will return the corresponding exact physaddr for them.\n\nSigned-off-by: Peter Maydell \nReviewed-by: Philippe Mathieu-Daudé \nMessage-id: 20260417173105.1648172-11-peter.maydell@linaro.org\n---\n include/hw/core/cpu.h | 16 +++++++++++-----\n include/hw/core/sysemu-cpu-ops.h | 4 ++++\n 2 files changed, 15 insertions(+), 5 deletions(-)","diff":"diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h\nindex 9d6b4fd697..730876b7b8 100644\n--- a/include/hw/core/cpu.h\n+++ b/include/hw/core/cpu.h\n@@ -746,15 +746,18 @@ void cpu_dump_state(CPUState *cpu, FILE *f, int flags);\n \n /**\n * cpu_get_phys_addr_attrs_debug:\n- * @cpu: The CPU to obtain the physical page address for.\n+ * @cpu: The CPU to use for the virtual-to-physical translation\n * @addr: The virtual address.\n * @attrs: Updated on return with the memory transaction attributes to use\n * for this access.\n *\n- * Obtains the physical page corresponding to a virtual one, together\n+ * Obtains the physical address corresponding to a virtual one, together\n * with the corresponding memory transaction attributes to use for the access.\n * Use it only for debugging because no protection checks are done.\n *\n+ * The address need not be page-aligned; the returned address will\n+ * be the physical address corresponding to that virtual address.\n+ *\n * Returns: Corresponding physical page address or -1 if no page found.\n */\n hwaddr cpu_get_phys_addr_attrs_debug(CPUState *cpu, vaddr addr,\n@@ -762,13 +765,16 @@ hwaddr cpu_get_phys_addr_attrs_debug(CPUState *cpu, vaddr addr,\n \n /**\n * cpu_get_phys_addr_debug:\n- * @cpu: The CPU to obtain the physical page address for.\n+ * @cpu: The CPU to use for the virtual-to-physical translation\n * @addr: The virtual address.\n *\n- * Obtains the physical page corresponding to a virtual one.\n+ * Obtains the physical address corresponding to a virtual one.\n * Use it only for debugging because no protection checks are done.\n *\n- * Returns: Corresponding physical page address or -1 if no page found.\n+ * The address need not be page-aligned; the returned address will\n+ * be the physical address corresponding to that virtual address.\n+ *\n+ * Returns: Corresponding physical address, or -1 if no page found.\n */\n hwaddr cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);\n \ndiff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h\nindex a4fc330bea..a87c55d922 100644\n--- a/include/hw/core/sysemu-cpu-ops.h\n+++ b/include/hw/core/sysemu-cpu-ops.h\n@@ -31,6 +31,8 @@ typedef struct SysemuCPUOps {\n bool (*get_paging_enabled)(const CPUState *cpu);\n /**\n * @get_phys_addr_debug: Callback for obtaining a physical address.\n+ * This must be able to handle a non-page-aligned address, and will\n+ * return the physical address corresponding to that address.\n */\n hwaddr (*get_phys_addr_debug)(CPUState *cpu, vaddr addr);\n /**\n@@ -39,6 +41,8 @@ typedef struct SysemuCPUOps {\n * access.\n * CPUs which use memory transaction attributes should implement this\n * instead of get_phys_addr_debug.\n+ * This must be able to handle a non-page-aligned address, and will\n+ * return the physical address corresponding to that address.\n */\n hwaddr (*get_phys_addr_attrs_debug)(CPUState *cpu, vaddr addr,\n MemTxAttrs *attrs);\n","prefixes":["v2","11/25"]}