{"id":2231005,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2231005/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-ppc/patch/20260430093810.2762539-5-peter.maydell@linaro.org/","project":{"id":69,"url":"http://patchwork.ozlabs.org/api/1.1/projects/69/?format=json","name":"QEMU powerpc development","link_name":"qemu-ppc","list_id":"qemu-ppc.nongnu.org","list_email":"qemu-ppc@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260430093810.2762539-5-peter.maydell@linaro.org>","date":"2026-04-30T09:37:49","name":"[v2,04/25] target/microblaze: Make get_phys_page_attrs_debug handle non-page-aligned addrs","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"6b5f8d77fc781385055b14e4385d7e48f8decbfc","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/1.1/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-ppc/patch/20260430093810.2762539-5-peter.maydell@linaro.org/mbox/","series":[{"id":502256,"url":"http://patchwork.ozlabs.org/api/1.1/series/502256/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-ppc/list/?series=502256","date":"2026-04-30T09:37:46","name":"Handle sub-page granularity in cpu_memory_rw_debug()","version":2,"mbox":"http://patchwork.ozlabs.org/series/502256/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2231005/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2231005/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=wYzPFoAU;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5q0B56rRz1xqf\n\tfor ; Thu, 30 Apr 2026 19:40:10 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wINqq-0004gA-Ie; Thu, 30 Apr 2026 05:38:32 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wINqk-0004b2-P4\n for qemu-ppc@nongnu.org; Thu, 30 Apr 2026 05:38:26 -0400","from mail-wr1-x435.google.com ([2a00:1450:4864:20::435])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wINqg-0002Td-BT\n for qemu-ppc@nongnu.org; Thu, 30 Apr 2026 05:38:26 -0400","by mail-wr1-x435.google.com with SMTP id\n ffacd0b85a97d-446fea16729so636337f8f.3\n for ; Thu, 30 Apr 2026 02:38:18 -0700 (PDT)","from lanath.. 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Iglesias\" ,\n Jiaxun Yang , Nicholas Piggin ,\n Chinmay Rath , Glenn Miles ,\n Palmer Dabbelt ,\n Alistair Francis , Weiwei Li ,\n Daniel Henrique Barboza ,\n Liu Zhiwei ,\n Chao Liu , Ilya Leoshkevich ,\n David Hildenbrand ,\n Mark Cave-Ayland ,\n Artyom Tarasenko , Max Filippov ","Subject":"[PATCH v2 04/25] target/microblaze: Make get_phys_page_attrs_debug\n handle non-page-aligned addrs","Date":"Thu, 30 Apr 2026 10:37:49 +0100","Message-ID":"<20260430093810.2762539-5-peter.maydell@linaro.org>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260430093810.2762539-1-peter.maydell@linaro.org>","References":"<20260430093810.2762539-1-peter.maydell@linaro.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::435;\n envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-ppc@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Currently our implementations of SysemuCPUOps::get_phys_page_debug\nand SysemuCPUOps::get_phys_page_attrs_debug are a mix of \"accepts a\nnon-page-aligned virtual address and returns the corresponding\nnon-page-aligned physical address\" and \"only returns a page-aligned\nphysical address\". This is awkward for callsites, which in practice\nall want the physical address for an arbitrary virtual address and\nhave to work around the possibility of getting a page-aligned\naddress, and it doesn't account for protection being possibly on a\nsub-page-sized granularity. We want to standardize on the\nimplementation having to handle non-page-aligned addresses.\n\nFor microblaze, we just need to remove the explicit rounding down to\nthe page boundary that we were doing in\nmb_cpu_get_phys_page_attrs_debug() when calculating the output\nphysaddr from the results of the MMU lookup.\n\nSigned-off-by: Peter Maydell \nReviewed-by: Philippe Mathieu-Daudé \nReviewed-by: Richard Henderson \nMessage-id: 20260417173105.1648172-4-peter.maydell@linaro.org\n---\n target/microblaze/helper.c | 9 ++++-----\n 1 file changed, 4 insertions(+), 5 deletions(-)","diff":"diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c\nindex a1857b7217..da8abe063e 100644\n--- a/target/microblaze/helper.c\n+++ b/target/microblaze/helper.c\n@@ -284,7 +284,6 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,\n MemTxAttrs *attrs)\n {\n MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);\n- vaddr vaddr;\n hwaddr paddr = 0;\n MicroBlazeMMULookup lu;\n int mmu_idx = cpu_mmu_index(cs, false);\n@@ -297,12 +296,12 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,\n if (mmu_idx != MMU_NOMMU_IDX) {\n hit = mmu_translate(cpu, &lu, addr, 0, 0);\n if (hit) {\n- vaddr = addr & TARGET_PAGE_MASK;\n- paddr = lu.paddr + vaddr - lu.vaddr;\n+ paddr = lu.paddr + addr - lu.vaddr;\n } else\n paddr = 0; /* ???. */\n- } else\n- paddr = addr & TARGET_PAGE_MASK;\n+ } else {\n+ paddr = addr;\n+ }\n \n return paddr;\n }\n","prefixes":["v2","04/25"]}