{"id":2230989,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230989/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260430093422.74812-8-biju.das.jz@bp.renesas.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/1.1/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260430093422.74812-8-biju.das.jz@bp.renesas.com>","date":"2026-04-30T09:34:12","name":"[v4,7/7] pinctrl: renesas: rzg2l: Add support for clone channel control","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"b51975da8e046f998b12a536eeea9b9b458c4885","submitter":{"id":87968,"url":"http://patchwork.ozlabs.org/api/1.1/people/87968/?format=json","name":"Biju","email":"biju.das.au@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260430093422.74812-8-biju.das.jz@bp.renesas.com/mbox/","series":[{"id":502254,"url":"http://patchwork.ozlabs.org/api/1.1/series/502254/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=502254","date":"2026-04-30T09:34:06","name":"Add Renesas RZ/G3L PINCONTROL support","version":4,"mbox":"http://patchwork.ozlabs.org/series/502254/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230989/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230989/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=JEW7Wnnz;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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As per the RZ/G3L hardware manual, the clone channel\nsetting is to be done before the mux setting.\n\nSigned-off-by: Biju Das \n---\nv3->v4:\n * Started using an 8-bit pin mask instead of start and end pin indices,\n and combined multiple entries with the same port number and config\n using ORed values of BIT() and GENMASK(), thereby reducing table size.\n * Started using an 8-bit function mask instead of a function index, and\n got rid of the shared pin bit. This also provides info about the\n possible functions.\n * Dropped RZG3L_CLONE_CHANNEL_{PACK,DTAT,SHARED_PIN_MASK} macros.\n * Replaced RZG3L_CLONE_CHANNEL_CFG_PIN_{START,END}_MASK macro with\n RZG3L_CLONE_CHANNEL_PIN_MASK.\n * Replaced RZG3L_CLONE_CHANNEL_CFG_PORT_MASK macro with\n RZG3L_CLONE_CHANNEL_PORT_MASK.\n * Updated kernel doc comment for clone register from 'registers' to\n 'register'.\n * Dropped dynamic allocation for the clone register cache, instead using\n static allocation in struct rzg2l_pinctrl_reg_cache, as it is a single\n 32-bit register.\n * Replaced the LUT and for loop in rzg2l_pinctrl_set_clone_mode() with a\n simple switch statement.\n * Dropped the complex check to find the func match in\n rzg2l_pinctrl_set_clone_mode() by using pin_func_mask & BIT(func).\n * Dropped the inner for loop for finding a pin match in\n rzg2l_pinctrl_set_clone_mode() by using pin_mask & BIT(pin).\n * Dropped field_prep with \"val << bit\" in rzg2l_pinctrl_set_clone_mode()\n as val is just 0 or 1.\n * In rzg2l_pinctrl_probe(), replaced the temporary variable offset with\n &pctrl->clone_offset.\n * Replaced RZG3L_CLONE_CHANNEL_PIN_CFG_PACK with RZG3L_CLONE_CHANNEL_DATA,\n and replaced clone_pin_configs, n_clone_pins,\n r9a08g046_clone_channel_pin_cfg with clone_channel_data,\n n_clone_channel_data, and r9a08g046_clone_channel_data.\nv3:\n * New patch.\n---\n drivers/pinctrl/renesas/pinctrl-rzg2l.c | 181 ++++++++++++++++++++++++\n 1 file changed, 181 insertions(+)","diff":"diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c\nindex eff5fc081ec8..bed551fe332d 100644\n--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c\n+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c\n@@ -11,12 +11,14 @@\n #include \n #include \n #include \n+#include \n #include \n #include \n #include \n #include \n #include \n #include \n+#include \n #include \n #include \n \n@@ -152,6 +154,18 @@\n \t FIELD_PREP_CONST(VARIABLE_PIN_CFG_PORT_MASK, (port)) | \\\n \t FIELD_PREP_CONST(PIN_CFG_MASK, (cfg)))\n \n+#define RZG3L_CLONE_CHANNEL_PIN_MASK\tGENMASK(31, 24)\n+#define RZG3L_CLONE_CHANNEL_PORT_MASK\tGENMASK(23, 19)\n+#define RZG3L_CLONE_CHANNEL_BIT_MASK\tGENMASK(12, 9)\n+#define RZG3L_CLONE_CHANNEL_VAL_MASK\tBIT(8)\n+#define RZG3L_CLONE_CHANNEL_PFC_MASK\tGENMASK(7, 0)\n+#define RZG3L_CLONE_CHANNEL_DATA(port, pins, bit, val, pfc) \\\n+\t(FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_PIN_MASK, (pins)) | \\\n+\t FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_PORT_MASK, (port)) | \\\n+\t FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_BIT_MASK, (bit)) | \\\n+\t FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_VAL_MASK, (val)) | \\\n+\t FIELD_PREP_CONST(RZG3L_CLONE_CHANNEL_PFC_MASK, (pfc)))\n+\n #define P(off)\t\t\t(0x0000 + (off))\n #define PM(off)\t\t\t(0x0100 + (off) * 2)\n #define PMC(off)\t\t(0x0200 + (off))\n@@ -313,6 +327,8 @@ struct rzg2l_pinctrl_data {\n \tconst struct rzg2l_dedicated_configs *dedicated_pins;\n \tunsigned int n_port_pins;\n \tunsigned int n_dedicated_pins;\n+\tconst u32 *clone_channel_data;\n+\tunsigned int n_clone_channel_data;\n \tconst struct rzg2l_hwcfg *hwcfg;\n \tconst u64 *variable_pin_cfg;\n \tunsigned int n_variable_pin_cfg;\n@@ -350,6 +366,7 @@ struct rzg2l_pinctrl_pin_settings {\n * @smt: SMT registers cache\n * @sr: SR registers cache\n * @nod: NOD registers cache\n+ * @clone: Clone register cache\n * @sd_ch: SD_CH registers cache\n * @eth_poc: ET_POC registers cache\n * @other_poc: OTHER_POC register cache\n@@ -367,6 +384,7 @@ struct rzg2l_pinctrl_reg_cache {\n \tu32\t*smt[2];\n \tu32\t*sr[2];\n \tu32\t*nod[2];\n+\tu32\tclone;\n \tu8\tsd_ch[2];\n \tu8\teth_poc[2];\n \tu8\toen;\n@@ -385,6 +403,8 @@ struct rzg2l_pinctrl {\n \n \tstruct clk\t\t\t*clk;\n \n+\tstruct regmap\t\t\t*syscon;\n+\n \tstruct gpio_chip\t\tgpio_chip;\n \tstruct pinctrl_gpio_range\tgpio_range;\n \tDECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT);\n@@ -398,6 +418,7 @@ struct rzg2l_pinctrl {\n \tstruct rzg2l_pinctrl_reg_cache\t*cache;\n \tstruct rzg2l_pinctrl_reg_cache\t*dedicated_cache;\n \tatomic_t\t\t\twakeup_path;\n+\tu32\t\t\t\tclone_offset;\n };\n \n static const u16 available_ps[] = { 1800, 2500, 3300 };\n@@ -623,6 +644,45 @@ static int rzg2l_validate_pin(struct rzg2l_pinctrl *pctrl,\n \treturn 0;\n }\n \n+static int rzg2l_pinctrl_set_clone_mode(struct rzg2l_pinctrl *pctrl,\n+\t\t\t\t\tu8 port, u8 pin, u8 func)\n+{\n+\tunsigned int i;\n+\n+\tif (!pctrl->data->clone_channel_data)\n+\t\treturn 0;\n+\n+\tswitch (func) {\n+\tcase 2:\n+\tcase 4 ... 7:\n+\t\tbreak;\n+\tdefault:\n+\t\treturn 0;\n+\t}\n+\n+\tfor (i = 0; i < pctrl->data->n_clone_channel_data; i++) {\n+\t\tunsigned int pin_data = pctrl->data->clone_channel_data[i];\n+\t\tunsigned int pin_func_mask = FIELD_GET(RZG3L_CLONE_CHANNEL_PFC_MASK, pin_data);\n+\t\tunsigned int pin_mask = FIELD_GET(RZG3L_CLONE_CHANNEL_PIN_MASK, pin_data);\n+\t\tu32 bit, val;\n+\n+\t\tif (!(pin_func_mask & BIT(func)) ||\n+\t\t FIELD_GET(RZG3L_CLONE_CHANNEL_PORT_MASK, pin_data) != port)\n+\t\t\tcontinue;\n+\n+\t\tif (!(pin_mask & BIT(pin)))\n+\t\t\tcontinue;\n+\n+\t\tbit = FIELD_GET(RZG3L_CLONE_CHANNEL_BIT_MASK, pin_data);\n+\t\tval = FIELD_GET(RZG3L_CLONE_CHANNEL_VAL_MASK, pin_data);\n+\n+\t\treturn regmap_update_bits(pctrl->syscon, pctrl->clone_offset,\n+\t\t\t\t\t BIT(bit), val << bit);\n+\t}\n+\n+\treturn 0;\n+}\n+\n static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,\n \t\t\t\t u8 pin, u8 off, u8 func)\n {\n@@ -698,6 +758,10 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev,\n \t\tfunc = psel_val[i] - hwcfg->func_base;\n \t\tdev_dbg(pctrl->dev, \"port:%u pin: %u off:%x PSEL:%u\\n\", port, pin, off, func);\n \n+\t\tret = rzg2l_pinctrl_set_clone_mode(pctrl, port, pin, func);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n \t\trzg2l_pinctrl_set_pfc_mode(pctrl, pin, off, func);\n \t}\n \n@@ -2636,6 +2700,97 @@ static const struct rzg2l_dedicated_configs rzg3l_dedicated_pins[] = {\n \t (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },\n };\n \n+static const u32 r9a08g046_clone_channel_data[] = {\n+\t/* I2C ch2 Bit:0 Value:0 PFC:4 */\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PG, GENMASK(7, 6), 0, 0, BIT(4)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PH, GENMASK(3, 2), 0, 0, BIT(4)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PK, GENMASK(1, 0), 0, 0, BIT(4)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(5, 4) | GENMASK(1, 0), 0, 0, BIT(4)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PB, GENMASK(5, 4) | GENMASK(1, 0), 0, 0, BIT(4)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PC, GENMASK(1, 0), 0, 0, BIT(4)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(7, 6) | GENMASK(3, 2), 0, 0, BIT(4)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(7, 6) | GENMASK(3, 2), 0, 0, BIT(4)),\n+\t/* I2C ch2 Bit:0 Value:1 PFC:4 */\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(5, 4) | GENMASK(1, 0), 0, 1, BIT(4)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(6, 5) | GENMASK(2, 1), 0, 1, BIT(4)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(5, 4) | GENMASK(1, 0), 0, 1, BIT(4)),\n+\t/* I2C ch3 Bit:1 Value:0 PFC:4 */\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PF, GENMASK(1, 0), 1, 0, BIT(4)),\n+\t/* I2C ch3 Bit:1 Value:1 PFC:4 */\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_P2, GENMASK(1, 0), 1, 1, BIT(4)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, BIT(6) | GENMASK(3, 2), 1, 1, BIT(4)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(4, 3) | BIT(0), 1, 1, BIT(4)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(7, 6), 1, 1, BIT(4)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(3, 2), 1, 1, BIT(4)),\n+\t/* SCIF ch3 Bit:4 Value:0 PFC:{6,7} */\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PG, GENMASK(6, 4), 4, 0, BIT(6)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PH, GENMASK(5, 3), 4, 0, BIT(7)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(4, 2), 4, 0, BIT(7)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PB, GENMASK(5, 3), 4, 0, BIT(7)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(2, 0), 4, 0, BIT(7)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(3, 1), 4, 0, BIT(7)),\n+\t/* SCIF ch3 Bit:4 Value:1 PFC:7 */\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(2, 0), 4, 1, BIT(7)),\n+\t/* SCIF ch4 Bit:5 Value:0 PFC:7 */\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PK, GENMASK(2, 0), 5, 0, BIT(7)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(7, 5), 5, 0, BIT(7)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PB, GENMASK(7, 6), 5, 0, BIT(7)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PC, BIT(0), 5, 0, BIT(7)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(5, 3), 5, 0, BIT(7)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(6, 4), 5, 0, BIT(7)),\n+\t/* SCIF ch4 Bit:5 Value:1 PFC:7 */\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(5, 3), 5, 1, BIT(7)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(4, 2), 5, 1, BIT(7)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(7, 5), 5, 1, BIT(7)),\n+\t/* SCIF ch5 Bit:6 Value:0 PFC:7 */\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, BIT(7), 6, 0, BIT(7)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PF, GENMASK(1, 0), 6, 0, BIT(7)),\n+\t/* SCIF ch5 Bit:6 Value:1 PFC:7 */\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, BIT(6), 6, 1, BIT(7)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(6, 5) | GENMASK(1, 0), 6, 1, BIT(7)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(4, 2) | BIT(0), 6, 1, BIT(7)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(2, 0), 6, 1, BIT(7)),\n+\t/* RSPI ch1 Bit:8 Value:0 PFC:2 */\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PH, GENMASK(5, 0), 8, 0, BIT(2)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(7, 5), 8, 0, BIT(2)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(3, 0), 8, 0, BIT(2)),\n+\t/* RSPI ch1 Bit:8 Value:1 PFC:2 */\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(6, 0), 8, 1, BIT(2)),\n+\t/* RSPI ch2 Bit:9 Value:0 PFC:2 */\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(7, 4), 9, 0, BIT(2)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PF, GENMASK(2, 0), 9, 0, BIT(2)),\n+\t/* RSPI ch2 Bit:9 Value:1 PFC:2 */\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(6, 0), 9, 1, BIT(2)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, BIT(7), 9, 1, BIT(2)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(5, 0), 9, 1, BIT(2)),\n+\t/* RSCI ch1 Bit:12 Value:0 PFC:{5,6} shared pins based on RSCI mode */\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PG, GENMASK(3, 0), 12, 0, GENMASK(6, 5)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(3, 0), 12, 0, GENMASK(6, 5)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PB, GENMASK(7, 6), 12, 0, GENMASK(6, 5)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PC, GENMASK(1, 0), 12, 0, GENMASK(6, 5)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(7, 4), 12, 0, GENMASK(6, 5)),\n+\t/* RSCI ch1 Bit:12 Value:1 PFC:{5,6} shared pins based on RSCI mode */\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(3, 0), 12, 1, GENMASK(6, 5)),\n+\t/* RSCI ch2 Bit:13 Value:0 PFC:{5,6} shared pins based on RSCI mode */\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PH, GENMASK(3, 0), 13, 0, GENMASK(6, 5)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PK, GENMASK(3, 0), 13, 0, GENMASK(6, 5)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PA, GENMASK(7, 4), 13, 0, GENMASK(6, 5)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PD, GENMASK(3, 0), 13, 0, GENMASK(6, 5)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(3, 0), 13, 0, GENMASK(6, 5)),\n+\t/* RSCI ch2 Bit:13 Value:1 PFC:{5,6} shared pins based on RSCI mode */\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_P5, GENMASK(6, 4), 13, 1, GENMASK(6, 5)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(6, 5) | BIT(0), 13, 1, GENMASK(6, 5)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(7, 6) | GENMASK(1, 0), 13, 1, GENMASK(6, 5)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(1, 0), 13, 1, GENMASK(6, 5)),\n+\t/* RSCI ch3 Bit:14 Value:0 PFC:{5,6} shared pins based on RSCI mode */\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PE, GENMASK(7, 6), 14, 0, GENMASK(6, 5)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_PF, GENMASK(1, 0), 14, 0, GENMASK(6, 5)),\n+\t/* RSCI ch3 Bit:14 Value:1 PFC:{5,6} shared pins based on RSCI mode */\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_P6, GENMASK(4, 1), 14, 1, GENMASK(6, 5)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_P7, GENMASK(5, 2), 14, 1, GENMASK(6, 5)),\n+\tRZG3L_CLONE_CHANNEL_DATA(RZG3L_P8, GENMASK(5, 2), 14, 1, GENMASK(6, 5)),\n+};\n+\n static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl)\n {\n \tconst struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq];\n@@ -3222,6 +3377,16 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)\n \t\t\t\t \"failed to enable GPIO clk\\n\");\n \t}\n \n+\tif (pctrl->data->clone_channel_data) {\n+\t\tstruct device_node *np = pctrl->dev->of_node;\n+\n+\t\tpctrl->syscon = syscon_regmap_lookup_by_phandle_args(np, \"renesas,clonech\",\n+\t\t\t\t\t\t\t\t 1, &pctrl->clone_offset);\n+\t\tif (IS_ERR(pctrl->syscon))\n+\t\t\treturn dev_err_probe(pctrl->dev, PTR_ERR(pctrl->syscon),\n+\t\t\t\t\t \"Failed to parse renesas,clonech\\n\");\n+\t}\n+\n \traw_spin_lock_init(&pctrl->lock);\n \tspin_lock_init(&pctrl->bitmap_lock);\n \tmutex_init(&pctrl->mutex);\n@@ -3511,6 +3676,14 @@ static int rzg2l_pinctrl_suspend_noirq(struct device *dev)\n \tif (regs->other_poc)\n \t\tcache->other_poc = readb(pctrl->base + regs->other_poc);\n \n+\tif (pctrl->syscon) {\n+\t\tint ret;\n+\n+\t\tret = regmap_read(pctrl->syscon, pctrl->clone_offset, &cache->clone);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n \tif (!atomic_read(&pctrl->wakeup_path))\n \t\tclk_disable_unprepare(pctrl->clk);\n \telse\n@@ -3528,6 +3701,12 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev)\n \tunsigned long flags;\n \tint ret;\n \n+\tif (pctrl->syscon) {\n+\t\tret = regmap_write(pctrl->syscon, pctrl->clone_offset, cache->clone);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n \tif (!atomic_read(&pctrl->wakeup_path)) {\n \t\tret = clk_prepare_enable(pctrl->clk);\n \t\tif (ret)\n@@ -3742,6 +3921,8 @@ static struct rzg2l_pinctrl_data r9a08g046_data = {\n \t.dedicated_pins = rzg3l_dedicated_pins,\n \t.n_port_pins = ARRAY_SIZE(r9a08g046_gpio_configs) * RZG2L_PINS_PER_PORT,\n \t.n_dedicated_pins = ARRAY_SIZE(rzg3l_dedicated_pins),\n+\t.clone_channel_data = r9a08g046_clone_channel_data,\n+\t.n_clone_channel_data = ARRAY_SIZE(r9a08g046_clone_channel_data),\n \t.hwcfg = &rzg3l_hwcfg,\n \t.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,\n \t.pmc_writeb = &rzg2l_pmc_writeb,\n","prefixes":["v4","7/7"]}