{"id":2230985,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230985/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260430093422.74812-4-biju.das.jz@bp.renesas.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/1.1/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260430093422.74812-4-biju.das.jz@bp.renesas.com>","date":"2026-04-30T09:34:08","name":"[v4,3/7] pinctrl: renesas: rzg2l: Add support for selecting power source for {WDT,AWO,ISO}","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f626629b059eecd20d35f3b11db406b1f2c3fe5f","submitter":{"id":87968,"url":"http://patchwork.ozlabs.org/api/1.1/people/87968/?format=json","name":"Biju","email":"biju.das.au@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260430093422.74812-4-biju.das.jz@bp.renesas.com/mbox/","series":[{"id":502254,"url":"http://patchwork.ozlabs.org/api/1.1/series/502254/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=502254","date":"2026-04-30T09:34:06","name":"Add Renesas RZ/G3L PINCONTROL support","version":4,"mbox":"http://patchwork.ozlabs.org/series/502254/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230985/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230985/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=CVZ0T1kU;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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Update rzg2l_get_power_source() to extract the\nrelevant bit field via field_get() when reading OTHER_POC, and update\nrzg2l_set_power_source() to perform a read-modify-write under the\nspinlock when writing to OTHER_POC, since multiple domains share the\nsame register.\n\nSigned-off-by: Biju Das \n---\nv3->v4:\n * Updated commit description.\n * Updated rzg2l_caps_to_pwr_reg() to return mask in addition to register\n offset.\n * Dropped ffs(), using field_get() instead to get PoC offset in\n rzg2l_get_power_source().\n * Simplified rzg2l_set_power_source() by using mask from\n rzg2l_caps_to_pwr_reg().\n * Added scoped_guard() for RMW operation in rzg2l_set_power_source().\nv2->v3:\n * No change\nv1->v2:\n * No change\n---\n drivers/pinctrl/renesas/pinctrl-rzg2l.c | 53 ++++++++++++++++++++-----\n 1 file changed, 44 insertions(+), 9 deletions(-)","diff":"diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c\nindex ca9d4a3ec737..7b1bb66d4ff6 100644\n--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c\n+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c\n@@ -63,10 +63,18 @@\n #define PIN_CFG_SMT\t\t\tBIT(16)\t/* Schmitt-trigger input control */\n #define PIN_CFG_ELC\t\t\tBIT(17)\n #define PIN_CFG_IOLH_RZV2H\t\tBIT(18)\n+#define PIN_CFG_PVDD1833_OTH_AWO_POC\tBIT(19) /* known on RZ/G3L only */\n+#define PIN_CFG_PVDD1833_OTH_ISO_POC\tBIT(20) /* known on RZ/G3L only */\n+#define PIN_CFG_WDTOVF_N_POC\t\tBIT(21) /* known on RZ/G3L only */\n \n #define RZG2L_SINGLE_PIN\t\tBIT_ULL(63)\t/* Dedicated pin */\n #define RZG2L_VARIABLE_CFG\t\tBIT_ULL(62)\t/* Variable cfg for port pins */\n \n+#define PIN_CFG_OTHER_POC_MASK\t\\\n+\t\t\t\t\t(PIN_CFG_PVDD1833_OTH_AWO_POC | \\\n+\t\t\t\t\t PIN_CFG_PVDD1833_OTH_ISO_POC | \\\n+\t\t\t\t\t PIN_CFG_WDTOVF_N_POC)\n+\n #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \\\n \t\t\t\t\t(PIN_CFG_IOLH_##group | \\\n \t\t\t\t\t PIN_CFG_PUPD | \\\n@@ -146,6 +154,7 @@\n #define SD_CH(off, ch)\t\t((off) + (ch) * 4)\n #define ETH_POC(off, ch)\t((off) + (ch) * 4)\n #define QSPI\t\t\t(0x3008) /* known on RZ/{G2L,G2LC,G2UL,Five} only */\n+#define OTHER_POC\t\t(0x3028) /* known on RZ/G3L only */\n \n #define PVDD_2500\t\t2\t/* I/O domain voltage 2.5V */\n #define PVDD_1800\t\t1\t/* I/O domain voltage <= 1.8V */\n@@ -900,7 +909,8 @@ static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,\n \traw_spin_unlock_irqrestore(&pctrl->lock, flags);\n }\n \n-static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 caps)\n+static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs,\n+\t\t\t\t u32 caps, u8 *mask)\n {\n \tif (caps & PIN_CFG_IO_VMC_SD0)\n \t\treturn SD_CH(regs->sd_ch, 0);\n@@ -912,6 +922,16 @@ static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32\n \t\treturn ETH_POC(regs->eth_poc, 1);\n \tif (caps & PIN_CFG_IO_VMC_QSPI)\n \t\treturn QSPI;\n+\tif (caps & PIN_CFG_OTHER_POC_MASK) {\n+\t\tif (caps & PIN_CFG_PVDD1833_OTH_AWO_POC)\n+\t\t\t*mask = BIT(0);\n+\t\telse if (caps & PIN_CFG_PVDD1833_OTH_ISO_POC)\n+\t\t\t*mask = BIT(1);\n+\t\telse\n+\t\t\t*mask = BIT(2);\n+\n+\t\treturn OTHER_POC;\n+\t}\n \n \treturn -EINVAL;\n }\n@@ -920,17 +940,20 @@ static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps\n {\n \tconst struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;\n \tconst struct rzg2l_register_offsets *regs = &hwcfg->regs;\n+\tu8 val, mask;\n \tint pwr_reg;\n-\tu8 val;\n \n \tif (caps & PIN_CFG_SOFT_PS)\n \t\treturn pctrl->settings[pin].power_source;\n \n-\tpwr_reg = rzg2l_caps_to_pwr_reg(regs, caps);\n+\tpwr_reg = rzg2l_caps_to_pwr_reg(regs, caps, &mask);\n \tif (pwr_reg < 0)\n \t\treturn pwr_reg;\n \n \tval = readb(pctrl->base + pwr_reg);\n+\tif (pwr_reg == OTHER_POC)\n+\t\tval = field_get(mask, val);\n+\n \tswitch (val) {\n \tcase PVDD_1800:\n \t\treturn 1800;\n@@ -948,8 +971,8 @@ static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps\n {\n \tconst struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;\n \tconst struct rzg2l_register_offsets *regs = &hwcfg->regs;\n+\tu8 poc_val, val, mask;\n \tint pwr_reg;\n-\tu8 val;\n \n \tif (caps & PIN_CFG_SOFT_PS) {\n \t\tpctrl->settings[pin].power_source = ps;\n@@ -958,25 +981,37 @@ static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps\n \n \tswitch (ps) {\n \tcase 1800:\n-\t\tval = PVDD_1800;\n+\t\tpoc_val = PVDD_1800;\n \t\tbreak;\n \tcase 2500:\n \t\tif (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1)))\n \t\t\treturn -EINVAL;\n-\t\tval = PVDD_2500;\n+\t\tpoc_val = PVDD_2500;\n \t\tbreak;\n \tcase 3300:\n-\t\tval = PVDD_3300;\n+\t\tpoc_val = PVDD_3300;\n \t\tbreak;\n \tdefault:\n \t\treturn -EINVAL;\n \t}\n \n-\tpwr_reg = rzg2l_caps_to_pwr_reg(regs, caps);\n+\tpwr_reg = rzg2l_caps_to_pwr_reg(regs, caps, &mask);\n \tif (pwr_reg < 0)\n \t\treturn pwr_reg;\n \n-\twriteb(val, pctrl->base + pwr_reg);\n+\tif (pwr_reg == OTHER_POC) {\n+\t\tscoped_guard(raw_spinlock, &pctrl->lock) {\n+\t\t\tval = readb(pctrl->base + pwr_reg);\n+\t\t\tif (poc_val)\n+\t\t\t\tval |= mask;\n+\t\t\telse\n+\t\t\t\tval &= ~mask;\n+\t\t\twriteb(val, pctrl->base + pwr_reg);\n+\t\t}\n+\t} else {\n+\t\twriteb(poc_val, pctrl->base + pwr_reg);\n+\t}\n+\n \tpctrl->settings[pin].power_source = ps;\n \n \treturn 0;\n","prefixes":["v4","3/7"]}