{"id":2230982,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230982/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260430093422.74812-2-biju.das.jz@bp.renesas.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/1.1/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260430093422.74812-2-biju.das.jz@bp.renesas.com>","date":"2026-04-30T09:34:06","name":"[v4,1/7] dt-bindings: pinctrl: renesas: Document RZ/G3L SoC","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"fa8919a8815e942af0144e9df27748f965c4f668","submitter":{"id":87968,"url":"http://patchwork.ozlabs.org/api/1.1/people/87968/?format=json","name":"Biju","email":"biju.das.au@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260430093422.74812-2-biju.das.jz@bp.renesas.com/mbox/","series":[{"id":502254,"url":"http://patchwork.ozlabs.org/api/1.1/series/502254/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=502254","date":"2026-04-30T09:34:06","name":"Add Renesas RZ/G3L PINCONTROL support","version":4,"mbox":"http://patchwork.ozlabs.org/series/502254/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230982/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230982/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=KpKblg51;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.232.135.74; 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The RZ/G3L PFC is similar to the RZ/G3S SoC but has\nmore pins.\n\nAlso add header file similar to RZ/G3E and RZ/V2H as it has alpha\nnumeric ports.\n\nDocument renesas,clonech property for controlling clone channel\ncontrol register located on SYSC IP block on RZ/G3L SoC.\n\nAcked-by: Conor Dooley \nSigned-off-by: Biju Das \n---\nv3->v4:\n * Dropped Port P4 as it does not exist on RZ/G3L SoC.\n * Retained the tag as it is trivial change.\nv2->v3:\n * Documented renesas,clonech property for controlling clone channel\n control register located on SYSC IP block on RZ/G3L SoC.\n * Retained the tag as it is similar change for RZ/G3E thermal bindings.\nv1->v2:\n * Collected tag\n---\n .../pinctrl/renesas,rzg2l-pinctrl.yaml | 20 ++++++++++\n .../pinctrl/renesas,r9a08g046-pinctrl.h | 38 +++++++++++++++++++\n 2 files changed, 58 insertions(+)\n create mode 100644 include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h","diff":"diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml\nindex 1a94e396b1b0..fb1fe1ea759f 100644\n--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml\n+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml\n@@ -26,6 +26,7 @@ properties:\n - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five\n - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}\n - renesas,r9a08g045-pinctrl # RZ/G3S\n+ - renesas,r9a08g046-pinctrl # RZ/G3L\n - renesas,r9a09g047-pinctrl # RZ/G3E\n - renesas,r9a09g056-pinctrl # RZ/V2N\n - renesas,r9a09g057-pinctrl # RZ/V2H(P)\n@@ -88,6 +89,16 @@ properties:\n - const: main\n - const: error\n \n+ renesas,clonech:\n+ $ref: /schemas/types.yaml#/definitions/phandle-array\n+ items:\n+ - items:\n+ - description: phandle to system controller\n+ - description: offset of clone channel control register\n+ description:\n+ Phandle and offset to the system controller containing the clone channel\n+ control values.\n+\n additionalProperties:\n anyOf:\n - type: object\n@@ -150,6 +161,15 @@ additionalProperties:\n allOf:\n - $ref: pinctrl.yaml#\n \n+ - if:\n+ properties:\n+ compatible:\n+ contains:\n+ const: renesas,r9a08g046-pinctrl\n+ then:\n+ required:\n+ - renesas,clonech\n+\n - if:\n properties:\n compatible:\ndiff --git a/include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h b/include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h\nnew file mode 100644\nindex 000000000000..5ec5bfc27c7d\n--- /dev/null\n+++ b/include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h\n@@ -0,0 +1,38 @@\n+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */\n+/*\n+ * This header provides constants for Renesas RZ/G3L family pinctrl bindings.\n+ *\n+ * Copyright (C) 2026 Renesas Electronics Corp.\n+ *\n+ */\n+\n+#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__\n+#define __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__\n+\n+#include \n+\n+/* RZG3L_Px = Offset address of PFC_P_mn - 0x22 */\n+#define RZG3L_P2\t2\n+#define RZG3L_P3\t3\n+#define RZG3L_P5\t5\n+#define RZG3L_P6\t6\n+#define RZG3L_P7\t7\n+#define RZG3L_P8\t8\n+#define RZG3L_PA\t10\n+#define RZG3L_PB\t11\n+#define RZG3L_PC\t12\n+#define RZG3L_PD\t13\n+#define RZG3L_PE\t14\n+#define RZG3L_PF\t15\n+#define RZG3L_PG\t16\n+#define RZG3L_PH\t17\n+#define RZG3L_PJ\t19\n+#define RZG3L_PK\t20\n+#define RZG3L_PL\t21\n+#define RZG3L_PM\t22\n+#define RZG3L_PS\t28\n+\n+#define RZG3L_PORT_PINMUX(b, p, f)\tRZG2L_PORT_PINMUX(RZG3L_P##b, p, f)\n+#define RZG3L_GPIO(port, pin)\t\tRZG2L_GPIO(RZG3L_P##port, pin)\n+\n+#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A08G046_PINCTRL_H__ */\n","prefixes":["v4","1/7"]}