{"id":2230974,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230974/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430091832.1846637-5-kchiu@axiado.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260430091832.1846637-5-kchiu@axiado.com>","date":"2026-04-30T09:18:32","name":"[v2,4/4] hw/arm: ax3000-soc: Enable Cadence GPIO controllers","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"8b740c5aa9ddc8d256c5745c7d1262e70799ff9c","submitter":{"id":92340,"url":"http://patchwork.ozlabs.org/api/1.1/people/92340/?format=json","name":"Kuan-Jui Chiu","email":"kchiu@axiado.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430091832.1846637-5-kchiu@axiado.com/mbox/","series":[{"id":502248,"url":"http://patchwork.ozlabs.org/api/1.1/series/502248/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502248","date":"2026-04-30T09:18:30","name":"Add Axiado SoC AX3000 and EVK board","version":2,"mbox":"http://patchwork.ozlabs.org/series/502248/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230974/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230974/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=axiado.com header.i=@axiado.com header.a=rsa-sha256\n header.s=selector1 header.b=mkwaibgH;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Ip=[64.62.143.114];\n Helo=[smtp.corp.axiado.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n CH1PEPF0000A34C.namprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DM3PPFD4080C554","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Enable 8 Cadence GPIO controllers into Axiado AX3000 SoC\n\nSigned-off-by: Kuan-Jui Chiu \n---\n hw/arm/Kconfig | 1 +\n hw/arm/ax3000-soc.c | 30 ++++++++++++++++++++++++++++++\n include/hw/arm/ax3000-soc.h | 23 ++++++++++++++++++++++-\n 3 files changed, 53 insertions(+), 1 deletion(-)","diff":"diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig\nindex e569d8ee9e..3adca2923c 100644\n--- a/hw/arm/Kconfig\n+++ b/hw/arm/Kconfig\n@@ -697,6 +697,7 @@ config AXIADO_SOC\n depends on ARM\n select ARM_GIC\n select CADENCE # UART\n+ select CADENCE_GPIO\n select AXIADO_SDHCI\n select UNIMP\n \ndiff --git a/hw/arm/ax3000-soc.c b/hw/arm/ax3000-soc.c\nindex e845a64c2a..b5669cd5ba 100644\n--- a/hw/arm/ax3000-soc.c\n+++ b/hw/arm/ax3000-soc.c\n@@ -59,6 +59,11 @@ static void ax3000_init(Object *obj)\n }\n \n object_initialize_child(obj, \"sdhci0\", &s->sdhci0, TYPE_AXIADO_SDHCI);\n+\n+ for (i = 0; i < AX3000_NUM_GPIOS; i++) {\n+ g_autofree char *name = g_strdup_printf(\"gpio%d\", i);\n+ object_initialize_child(obj, name, &s->gpio[i], TYPE_CADENCE_GPIO);\n+ }\n }\n \n static void ax3000_realize(DeviceState *dev, Error **errp)\n@@ -207,6 +212,31 @@ static void ax3000_realize(DeviceState *dev, Error **errp)\n blk_by_legacy_dinfo((drive_get(IF_SD, 0, 0))),\n &error_fatal);\n qdev_realize_and_unref(card, s->sdhci0.sd_bus, &error_fatal);\n+\n+ /* GPIOs */\n+ for (i = 0; i < AX3000_NUM_GPIOS; i++) {\n+ struct {\n+ hwaddr addr;\n+ unsigned int irq;\n+ } gpio_table[] = {\n+ { AX3000_GPIO0_BASE, AX3000_GPIO0_IRQ },\n+ { AX3000_GPIO1_BASE, AX3000_GPIO1_IRQ },\n+ { AX3000_GPIO2_BASE, AX3000_GPIO2_IRQ },\n+ { AX3000_GPIO3_BASE, AX3000_GPIO3_IRQ },\n+ { AX3000_GPIO4_BASE, AX3000_GPIO4_IRQ },\n+ { AX3000_GPIO5_BASE, AX3000_GPIO5_IRQ },\n+ { AX3000_GPIO6_BASE, AX3000_GPIO6_IRQ },\n+ { AX3000_GPIO7_BASE, AX3000_GPIO7_IRQ }\n+ };\n+\n+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) {\n+ return;\n+ }\n+\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,\n+ qdev_get_gpio_in(gic_dev, gpio_table[i].irq));\n+ }\n }\n \n static void ax3000_class_init(ObjectClass *oc, const void *data)\ndiff --git a/include/hw/arm/ax3000-soc.h b/include/hw/arm/ax3000-soc.h\nindex 2708c9c672..aa388f79f0 100644\n--- a/include/hw/arm/ax3000-soc.h\n+++ b/include/hw/arm/ax3000-soc.h\n@@ -12,6 +12,7 @@\n #include \"cpu.h\"\n #include \"hw/intc/arm_gicv3_common.h\"\n #include \"hw/char/cadence_uart.h\"\n+#include \"hw/gpio/cadence_gpio.h\"\n #include \"hw/sd/axiado_sdhci.h\"\n #include \"hw/core/sysbus.h\"\n #include \"qemu/units.h\"\n@@ -37,6 +38,15 @@ OBJECT_DECLARE_TYPE(Ax3000SoCState, Ax3000SoCClass, AX3000_SOC)\n #define AX3000_SDHCI0_BASE 0x86000000\n #define AX3000_EMMC_PHY_BASE 0x80801C00\n \n+#define AX3000_GPIO0_BASE 0x80500000\n+#define AX3000_GPIO1_BASE 0x80580000\n+#define AX3000_GPIO2_BASE 0x80600000\n+#define AX3000_GPIO3_BASE 0x80680000\n+#define AX3000_GPIO4_BASE 0x80700000\n+#define AX3000_GPIO5_BASE 0x80780000\n+#define AX3000_GPIO6_BASE 0x80800000\n+#define AX3000_GPIO7_BASE 0x80880000\n+\n #define AX3000_TIMER_CTRL 0x8A020000\n #define AX3000_PLL_BASE 0x80000000\n #define CLKRST_CPU_PLL_POSTDIV_OFFSET 0x0C\n@@ -47,6 +57,7 @@ enum Ax3000Configuration {\n AX3000_NUM_IRQS = 224,\n AX3000_NUM_BANKS = 2,\n AX3000_NUM_UARTS = 4,\n+ AX3000_NUM_GPIOS = 8,\n };\n \n typedef struct Ax3000SoCState {\n@@ -57,6 +68,7 @@ typedef struct Ax3000SoCState {\n MemoryRegion dram[AX3000_NUM_BANKS];\n MemoryRegion pll_ctrl;\n CadenceUARTState uart[AX3000_NUM_UARTS];\n+ CadenceGPIOState gpio[AX3000_NUM_GPIOS];\n AxiadoSDHCIState sdhci0;\n } Ax3000SoCState;\n \n@@ -72,7 +84,16 @@ enum Ax3000Irqs {\n AX3000_UART2_IRQ = 114,\n AX3000_UART3_IRQ = 170,\n \n- AX3000_SDHCI0_IRQ = 123,\n+ AX3000_SDHCI0_IRQ = 123,\n+\n+ AX3000_GPIO0_IRQ = 183,\n+ AX3000_GPIO1_IRQ = 184,\n+ AX3000_GPIO2_IRQ = 185,\n+ AX3000_GPIO3_IRQ = 186,\n+ AX3000_GPIO4_IRQ = 187,\n+ AX3000_GPIO5_IRQ = 188,\n+ AX3000_GPIO6_IRQ = 189,\n+ AX3000_GPIO7_IRQ = 190,\n };\n \n #endif /* AXIADO_AX3000_H */\n","prefixes":["v2","4/4"]}