{"id":2230955,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230955/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260430-91-v1-1-4cc79569fef9@nxp.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.1/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260430-91-v1-1-4cc79569fef9@nxp.com>","date":"2026-04-30T09:00:09","name":"[RESEND] imx91: Switch to OF_UPSTREAM","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"bdbf2f81a340fd0b296a821cdb04e5d06c2b6733","submitter":{"id":80695,"url":"http://patchwork.ozlabs.org/api/1.1/people/80695/?format=json","name":"Alice Guo (OSS)","email":"alice.guo@oss.nxp.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260430-91-v1-1-4cc79569fef9@nxp.com/mbox/","series":[{"id":502242,"url":"http://patchwork.ozlabs.org/api/1.1/series/502242/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=502242","date":"2026-04-30T09:00:09","name":"[RESEND] imx91: Switch to OF_UPSTREAM","version":1,"mbox":"http://patchwork.ozlabs.org/series/502242/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230955/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230955/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com\n header.a=rsa-sha256 header.s=selector1-NXP1-onmicrosoft-com\n header.b=j+SfBXaG;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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There are no changes compared to the\nprevious submission.\n---\n arch/arm/dts/imx91-11x11-evk.dts | 875 ---------------------------\n arch/arm/dts/imx91-11x11-frdm.dts | 773 -----------------------\n arch/arm/dts/imx91-pinfunc.h | 770 -----------------------\n arch/arm/dts/imx91.dtsi | 53 --\n arch/arm/mach-imx/imx9/Kconfig | 2 +\n configs/imx91_11x11_evk_defconfig | 2 +-\n configs/imx91_11x11_evk_inline_ecc_defconfig | 2 +-\n configs/imx91_11x11_frdm_defconfig | 2 +-\n 8 files changed, 5 insertions(+), 2474 deletions(-)\n\n\n---\nbase-commit: 4433253ecf2041f9362a763bb6cb79960921ac7e\nchange-id: 20260430-91-d7e39847f1e6\n\nBest regards,\n-- \nAlice Guo ","diff":"diff --git a/arch/arm/dts/imx91-11x11-evk.dts b/arch/arm/dts/imx91-11x11-evk.dts\ndeleted file mode 100644\nindex ca9070a4c76..00000000000\n--- a/arch/arm/dts/imx91-11x11-evk.dts\n+++ /dev/null\n@@ -1,875 +0,0 @@\n-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n-/*\n- * Copyright 2024 NXP\n- */\n-\n-/dts-v1/;\n-\n-#include \n-#include \"imx91.dtsi\"\n-\n-/ {\n-\tcompatible = \"fsl,imx91-11x11-evk\", \"fsl,imx91\";\n-\tmodel = \"NXP i.MX91 11X11 EVK board\";\n-\n-\taliases {\n-\t\tethernet0 = &fec;\n-\t\tethernet1 = &eqos;\n-\t\trtc0 = &bbnsm_rtc;\n-\t};\n-\n-\tchosen {\n-\t\tstdout-path = &lpuart1;\n-\t};\n-\n-\treg_vref_1v8: regulator-adc-vref {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-max-microvolt = <1800000>;\n-\t\tregulator-min-microvolt = <1800000>;\n-\t\tregulator-name = \"vref_1v8\";\n-\t};\n-\n-\treg_audio_pwr: regulator-audio-pwr {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-always-on;\n-\t\tregulator-max-microvolt = <3300000>;\n-\t\tregulator-min-microvolt = <3300000>;\n-\t\tregulator-name = \"audio-pwr\";\n-\t\tgpio = <&adp5585 1 GPIO_ACTIVE_HIGH>;\n-\t\tenable-active-high;\n-\t};\n-\n-\treg_usdhc2_vmmc: regulator-usdhc2 {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\toff-on-delay-us = <12000>;\n-\t\tpinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;\n-\t\tpinctrl-names = \"default\";\n-\t\tregulator-max-microvolt = <3300000>;\n-\t\tregulator-min-microvolt = <3300000>;\n-\t\tregulator-name = \"VSD_3V3\";\n-\t\tgpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;\n-\t\tenable-active-high;\n-\t};\n-\n-\treg_usdhc3_vmmc: regulator-usdhc3 {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-max-microvolt = <3300000>;\n-\t\tregulator-min-microvolt = <3300000>;\n-\t\tregulator-name = \"WLAN_EN\";\n-\t\tgpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>;\n-\t\tenable-active-high;\n-\t\t/*\n-\t\t * IW612 wifi chip needs more delay than other wifi chips to complete\n-\t\t * the host interface initialization after power up, otherwise the\n-\t\t * internal state of IW612 may be unstable, resulting in the failure of\n-\t\t * the SDIO3.0 switch voltage.\n-\t\t */\n-\t\tstartup-delay-us = <20000>;\n-\t};\n-\n-\treg_vdd_12v: regulator-vdd-12v {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-max-microvolt = <12000000>;\n-\t\tregulator-min-microvolt = <12000000>;\n-\t\tregulator-name = \"reg_vdd_12v\";\n-\t\tgpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>;\n-\t\tenable-active-high;\n-\t};\n-\n-\treg_vrpi_3v3: regulator-vrpi-3v3 {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-max-microvolt = <3300000>;\n-\t\tregulator-min-microvolt = <3300000>;\n-\t\tregulator-name = \"VRPI_3V3\";\n-\t\tvin-supply = <&buck4>;\n-\t\tgpio = <&pcal6524 2 GPIO_ACTIVE_HIGH>;\n-\t\tenable-active-high;\n-\t};\n-\n-\treg_vrpi_5v: regulator-vrpi-5v {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-max-microvolt = <5000000>;\n-\t\tregulator-min-microvolt = <5000000>;\n-\t\tregulator-name = \"VRPI_5V\";\n-\t\tgpio = <&pcal6524 8 GPIO_ACTIVE_HIGH>;\n-\t\tenable-active-high;\n-\t};\n-\n-\treserved-memory {\n-\t\tranges;\n-\t\t#address-cells = <2>;\n-\t\t#size-cells = <2>;\n-\n-\t\tlinux,cma {\n-\t\t\tcompatible = \"shared-dma-pool\";\n-\t\t\talloc-ranges = <0 0x80000000 0 0x40000000>;\n-\t\t\treusable;\n-\t\t\tsize = <0 0x10000000>;\n-\t\t\tlinux,cma-default;\n-\t\t};\n-\t};\n-};\n-\n-&adc1 {\n-\tvref-supply = <®_vref_1v8>;\n-\tstatus = \"okay\";\n-};\n-\n-&eqos {\n-\tphy-handle = <ðphy1>;\n-\tphy-mode = \"rgmii-id\";\n-\tpinctrl-0 = <&pinctrl_eqos>;\n-\tpinctrl-1 = <&pinctrl_eqos_sleep>;\n-\tpinctrl-names = \"default\", \"sleep\";\n-\tstatus = \"okay\";\n-\n-\tmdio {\n-\t\tcompatible = \"snps,dwmac-mdio\";\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\t\tclock-frequency = <5000000>;\n-\n-\t\tethphy1: ethernet-phy@1 {\n-\t\t\treg = <1>;\n-\t\t\teee-broken-1000t;\n-\t\t};\n-\t};\n-};\n-\n-&fec {\n-\tphy-handle = <ðphy2>;\n-\tphy-mode = \"rgmii-id\";\n-\tpinctrl-0 = <&pinctrl_fec>;\n-\tpinctrl-1 = <&pinctrl_fec_sleep>;\n-\tpinctrl-names = \"default\", \"sleep\";\n-\tfsl,magic-packet;\n-\tstatus = \"okay\";\n-\n-\tmdio {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\t\tclock-frequency = <5000000>;\n-\n-\t\tethphy2: ethernet-phy@2 {\n-\t\t\treg = <2>;\n-\t\t\teee-broken-1000t;\n-\t\t};\n-\t};\n-};\n-\n-/*\n- * When add, delete or change any target device setting in &lpi2c1,\n- * please synchronize the changes to the &i3c1 bus in imx91-11x11-evk-i3c.dts.\n- */\n-&lpi2c1 {\n-\tclock-frequency = <400000>;\n-\tpinctrl-0 = <&pinctrl_lpi2c1>;\n-\tpinctrl-names = \"default\";\n-\tstatus = \"okay\";\n-\n-\tcodec: wm8962@1a {\n-\t\tcompatible = \"wlf,wm8962\";\n-\t\treg = <0x1a>;\n-\t\tclocks = <&clk IMX93_CLK_SAI3_GATE>;\n-\t\tAVDD-supply = <®_audio_pwr>;\n-\t\tCPVDD-supply = <®_audio_pwr>;\n-\t\tDBVDD-supply = <®_audio_pwr>;\n-\t\tDCVDD-supply = <®_audio_pwr>;\n-\t\tMICVDD-supply = <®_audio_pwr>;\n-\t\tPLLVDD-supply = <®_audio_pwr>;\n-\t\tSPKVDD1-supply = <®_audio_pwr>;\n-\t\tSPKVDD2-supply = <®_audio_pwr>;\n-\t\tgpio-cfg = <\n-\t\t\t0x0000 /* 0:Default */\n-\t\t\t0x0000 /* 1:Default */\n-\t\t\t0x0000 /* 2:FN_DMICCLK */\n-\t\t\t0x0000 /* 3:Default */\n-\t\t\t0x0000 /* 4:FN_DMICCDAT */\n-\t\t\t0x0000 /* 5:Default */\n-\t\t>;\n-\t};\n-\n-\tlsm6dsm@6a {\n-\t\tcompatible = \"st,lsm6dso\";\n-\t\treg = <0x6a>;\n-\t};\n-};\n-\n-&lpi2c2 {\n-\t#address-cells = <1>;\n-\t#size-cells = <0>;\n-\tclock-frequency = <400000>;\n-\tpinctrl-0 = <&pinctrl_lpi2c2>;\n-\tpinctrl-names = \"default\";\n-\tstatus = \"okay\";\n-\n-\tpcal6524: gpio@22 {\n-\t\tcompatible = \"nxp,pcal6524\";\n-\t\treg = <0x22>;\n-\t\t#interrupt-cells = <2>;\n-\t\tinterrupt-controller;\n-\t\tinterrupts = <27 IRQ_TYPE_LEVEL_LOW>;\n-\t\t#gpio-cells = <2>;\n-\t\tgpio-controller;\n-\t\tinterrupt-parent = <&gpio3>;\n-\t\tpinctrl-0 = <&pinctrl_pcal6524>;\n-\t\tpinctrl-names = \"default\";\n-\t};\n-\n-\tpmic@25 {\n-\t\tcompatible = \"nxp,pca9451a\";\n-\t\treg = <0x25>;\n-\t\tinterrupts = <11 IRQ_TYPE_EDGE_FALLING>;\n-\t\tinterrupt-parent = <&pcal6524>;\n-\n-\t\tregulators {\n-\n-\t\t\tbuck1: BUCK1 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-max-microvolt = <2237500>;\n-\t\t\t\tregulator-min-microvolt = <650000>;\n-\t\t\t\tregulator-name = \"BUCK1\";\n-\t\t\t\tregulator-ramp-delay = <3125>;\n-\t\t\t};\n-\n-\t\t\tbuck2: BUCK2 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-max-microvolt = <2187500>;\n-\t\t\t\tregulator-min-microvolt = <600000>;\n-\t\t\t\tregulator-name = \"BUCK2\";\n-\t\t\t\tregulator-ramp-delay = <3125>;\n-\t\t\t};\n-\n-\t\t\tbuck4: BUCK4 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-max-microvolt = <3400000>;\n-\t\t\t\tregulator-min-microvolt = <600000>;\n-\t\t\t\tregulator-name = \"BUCK4\";\n-\t\t\t};\n-\n-\t\t\tbuck5: BUCK5 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-max-microvolt = <3400000>;\n-\t\t\t\tregulator-min-microvolt = <600000>;\n-\t\t\t\tregulator-name = \"BUCK5\";\n-\t\t\t};\n-\n-\t\t\tbuck6: BUCK6 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-max-microvolt = <3400000>;\n-\t\t\t\tregulator-min-microvolt = <600000>;\n-\t\t\t\tregulator-name = \"BUCK6\";\n-\t\t\t};\n-\n-\t\t\tldo1: LDO1 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-min-microvolt = <1600000>;\n-\t\t\t\tregulator-name = \"LDO1\";\n-\t\t\t};\n-\n-\t\t\tldo4: LDO4 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-min-microvolt = <800000>;\n-\t\t\t\tregulator-name = \"LDO4\";\n-\t\t\t};\n-\n-\t\t\tldo5: LDO5 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-name = \"LDO5\";\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tadp5585: io-expander@34 {\n-\t\tcompatible = \"adi,adp5585-00\", \"adi,adp5585\";\n-\t\treg = <0x34>;\n-\t\t#gpio-cells = <2>;\n-\t\tgpio-controller;\n-\t\t#pwm-cells = <3>;\n-\t\tgpio-reserved-ranges = <5 1>;\n-\n-\t\texp-sel-hog {\n-\t\t\tgpio-hog;\n-\t\t\tgpios = <4 GPIO_ACTIVE_HIGH>;\n-\t\t\toutput-low;\n-\t\t};\n-\t};\n-};\n-\n-&lpi2c3 {\n-\t#address-cells = <1>;\n-\t#size-cells = <0>;\n-\tclock-frequency = <400000>;\n-\tpinctrl-0 = <&pinctrl_lpi2c3>;\n-\tpinctrl-names = \"default\";\n-\tstatus = \"okay\";\n-\n-\tptn5110: tcpc@50 {\n-\t\tcompatible = \"nxp,ptn5110\", \"tcpci\";\n-\t\treg = <0x50>;\n-\t\tinterrupts = <27 IRQ_TYPE_LEVEL_LOW>;\n-\t\tinterrupt-parent = <&gpio3>;\n-\t\tstatus = \"okay\";\n-\n-\t\ttypec1_con: connector {\n-\t\t\tcompatible = \"usb-c-connector\";\n-\t\t\tdata-role = \"dual\";\n-\t\t\tlabel = \"USB-C\";\n-\t\t\top-sink-microwatt = <15000000>;\n-\t\t\tpower-role = \"dual\";\n-\t\t\tself-powered;\n-\t\t\tsink-pdos = ;\n-\t\t\tsource-pdos = ;\n-\t\t\ttry-power-role = \"sink\";\n-\n-\t\t\tports {\n-\t\t\t\t#address-cells = <1>;\n-\t\t\t\t#size-cells = <0>;\n-\n-\t\t\t\tport@0 {\n-\t\t\t\t\treg = <0>;\n-\n-\t\t\t\t\ttypec1_dr_sw: endpoint {\n-\t\t\t\t\t\tremote-endpoint = <&usb1_drd_sw>;\n-\t\t\t\t\t};\n-\t\t\t\t};\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tptn5110_2: tcpc@51 {\n-\t\tcompatible = \"nxp,ptn5110\", \"tcpci\";\n-\t\treg = <0x51>;\n-\t\tinterrupts = <27 IRQ_TYPE_LEVEL_LOW>;\n-\t\tinterrupt-parent = <&gpio3>;\n-\t\tstatus = \"okay\";\n-\n-\t\ttypec2_con: connector {\n-\t\t\tcompatible = \"usb-c-connector\";\n-\t\t\tdata-role = \"dual\";\n-\t\t\tlabel = \"USB-C\";\n-\t\t\top-sink-microwatt = <15000000>;\n-\t\t\tpower-role = \"dual\";\n-\t\t\tself-powered;\n-\t\t\tsink-pdos = ;\n-\t\t\tsource-pdos = ;\n-\t\t\ttry-power-role = \"sink\";\n-\n-\t\t\tports {\n-\t\t\t\t#address-cells = <1>;\n-\t\t\t\t#size-cells = <0>;\n-\n-\t\t\t\tport@0 {\n-\t\t\t\t\treg = <0>;\n-\n-\t\t\t\t\ttypec2_dr_sw: endpoint {\n-\t\t\t\t\t\tremote-endpoint = <&usb2_drd_sw>;\n-\t\t\t\t\t};\n-\t\t\t\t};\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tpcf2131: rtc@53 {\n-\t\tcompatible = \"nxp,pcf2131\";\n-\t\treg = <0x53>;\n-\t\tinterrupts = <1 IRQ_TYPE_EDGE_FALLING>;\n-\t\tinterrupt-parent = <&pcal6524>;\n-\t\tstatus = \"okay\";\n-\t};\n-};\n-\n-&lpuart1 {\n-\tpinctrl-0 = <&pinctrl_uart1>;\n-\tpinctrl-names = \"default\";\n-\tstatus = \"okay\";\n-};\n-\n-&lpuart5 {\n-\tpinctrl-0 = <&pinctrl_uart5>;\n-\tpinctrl-names = \"default\";\n-\tstatus = \"okay\";\n-};\n-\n-&usbotg1 {\n-\tadp-disable;\n-\tdisable-over-current;\n-\tdr_mode = \"otg\";\n-\thnp-disable;\n-\tsrp-disable;\n-\tusb-role-switch;\n-\tsamsung,picophy-dc-vol-level-adjust = <7>;\n-\tsamsung,picophy-pre-emp-curr-control = <3>;\n-\tstatus = \"okay\";\n-\n-\tport {\n-\t\tusb1_drd_sw: endpoint {\n-\t\t\tremote-endpoint = <&typec1_dr_sw>;\n-\t\t};\n-\t};\n-};\n-\n-&usbotg2 {\n-\tadp-disable;\n-\tdisable-over-current;\n-\tdr_mode = \"otg\";\n-\thnp-disable;\n-\tsrp-disable;\n-\tusb-role-switch;\n-\tsamsung,picophy-dc-vol-level-adjust = <7>;\n-\tsamsung,picophy-pre-emp-curr-control = <3>;\n-\tstatus = \"okay\";\n-\n-\tport {\n-\t\tusb2_drd_sw: endpoint {\n-\t\t\tremote-endpoint = <&typec2_dr_sw>;\n-\t\t};\n-\t};\n-};\n-\n-&usdhc1 {\n-\tbus-width = <8>;\n-\tnon-removable;\n-\tpinctrl-0 = <&pinctrl_usdhc1>;\n-\tpinctrl-1 = <&pinctrl_usdhc1_100mhz>;\n-\tpinctrl-2 = <&pinctrl_usdhc1_200mhz>;\n-\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\";\n-\tstatus = \"okay\";\n-};\n-\n-&usdhc2 {\n-\tbus-width = <4>;\n-\tcd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;\n-\tno-mmc;\n-\tno-sdio;\n-\tpinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;\n-\tpinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;\n-\tpinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;\n-\tpinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;\n-\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\", \"sleep\";\n-\tvmmc-supply = <®_usdhc2_vmmc>;\n-\tstatus = \"okay\";\n-};\n-\n-&wdog3 {\n-\tfsl,ext-reset-output;\n-\tstatus = \"okay\";\n-};\n-\n-&iomuxc {\n-\tpinctrl_eqos: eqosgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_ENET1_MDC__ENET1_MDC\t\t\t0x57e\n-\t\t\tMX91_PAD_ENET1_MDIO__ENET_QOS_MDIO\t\t\t0x57e\n-\t\t\tMX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0\t\t\t0x57e\n-\t\t\tMX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1\t\t\t0x57e\n-\t\t\tMX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2\t\t\t0x57e\n-\t\t\tMX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3\t\t\t0x57e\n-\t\t\tMX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC\t0x5fe\n-\t\t\tMX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL\t\t0x57e\n-\t\t\tMX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0\t\t\t0x57e\n-\t\t\tMX91_PAD_ENET1_TD1__ENET1_RGMII_TD1\t\t\t0x57e\n-\t\t\tMX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2\t\t\t0x57e\n-\t\t\tMX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3\t\t\t0x57e\n-\t\t\tMX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK\t0x5fe\n-\t\t\tMX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL\t\t0x57e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_eqos_sleep: eqossleepgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_ENET1_MDC__GPIO4_IO0\t\t\t\t0x31e\n-\t\t\tMX91_PAD_ENET1_MDIO__GPIO4_IO1\t\t\t\t0x31e\n-\t\t\tMX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e\n-\t\t\tMX91_PAD_ENET1_RD1__GPIO4_IO11\t\t\t\t0x31e\n-\t\t\tMX91_PAD_ENET1_RD2__GPIO4_IO12\t\t\t\t0x31e\n-\t\t\tMX91_PAD_ENET1_RD3__GPIO4_IO13\t\t\t\t0x31e\n-\t\t\tMX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e\n-\t\t\tMX91_PAD_ENET1_RX_CTL__GPIO4_IO8\t\t\t0x31e\n-\t\t\tMX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e\n-\t\t\tMX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e\n-\t\t\tMX91_PAD_ENET1_TD2__GPIO4_IO3\t\t\t\t0x31e\n-\t\t\tMX91_PAD_ENET1_TD3__GPIO4_IO2\t\t\t\t0x31e\n-\t\t\tMX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e\n-\t\t\tMX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_fec: fecgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_ENET2_MDC__ENET2_MDC\t\t\t0x57e\n-\t\t\tMX91_PAD_ENET2_MDIO__ENET2_MDIO\t\t\t0x57e\n-\t\t\tMX91_PAD_ENET2_RD0__ENET2_RGMII_RD0\t\t0x57e\n-\t\t\tMX91_PAD_ENET2_RD1__ENET2_RGMII_RD1\t\t0x57e\n-\t\t\tMX91_PAD_ENET2_RD2__ENET2_RGMII_RD2\t\t0x57e\n-\t\t\tMX91_PAD_ENET2_RD3__ENET2_RGMII_RD3\t\t0x57e\n-\t\t\tMX91_PAD_ENET2_RXC__ENET2_RGMII_RXC\t\t0x5fe\n-\t\t\tMX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL\t0x57e\n-\t\t\tMX91_PAD_ENET2_TD0__ENET2_RGMII_TD0\t\t0x57e\n-\t\t\tMX91_PAD_ENET2_TD1__ENET2_RGMII_TD1\t\t0x57e\n-\t\t\tMX91_PAD_ENET2_TD2__ENET2_RGMII_TD2\t\t0x57e\n-\t\t\tMX91_PAD_ENET2_TD3__ENET2_RGMII_TD3\t\t0x57e\n-\t\t\tMX91_PAD_ENET2_TXC__ENET2_RGMII_TXC\t\t0x5fe\n-\t\t\tMX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL\t0x57e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_fec_sleep: fecsleepgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_ENET2_MDC__GPIO4_IO14\t\t\t0x51e\n-\t\t\tMX91_PAD_ENET2_MDIO__GPIO4_IO15\t\t\t0x51e\n-\t\t\tMX91_PAD_ENET2_RD0__GPIO4_IO24\t\t\t0x51e\n-\t\t\tMX91_PAD_ENET2_RD1__GPIO4_IO25\t\t\t0x51e\n-\t\t\tMX91_PAD_ENET2_RD2__GPIO4_IO26\t\t\t0x51e\n-\t\t\tMX91_PAD_ENET2_RD3__GPIO4_IO27\t\t\t0x51e\n-\t\t\tMX91_PAD_ENET2_RXC__GPIO4_IO23\t\t\t0x51e\n-\t\t\tMX91_PAD_ENET2_RX_CTL__GPIO4_IO22\t\t0x51e\n-\t\t\tMX91_PAD_ENET2_TD0__GPIO4_IO19\t\t\t0x51e\n-\t\t\tMX91_PAD_ENET2_TD1__GPIO4_IO18\t\t\t0x51e\n-\t\t\tMX91_PAD_ENET2_TD2__GPIO4_IO17\t\t\t0x51e\n-\t\t\tMX91_PAD_ENET2_TD3__GPIO4_IO16\t\t\t0x51e\n-\t\t\tMX91_PAD_ENET2_TXC__GPIO4_IO21\t\t\t0x51e\n-\t\t\tMX91_PAD_ENET2_TX_CTL__GPIO4_IO20\t\t0x51e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_flexcan2: flexcan2grp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_GPIO_IO25__CAN2_TX\t0x139e\n-\t\t\tMX91_PAD_GPIO_IO27__CAN2_RX\t0x139e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_flexcan2_sleep: flexcan2sleepgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_GPIO_IO25__GPIO2_IO25 0x31e\n-\t\t\tMX91_PAD_GPIO_IO27__GPIO2_IO27\t0x31e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_lcdif_gpio: lcdifgpiogrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_GPIO_IO00__GPIO2_IO0\t\t\t0x51e\n-\t\t\tMX91_PAD_GPIO_IO01__GPIO2_IO1\t\t\t0x51e\n-\t\t\tMX91_PAD_GPIO_IO02__GPIO2_IO2\t\t\t0x51e\n-\t\t\tMX91_PAD_GPIO_IO03__GPIO2_IO3\t\t\t0x51e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_lcdif: lcdifgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO27__GPIO2_IO27\t\t\t0x31e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_lpi2c1: lpi2c1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_I2C1_SCL__LPI2C1_SCL\t\t\t0x40000b9e\n-\t\t\tMX91_PAD_I2C1_SDA__LPI2C1_SDA\t\t\t0x40000b9e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_lpi2c2: lpi2c2grp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_I2C2_SCL__LPI2C2_SCL\t\t\t0x40000b9e\n-\t\t\tMX91_PAD_I2C2_SDA__LPI2C2_SDA\t\t\t0x40000b9e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_lpi2c3: lpi2c3grp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_GPIO_IO28__LPI2C3_SDA\t\t\t0x40000b9e\n-\t\t\tMX91_PAD_GPIO_IO29__LPI2C3_SCL\t\t\t0x40000b9e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_pcal6524: pcal6524grp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_CCM_CLKO2__GPIO3_IO27\t\t\t0x31e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_pdm: pdmgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_PDM_CLK__PDM_CLK\t\t\t0x31e\n-\t\t\tMX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0\t0x31e\n-\t\t\tMX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1\t0x31e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_pdm_sleep: pdmsleepgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_PDM_CLK__GPIO1_IO8\t\t\t0x31e\n-\t\t\tMX91_PAD_PDM_BIT_STREAM0__GPIO1_IO9\t\t0x31e\n-\t\t\tMX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10\t\t0x31e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SD2_RESET_B__GPIO3_IO7\t0x31e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_sai1: sai1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SAI1_TXC__SAI1_TX_BCLK\t\t\t0x31e\n-\t\t\tMX91_PAD_SAI1_TXFS__SAI1_TX_SYNC\t\t0x31e\n-\t\t\tMX91_PAD_SAI1_TXD0__SAI1_TX_DATA0\t\t0x31e\n-\t\t\tMX91_PAD_SAI1_RXD0__SAI1_RX_DATA0\t\t0x31e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_sai1_sleep: sai1sleepgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SAI1_TXC__GPIO1_IO12 0x51e\n-\t\t\tMX91_PAD_SAI1_TXFS__GPIO1_IO11\t\t\t0x51e\n-\t\t\tMX91_PAD_SAI1_TXD0__GPIO1_IO13\t\t\t0x51e\n-\t\t\tMX91_PAD_SAI1_RXD0__GPIO1_IO14\t\t\t0x51e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_sai3: sai3grp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_GPIO_IO26__SAI3_TX_SYNC\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO16__SAI3_TX_BCLK\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO17__SAI3_MCLK\t\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO19__SAI3_TX_DATA0\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO20__SAI3_RX_DATA0\t\t0x31e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_sai3_sleep: sai3sleepgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_GPIO_IO26__GPIO2_IO26\t\t\t0x51e\n-\t\t\tMX91_PAD_GPIO_IO16__GPIO2_IO16\t\t\t0x51e\n-\t\t\tMX91_PAD_GPIO_IO17__GPIO2_IO17\t\t\t0x51e\n-\t\t\tMX91_PAD_GPIO_IO19__GPIO2_IO19\t\t\t0x51e\n-\t\t\tMX91_PAD_GPIO_IO20__GPIO2_IO20\t\t\t0x51e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_spdif: spdifgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_GPIO_IO22__SPDIF_IN\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO23__SPDIF_OUT\t\t0x31e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_spdif_sleep: spdifsleepgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_GPIO_IO22__GPIO2_IO22\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO23__GPIO2_IO23\t\t0x31e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_uart1: uart1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_UART1_RXD__LPUART1_RX\t\t\t0x31e\n-\t\t\tMX91_PAD_UART1_TXD__LPUART1_TX\t\t\t0x31e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_uart5: uart5grp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX\t0x31e\n-\t\t\tMX91_PAD_DAP_TDI__LPUART5_RX\t\t0x31e\n-\t\t\tMX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B\t0x31e\n-\t\t\tMX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B\t0x31e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SD1_CLK__USDHC1_CLK\t\t0x158e\n-\t\t\tMX91_PAD_SD1_CMD__USDHC1_CMD\t\t0x138e\n-\t\t\tMX91_PAD_SD1_DATA0__USDHC1_DATA0\t0x138e\n-\t\t\tMX91_PAD_SD1_DATA1__USDHC1_DATA1\t0x138e\n-\t\t\tMX91_PAD_SD1_DATA2__USDHC1_DATA2\t0x138e\n-\t\t\tMX91_PAD_SD1_DATA3__USDHC1_DATA3\t0x138e\n-\t\t\tMX91_PAD_SD1_DATA4__USDHC1_DATA4\t0x138e\n-\t\t\tMX91_PAD_SD1_DATA5__USDHC1_DATA5\t0x138e\n-\t\t\tMX91_PAD_SD1_DATA6__USDHC1_DATA6\t0x138e\n-\t\t\tMX91_PAD_SD1_DATA7__USDHC1_DATA7\t0x138e\n-\t\t\tMX91_PAD_SD1_STROBE__USDHC1_STROBE\t0x158e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SD1_CLK__USDHC1_CLK\t\t0x15fe\n-\t\t\tMX91_PAD_SD1_CMD__USDHC1_CMD\t\t0x13fe\n-\t\t\tMX91_PAD_SD1_DATA0__USDHC1_DATA0\t0x13fe\n-\t\t\tMX91_PAD_SD1_DATA1__USDHC1_DATA1\t0x13fe\n-\t\t\tMX91_PAD_SD1_DATA2__USDHC1_DATA2\t0x13fe\n-\t\t\tMX91_PAD_SD1_DATA3__USDHC1_DATA3\t0x13fe\n-\t\t\tMX91_PAD_SD1_DATA4__USDHC1_DATA4\t0x13fe\n-\t\t\tMX91_PAD_SD1_DATA5__USDHC1_DATA5\t0x13fe\n-\t\t\tMX91_PAD_SD1_DATA6__USDHC1_DATA6\t0x13fe\n-\t\t\tMX91_PAD_SD1_DATA7__USDHC1_DATA7\t0x13fe\n-\t\t\tMX91_PAD_SD1_STROBE__USDHC1_STROBE\t0x15fe\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc1: usdhc1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SD1_CLK__USDHC1_CLK\t\t0x1582\n-\t\t\tMX91_PAD_SD1_CMD__USDHC1_CMD\t\t0x1382\n-\t\t\tMX91_PAD_SD1_DATA0__USDHC1_DATA0\t0x1382\n-\t\t\tMX91_PAD_SD1_DATA1__USDHC1_DATA1\t0x1382\n-\t\t\tMX91_PAD_SD1_DATA2__USDHC1_DATA2\t0x1382\n-\t\t\tMX91_PAD_SD1_DATA3__USDHC1_DATA3\t0x1382\n-\t\t\tMX91_PAD_SD1_DATA4__USDHC1_DATA4\t0x1382\n-\t\t\tMX91_PAD_SD1_DATA5__USDHC1_DATA5\t0x1382\n-\t\t\tMX91_PAD_SD1_DATA6__USDHC1_DATA6\t0x1382\n-\t\t\tMX91_PAD_SD1_DATA7__USDHC1_DATA7\t0x1382\n-\t\t\tMX91_PAD_SD1_STROBE__USDHC1_STROBE\t0x1582\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SD2_CLK__USDHC2_CLK\t\t0x158e\n-\t\t\tMX91_PAD_SD2_CMD__USDHC2_CMD\t\t0x138e\n-\t\t\tMX91_PAD_SD2_DATA0__USDHC2_DATA0\t0x138e\n-\t\t\tMX91_PAD_SD2_DATA1__USDHC2_DATA1\t0x138e\n-\t\t\tMX91_PAD_SD2_DATA2__USDHC2_DATA2\t0x138e\n-\t\t\tMX91_PAD_SD2_DATA3__USDHC2_DATA3\t0x138e\n-\t\t\tMX91_PAD_SD2_VSELECT__USDHC2_VSELECT\t0x51e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SD2_CLK__USDHC2_CLK\t\t0x15fe\n-\t\t\tMX91_PAD_SD2_CMD__USDHC2_CMD\t\t0x13fe\n-\t\t\tMX91_PAD_SD2_DATA0__USDHC2_DATA0\t0x13fe\n-\t\t\tMX91_PAD_SD2_DATA1__USDHC2_DATA1\t0x13fe\n-\t\t\tMX91_PAD_SD2_DATA2__USDHC2_DATA2\t0x13fe\n-\t\t\tMX91_PAD_SD2_DATA3__USDHC2_DATA3\t0x13fe\n-\t\t\tMX91_PAD_SD2_VSELECT__USDHC2_VSELECT\t0x51e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2_gpio: usdhc2gpiogrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SD2_CD_B__GPIO3_IO0\t\t0x31e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SD2_CD_B__GPIO3_IO0\t\t0x51e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2: usdhc2grp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SD2_CLK__USDHC2_CLK\t\t0x1582\n-\t\t\tMX91_PAD_SD2_CMD__USDHC2_CMD\t\t0x1382\n-\t\t\tMX91_PAD_SD2_DATA0__USDHC2_DATA0\t0x1382\n-\t\t\tMX91_PAD_SD2_DATA1__USDHC2_DATA1\t0x1382\n-\t\t\tMX91_PAD_SD2_DATA2__USDHC2_DATA2\t0x1382\n-\t\t\tMX91_PAD_SD2_DATA3__USDHC2_DATA3\t0x1382\n-\t\t\tMX91_PAD_SD2_VSELECT__USDHC2_VSELECT\t0x51e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2_sleep: usdhc2sleepgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SD2_CLK__GPIO3_IO1 0x51e\n-\t\t\tMX91_PAD_SD2_CMD__GPIO3_IO2\t\t0x51e\n-\t\t\tMX91_PAD_SD2_DATA0__GPIO3_IO3\t\t0x51e\n-\t\t\tMX91_PAD_SD2_DATA1__GPIO3_IO4\t\t0x51e\n-\t\t\tMX91_PAD_SD2_DATA2__GPIO3_IO5\t\t0x51e\n-\t\t\tMX91_PAD_SD2_DATA3__GPIO3_IO6\t\t0x51e\n-\t\t\tMX91_PAD_SD2_VSELECT__GPIO3_IO19\t0x51e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SD3_CLK__USDHC3_CLK\t\t0x158e\n-\t\t\tMX91_PAD_SD3_CMD__USDHC3_CMD\t\t0x138e\n-\t\t\tMX91_PAD_SD3_DATA0__USDHC3_DATA0\t0x138e\n-\t\t\tMX91_PAD_SD3_DATA1__USDHC3_DATA1\t0x138e\n-\t\t\tMX91_PAD_SD3_DATA2__USDHC3_DATA2\t0x138e\n-\t\t\tMX91_PAD_SD3_DATA3__USDHC3_DATA3\t0x138e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SD3_CLK__USDHC3_CLK\t\t0x15fe\n-\t\t\tMX91_PAD_SD3_CMD__USDHC3_CMD\t\t0x13fe\n-\t\t\tMX91_PAD_SD3_DATA0__USDHC3_DATA0\t0x13fe\n-\t\t\tMX91_PAD_SD3_DATA1__USDHC3_DATA1\t0x13fe\n-\t\t\tMX91_PAD_SD3_DATA2__USDHC3_DATA2\t0x13fe\n-\t\t\tMX91_PAD_SD3_DATA3__USDHC3_DATA3\t0x13fe\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc3: usdhc3grp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SD3_CLK__USDHC3_CLK\t\t0x1582\n-\t\t\tMX91_PAD_SD3_CMD__USDHC3_CMD\t\t0x1382\n-\t\t\tMX91_PAD_SD3_DATA0__USDHC3_DATA0\t0x1382\n-\t\t\tMX91_PAD_SD3_DATA1__USDHC3_DATA1\t0x1382\n-\t\t\tMX91_PAD_SD3_DATA2__USDHC3_DATA2\t0x1382\n-\t\t\tMX91_PAD_SD3_DATA3__USDHC3_DATA3\t0x1382\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc3_sleep: usdhc3sleepgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SD3_CLK__GPIO3_IO20\t\t0x31e\n-\t\t\tMX91_PAD_SD3_CMD__GPIO3_IO21\t\t0x31e\n-\t\t\tMX91_PAD_SD3_DATA0__GPIO3_IO22\t\t0x31e\n-\t\t\tMX91_PAD_SD3_DATA1__GPIO3_IO23\t\t0x31e\n-\t\t\tMX91_PAD_SD3_DATA2__GPIO3_IO24\t\t0x31e\n-\t\t\tMX91_PAD_SD3_DATA3__GPIO3_IO25\t\t0x31e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc3_wlan: usdhc3wlangrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_CCM_CLKO1__GPIO3_IO26\t\t0x31e\n-\t\t>;\n-\t};\n-};\ndiff --git a/arch/arm/dts/imx91-11x11-frdm.dts b/arch/arm/dts/imx91-11x11-frdm.dts\ndeleted file mode 100644\nindex fc9d6729c58..00000000000\n--- a/arch/arm/dts/imx91-11x11-frdm.dts\n+++ /dev/null\n@@ -1,773 +0,0 @@\n-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n-/*\n- * Copyright 2025 NXP\n- */\n-\n-/dts-v1/;\n-\n-#include \n-#include \"imx91.dtsi\"\n-\n-/ {\n-\tcompatible = \"fsl,imx91-11x11-frdm\", \"fsl,imx91\";\n-\tmodel = \"NXP i.MX91 11X11 FRDM Board\";\n-\n-\taliases {\n-\t\tethernet0 = &fec;\n-\t\tethernet1 = &eqos;\n-\t\trtc0 = &pcf2131;\n-\t};\n-\n-\tchosen {\n-\t\tstdout-path = &lpuart1;\n-\t};\n-\n-\treg_vref_1v8: regulator-adc-vref {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-max-microvolt = <1800000>;\n-\t\tregulator-min-microvolt = <1800000>;\n-\t\tregulator-name = \"vref_1v8\";\n-\t};\n-\n-\treg_usdhc2_vmmc: regulator-usdhc2 {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\toff-on-delay-us = <12000>;\n-\t\tpinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;\n-\t\tpinctrl-names = \"default\";\n-\t\tregulator-max-microvolt = <3300000>;\n-\t\tregulator-min-microvolt = <3300000>;\n-\t\tregulator-name = \"VSD_3V3\";\n-\t\tgpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;\n-\t\tenable-active-high;\n-\t\tbootph-pre-ram;\n-\t\tbootph-some-ram;\n-\t};\n-\n-\treg_vdd_12v: regulator-vdd-12v {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-max-microvolt = <12000000>;\n-\t\tregulator-min-microvolt = <12000000>;\n-\t\tregulator-name = \"reg_vdd_12v\";\n-\t\tgpio = <&pcal6524 14 GPIO_ACTIVE_HIGH>;\n-\t\tenable-active-high;\n-\t};\n-\n-\treg_vexp_3v3: regulator-vexp-3v3 {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-max-microvolt = <3300000>;\n-\t\tregulator-min-microvolt = <3300000>;\n-\t\tregulator-name = \"VEXP_3V3\";\n-\t\tvin-supply = <&buck4>;\n-\t\tgpio = <&pcal6524 2 GPIO_ACTIVE_HIGH>;\n-\t\tenable-active-high;\n-\t};\n-\n-\treg_vexp_5v: regulator-vexp-5v {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-max-microvolt = <5000000>;\n-\t\tregulator-min-microvolt = <5000000>;\n-\t\tregulator-name = \"VEXP_5V\";\n-\t\tgpio = <&pcal6524 8 GPIO_ACTIVE_HIGH>;\n-\t\tenable-active-high;\n-\t};\n-\n-\treserved-memory {\n-\t\tranges;\n-\t\t#address-cells = <2>;\n-\t\t#size-cells = <2>;\n-\n-\t\tlinux,cma {\n-\t\t\tcompatible = \"shared-dma-pool\";\n-\t\t\talloc-ranges = <0 0x80000000 0 0x40000000>;\n-\t\t\treusable;\n-\t\t\tsize = <0 0x10000000>;\n-\t\t\tlinux,cma-default;\n-\t\t};\n-\t};\n-\n-\tsoc@0 {\n-\t\tbootph-all;\n-\t\tbootph-pre-ram;\n-\t};\n-};\n-\n-&adc1 {\n-\tvref-supply = <®_vref_1v8>;\n-\tstatus = \"okay\";\n-};\n-\n-&aips1 {\n-\tbootph-pre-ram;\n-\tbootph-all;\n-};\n-\n-&aips2 {\n-\tbootph-pre-ram;\n-\tbootph-some-ram;\n-};\n-\n-&aips3 {\n-\tbootph-pre-ram;\n-\tbootph-some-ram;\n-};\n-\n-&clk {\n-\tbootph-all;\n-\tbootph-pre-ram;\n-};\n-\n-&clk_ext1 {\n-\tbootph-all;\n-\tbootph-pre-ram;\n-};\n-\n-&eqos {\n-\tphy-handle = <ðphy1>;\n-\tphy-mode = \"rgmii-id\";\n-\tpinctrl-0 = <&pinctrl_eqos>;\n-\tpinctrl-1 = <&pinctrl_eqos_sleep>;\n-\tpinctrl-names = \"default\", \"sleep\";\n-\tstatus = \"okay\";\n-\n-\tmdio {\n-\t\tcompatible = \"snps,dwmac-mdio\";\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\t\tclock-frequency = <5000000>;\n-\n-\t\tethphy1: ethernet-phy@1 {\n-\t\t\treg = <1>;\n-\t\t\teee-broken-1000t;\n-\t\t\treset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;\n-\t\t\treset-assert-us = <15000>;\n-\t\t\treset-deassert-us = <100000>;\n-\t\t};\n-\t};\n-};\n-\n-&fec {\n-\tphy-handle = <ðphy2>;\n-\tphy-mode = \"rgmii-id\";\n-\tpinctrl-0 = <&pinctrl_fec>;\n-\tpinctrl-1 = <&pinctrl_fec_sleep>;\n-\tpinctrl-names = \"default\", \"sleep\";\n-\tfsl,magic-packet;\n-\tstatus = \"okay\";\n-\n-\tmdio {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\t\tclock-frequency = <5000000>;\n-\n-\t\tethphy2: ethernet-phy@2 {\n-\t\t\treg = <2>;\n-\t\t\teee-broken-1000t;\n-\t\t\treset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;\n-\t\t\treset-assert-us = <15000>;\n-\t\t\treset-deassert-us = <100000>;\n-\t\t};\n-\t};\n-};\n-\n-&gpio1 {\n-\tbootph-pre-ram;\n-\tbootph-some-ram;\n-};\n-\n-&gpio2 {\n-\tbootph-pre-ram;\n-\tbootph-some-ram;\n-};\n-\n-&gpio3 {\n-\tbootph-pre-ram;\n-\tbootph-some-ram;\n-};\n-\n-&gpio4 {\n-\tbootph-pre-ram;\n-\tbootph-some-ram;\n-};\n-\n-&lpi2c1 {\n-\tbootph-pre-ram;\n-\tbootph-some-ram;\n-};\n-\n-&lpi2c2 {\n-\t#address-cells = <1>;\n-\t#size-cells = <0>;\n-\tclock-frequency = <400000>;\n-\tpinctrl-0 = <&pinctrl_lpi2c2>;\n-\tpinctrl-names = \"default\";\n-\tstatus = \"okay\";\n-\tbootph-pre-ram;\n-\tbootph-some-ram;\n-\n-\tpcal6524: gpio@22 {\n-\t\tcompatible = \"nxp,pcal6524\";\n-\t\treg = <0x22>;\n-\t\t#interrupt-cells = <2>;\n-\t\tinterrupt-controller;\n-\t\tinterrupt-parent = <&gpio3>;\n-\t\tinterrupts = <27 IRQ_TYPE_LEVEL_LOW>;\n-\t\t#gpio-cells = <2>;\n-\t\tgpio-controller;\n-\t\tpinctrl-0 = <&pinctrl_pcal6524>;\n-\t\tpinctrl-names = \"default\";\n-\t};\n-\n-\tpmic@25 {\n-\t\tcompatible = \"nxp,pca9451a\";\n-\t\treg = <0x25>;\n-\t\tinterrupts = <11 IRQ_TYPE_EDGE_FALLING>;\n-\t\tinterrupt-parent = <&pcal6524>;\n-\t\tbootph-pre-ram;\n-\t\tbootph-some-ram;\n-\n-\t\tregulators {\n-\t\t\tbootph-pre-ram;\n-\t\t\tbootph-some-ram;\n-\n-\t\t\tbuck1: BUCK1 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-max-microvolt = <2237500>;\n-\t\t\t\tregulator-min-microvolt = <650000>;\n-\t\t\t\tregulator-name = \"BUCK1\";\n-\t\t\t\tregulator-ramp-delay = <3125>;\n-\t\t\t};\n-\n-\t\t\tbuck2: BUCK2 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-max-microvolt = <2187500>;\n-\t\t\t\tregulator-min-microvolt = <600000>;\n-\t\t\t\tregulator-name = \"BUCK2\";\n-\t\t\t\tregulator-ramp-delay = <3125>;\n-\t\t\t};\n-\n-\t\t\tbuck4: BUCK4 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-max-microvolt = <3400000>;\n-\t\t\t\tregulator-min-microvolt = <600000>;\n-\t\t\t\tregulator-name = \"BUCK4\";\n-\t\t\t};\n-\n-\t\t\tbuck5: BUCK5 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-max-microvolt = <3400000>;\n-\t\t\t\tregulator-min-microvolt = <600000>;\n-\t\t\t\tregulator-name = \"BUCK5\";\n-\t\t\t};\n-\n-\t\t\tbuck6: BUCK6 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-max-microvolt = <3400000>;\n-\t\t\t\tregulator-min-microvolt = <600000>;\n-\t\t\t\tregulator-name = \"BUCK6\";\n-\t\t\t};\n-\n-\t\t\tldo1: LDO1 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-min-microvolt = <1600000>;\n-\t\t\t\tregulator-name = \"LDO1\";\n-\t\t\t};\n-\n-\t\t\tldo4: LDO4 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-min-microvolt = <800000>;\n-\t\t\t\tregulator-name = \"LDO4\";\n-\t\t\t};\n-\n-\t\t\tldo5: LDO5 {\n-\t\t\t\tregulator-always-on;\n-\t\t\t\tregulator-boot-on;\n-\t\t\t\tregulator-max-microvolt = <3300000>;\n-\t\t\t\tregulator-min-microvolt = <1800000>;\n-\t\t\t\tregulator-name = \"LDO5\";\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\teeprom: at24c256@50 {\n-\t\tcompatible = \"atmel,24c256\";\n-\t\treg = <0x50>;\n-\t\tpagesize = <64>;\n-\t};\n-};\n-\n-&lpi2c3 {\n-\t#address-cells = <1>;\n-\t#size-cells = <0>;\n-\tclock-frequency = <400000>;\n-\tpinctrl-0 = <&pinctrl_lpi2c3>;\n-\tpinctrl-names = \"default\";\n-\tstatus = \"okay\";\n-\tbootph-pre-ram;\n-\tbootph-some-ram;\n-\n-\tptn5110: tcpc@50 {\n-\t\tcompatible = \"nxp,ptn5110\", \"tcpci\";\n-\t\treg = <0x50>;\n-\t\tinterrupts = <27 IRQ_TYPE_LEVEL_LOW>;\n-\t\tinterrupt-parent = <&gpio3>;\n-\t\tstatus = \"okay\";\n-\n-\t\ttypec1_con: connector {\n-\t\t\tcompatible = \"usb-c-connector\";\n-\t\t\tdata-role = \"dual\";\n-\t\t\tlabel = \"USB-C\";\n-\t\t\top-sink-microwatt = <15000000>;\n-\t\t\tpower-role = \"dual\";\n-\t\t\tself-powered;\n-\t\t\tsink-pdos = ;\n-\t\t\tsource-pdos = ;\n-\t\t\ttry-power-role = \"sink\";\n-\n-\t\t\tports {\n-\t\t\t\t#address-cells = <1>;\n-\t\t\t\t#size-cells = <0>;\n-\n-\t\t\t\tport@0 {\n-\t\t\t\t\treg = <0>;\n-\n-\t\t\t\t\ttypec1_dr_sw: endpoint {\n-\t\t\t\t\t\tremote-endpoint = <&usb1_drd_sw>;\n-\t\t\t\t\t};\n-\t\t\t\t};\n-\t\t\t};\n-\t\t};\n-\t};\n-\n-\tpcf2131: rtc@53 {\n-\t\tcompatible = \"nxp,pcf2131\";\n-\t\treg = <0x53>;\n-\t\tinterrupts = <1 IRQ_TYPE_EDGE_FALLING>;\n-\t\tinterrupt-parent = <&pcal6524>;\n-\t\tstatus = \"okay\";\n-\t};\n-};\n-\n-&lpuart1 {\n-\tpinctrl-0 = <&pinctrl_uart1>;\n-\tpinctrl-names = \"default\";\n-\tstatus = \"okay\";\n-\tbootph-pre-ram;\n-\tbootph-some-ram;\n-};\n-\n-&lpuart5 {\n-\tpinctrl-0 = <&pinctrl_uart5>;\n-\tpinctrl-names = \"default\";\n-\tstatus = \"okay\";\n-};\n-\n-&osc_32k {\n-\tbootph-all;\n-\tbootph-pre-ram;\n-};\n-\n-&osc_24m {\n-\tbootph-all;\n-\tbootph-pre-ram;\n-};\n-\n-&usbotg1 {\n-\tadp-disable;\n-\tdisable-over-current;\n-\tdr_mode = \"otg\";\n-\thnp-disable;\n-\tsrp-disable;\n-\tusb-role-switch;\n-\tsamsung,picophy-dc-vol-level-adjust = <7>;\n-\tsamsung,picophy-pre-emp-curr-control = <3>;\n-\tstatus = \"okay\";\n-\n-\tport {\n-\t\tusb1_drd_sw: endpoint {\n-\t\t\tremote-endpoint = <&typec1_dr_sw>;\n-\t\t};\n-\t};\n-};\n-\n-&usbotg2 {\n-\tdisable-over-current;\n-\tdr_mode = \"host\";\n-\tsamsung,picophy-dc-vol-level-adjust = <7>;\n-\tsamsung,picophy-pre-emp-curr-control = <3>;\n-\tstatus = \"okay\";\n-};\n-\n-&usdhc1 {\n-\tbus-width = <8>;\n-\tnon-removable;\n-\tpinctrl-0 = <&pinctrl_usdhc1>;\n-\tpinctrl-1 = <&pinctrl_usdhc1_100mhz>;\n-\tpinctrl-2 = <&pinctrl_usdhc1_200mhz>;\n-\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\";\n-\tstatus = \"okay\";\n-\tbootph-pre-ram;\n-\tbootph-some-ram;\n-};\n-\n-&usdhc2 {\n-\tbus-width = <4>;\n-\tcd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;\n-\tno-mmc;\n-\tno-sdio;\n-\tpinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;\n-\tpinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;\n-\tpinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;\n-\tpinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;\n-\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\", \"sleep\";\n-\tvmmc-supply = <®_usdhc2_vmmc>;\n-\tstatus = \"okay\";\n-};\n-\n-&wdog3 {\n-\tfsl,ext-reset-output;\n-\tstatus = \"okay\";\n-};\n-\n-&iomuxc {\n-\tbootph-pre-ram;\n-\tbootph-some-ram;\n-\n-\tpinctrl_eqos: eqosgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_ENET1_MDC__ENET1_MDC\t\t\t\t0x57e\n-\t\t\tMX91_PAD_ENET1_MDIO__ENET_QOS_MDIO\t\t\t0x57e\n-\t\t\tMX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0\t\t\t0x57e\n-\t\t\tMX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1\t\t\t0x57e\n-\t\t\tMX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2\t\t\t0x57e\n-\t\t\tMX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3\t\t\t0x57e\n-\t\t\tMX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC\t0x5fe\n-\t\t\tMX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL\t\t0x57e\n-\t\t\tMX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0\t\t\t0x57e\n-\t\t\tMX91_PAD_ENET1_TD1__ENET1_RGMII_TD1\t\t\t0x57e\n-\t\t\tMX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2\t\t\t0x57e\n-\t\t\tMX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3\t\t\t0x57e\n-\t\t\tMX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK\t0x5fe\n-\t\t\tMX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL\t\t0x57e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_eqos_sleep: eqossleepgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_ENET1_MDC__GPIO4_IO0\t\t\t\t0x31e\n-\t\t\tMX91_PAD_ENET1_MDIO__GPIO4_IO1\t\t\t\t0x31e\n-\t\t\tMX91_PAD_ENET1_RD0__GPIO4_IO10\t\t\t\t0x31e\n-\t\t\tMX91_PAD_ENET1_RD1__GPIO4_IO11\t\t\t\t0x31e\n-\t\t\tMX91_PAD_ENET1_RD2__GPIO4_IO12\t\t\t\t0x31e\n-\t\t\tMX91_PAD_ENET1_RD3__GPIO4_IO13\t\t\t\t0x31e\n-\t\t\tMX91_PAD_ENET1_RXC__GPIO4_IO9\t\t\t\t0x31e\n-\t\t\tMX91_PAD_ENET1_RX_CTL__GPIO4_IO8\t\t\t0x31e\n-\t\t\tMX91_PAD_ENET1_TD0__GPIO4_IO5\t\t\t\t0x31e\n-\t\t\tMX91_PAD_ENET1_TD1__GPIO4_IO4\t\t\t\t0x31e\n-\t\t\tMX91_PAD_ENET1_TD2__GPIO4_IO3\t\t\t\t0x31e\n-\t\t\tMX91_PAD_ENET1_TD3__GPIO4_IO2\t\t\t\t0x31e\n-\t\t\tMX91_PAD_ENET1_TXC__GPIO4_IO7\t\t\t\t0x31e\n-\t\t\tMX91_PAD_ENET1_TX_CTL__GPIO4_IO6\t\t\t0x31e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_fec: fecgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_ENET2_MDC__ENET2_MDC\t\t\t0x57e\n-\t\t\tMX91_PAD_ENET2_MDIO__ENET2_MDIO\t\t\t0x57e\n-\t\t\tMX91_PAD_ENET2_RD0__ENET2_RGMII_RD0\t\t0x57e\n-\t\t\tMX91_PAD_ENET2_RD1__ENET2_RGMII_RD1\t\t0x57e\n-\t\t\tMX91_PAD_ENET2_RD2__ENET2_RGMII_RD2\t\t0x57e\n-\t\t\tMX91_PAD_ENET2_RD3__ENET2_RGMII_RD3\t\t0x57e\n-\t\t\tMX91_PAD_ENET2_RXC__ENET2_RGMII_RXC\t\t0x5fe\n-\t\t\tMX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL\t0x57e\n-\t\t\tMX91_PAD_ENET2_TD0__ENET2_RGMII_TD0\t\t0x57e\n-\t\t\tMX91_PAD_ENET2_TD1__ENET2_RGMII_TD1\t\t0x57e\n-\t\t\tMX91_PAD_ENET2_TD2__ENET2_RGMII_TD2\t\t0x57e\n-\t\t\tMX91_PAD_ENET2_TD3__ENET2_RGMII_TD3\t\t0x57e\n-\t\t\tMX91_PAD_ENET2_TXC__ENET2_RGMII_TXC\t\t0x5fe\n-\t\t\tMX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL\t0x57e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_fec_sleep: fecsleepgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_ENET2_MDC__GPIO4_IO14\t\t\t0x51e\n-\t\t\tMX91_PAD_ENET2_MDIO__GPIO4_IO15\t\t\t0x51e\n-\t\t\tMX91_PAD_ENET2_RD0__GPIO4_IO24\t\t\t0x51e\n-\t\t\tMX91_PAD_ENET2_RD1__GPIO4_IO25\t\t\t0x51e\n-\t\t\tMX91_PAD_ENET2_RD2__GPIO4_IO26\t\t\t0x51e\n-\t\t\tMX91_PAD_ENET2_RD3__GPIO4_IO27\t\t\t0x51e\n-\t\t\tMX91_PAD_ENET2_RXC__GPIO4_IO23\t\t\t0x51e\n-\t\t\tMX91_PAD_ENET2_RX_CTL__GPIO4_IO22\t\t0x51e\n-\t\t\tMX91_PAD_ENET2_TD0__GPIO4_IO19\t\t\t0x51e\n-\t\t\tMX91_PAD_ENET2_TD1__GPIO4_IO18\t\t\t0x51e\n-\t\t\tMX91_PAD_ENET2_TD2__GPIO4_IO17\t\t\t0x51e\n-\t\t\tMX91_PAD_ENET2_TD3__GPIO4_IO16\t\t\t0x51e\n-\t\t\tMX91_PAD_ENET2_TXC__GPIO4_IO21\t\t\t0x51e\n-\t\t\tMX91_PAD_ENET2_TX_CTL__GPIO4_IO20\t\t0x51e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_lcdif_gpio: lcdifgpiogrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_GPIO_IO00__GPIO2_IO0\t\t\t0x51e\n-\t\t\tMX91_PAD_GPIO_IO01__GPIO2_IO1\t\t\t0x51e\n-\t\t\tMX91_PAD_GPIO_IO02__GPIO2_IO2\t\t\t0x51e\n-\t\t\tMX91_PAD_GPIO_IO03__GPIO2_IO3\t\t\t0x51e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_lcdif: lcdifgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9\t\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17\t0x31e\n-\t\t\tMX91_PAD_GPIO_IO27__GPIO2_IO27\t\t\t0x31e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_lpi2c1: lpi2c1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_I2C1_SCL__LPI2C1_SCL\t\t\t0x40000b9e\n-\t\t\tMX91_PAD_I2C1_SDA__LPI2C1_SDA\t\t\t0x40000b9e\n-\t\t>;\n-\t\tbootph-pre-ram;\n-\t\tbootph-some-ram;\n-\t};\n-\n-\tpinctrl_lpi2c2: lpi2c2grp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_I2C2_SCL__LPI2C2_SCL\t\t\t0x40000b9e\n-\t\t\tMX91_PAD_I2C2_SDA__LPI2C2_SDA\t\t\t0x40000b9e\n-\t\t>;\n-\t\tbootph-pre-ram;\n-\t\tbootph-some-ram;\n-\t};\n-\n-\tpinctrl_lpi2c3: lpi2c3grp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_GPIO_IO28__LPI2C3_SDA\t\t\t0x40000b9e\n-\t\t\tMX91_PAD_GPIO_IO29__LPI2C3_SCL\t\t\t0x40000b9e\n-\t\t>;\n-\t\tbootph-pre-ram;\n-\t\tbootph-some-ram;\n-\t};\n-\n-\tpinctrl_pcal6524: pcal6524grp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_CCM_CLKO2__GPIO3_IO27\t\t\t0x31e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SD2_RESET_B__GPIO3_IO7\t0x31e\n-\t\t>;\n-\t\tbootph-pre-ram;\n-\t};\n-\n-\tpinctrl_uart1: uart1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_UART1_RXD__LPUART1_RX\t\t\t0x31e\n-\t\t\tMX91_PAD_UART1_TXD__LPUART1_TX\t\t\t0x31e\n-\t\t>;\n-\t\tbootph-pre-ram;\n-\t\tbootph-some-ram;\n-\t};\n-\n-\tpinctrl_uart5: uart5grp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX\t0x31e\n-\t\t\tMX91_PAD_DAP_TDI__LPUART5_RX\t\t0x31e\n-\t\t\tMX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B\t0x31e\n-\t\t\tMX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B\t0x31e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SD1_CLK__USDHC1_CLK\t\t0x158e\n-\t\t\tMX91_PAD_SD1_CMD__USDHC1_CMD\t\t0x138e\n-\t\t\tMX91_PAD_SD1_DATA0__USDHC1_DATA0\t0x138e\n-\t\t\tMX91_PAD_SD1_DATA1__USDHC1_DATA1\t0x138e\n-\t\t\tMX91_PAD_SD1_DATA2__USDHC1_DATA2\t0x138e\n-\t\t\tMX91_PAD_SD1_DATA3__USDHC1_DATA3\t0x138e\n-\t\t\tMX91_PAD_SD1_DATA4__USDHC1_DATA4\t0x138e\n-\t\t\tMX91_PAD_SD1_DATA5__USDHC1_DATA5\t0x138e\n-\t\t\tMX91_PAD_SD1_DATA6__USDHC1_DATA6\t0x138e\n-\t\t\tMX91_PAD_SD1_DATA7__USDHC1_DATA7\t0x138e\n-\t\t\tMX91_PAD_SD1_STROBE__USDHC1_STROBE\t0x158e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SD1_CLK__USDHC1_CLK\t\t0x15fe\n-\t\t\tMX91_PAD_SD1_CMD__USDHC1_CMD\t\t0x13fe\n-\t\t\tMX91_PAD_SD1_DATA0__USDHC1_DATA0\t0x13fe\n-\t\t\tMX91_PAD_SD1_DATA1__USDHC1_DATA1\t0x13fe\n-\t\t\tMX91_PAD_SD1_DATA2__USDHC1_DATA2\t0x13fe\n-\t\t\tMX91_PAD_SD1_DATA3__USDHC1_DATA3\t0x13fe\n-\t\t\tMX91_PAD_SD1_DATA4__USDHC1_DATA4\t0x13fe\n-\t\t\tMX91_PAD_SD1_DATA5__USDHC1_DATA5\t0x13fe\n-\t\t\tMX91_PAD_SD1_DATA6__USDHC1_DATA6\t0x13fe\n-\t\t\tMX91_PAD_SD1_DATA7__USDHC1_DATA7\t0x13fe\n-\t\t\tMX91_PAD_SD1_STROBE__USDHC1_STROBE\t0x15fe\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc1: usdhc1grp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SD1_CLK__USDHC1_CLK\t\t0x1582\n-\t\t\tMX91_PAD_SD1_CMD__USDHC1_CMD\t\t0x1382\n-\t\t\tMX91_PAD_SD1_DATA0__USDHC1_DATA0\t0x1382\n-\t\t\tMX91_PAD_SD1_DATA1__USDHC1_DATA1\t0x1382\n-\t\t\tMX91_PAD_SD1_DATA2__USDHC1_DATA2\t0x1382\n-\t\t\tMX91_PAD_SD1_DATA3__USDHC1_DATA3\t0x1382\n-\t\t\tMX91_PAD_SD1_DATA4__USDHC1_DATA4\t0x1382\n-\t\t\tMX91_PAD_SD1_DATA5__USDHC1_DATA5\t0x1382\n-\t\t\tMX91_PAD_SD1_DATA6__USDHC1_DATA6\t0x1382\n-\t\t\tMX91_PAD_SD1_DATA7__USDHC1_DATA7\t0x1382\n-\t\t\tMX91_PAD_SD1_STROBE__USDHC1_STROBE\t0x1582\n-\t\t>;\n-\t\tbootph-pre-ram;\n-\t\tbootph-some-ram;\n-\t};\n-\n-\tpinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SD2_CLK__USDHC2_CLK\t\t0x158e\n-\t\t\tMX91_PAD_SD2_CMD__USDHC2_CMD\t\t0x138e\n-\t\t\tMX91_PAD_SD2_DATA0__USDHC2_DATA0\t0x138e\n-\t\t\tMX91_PAD_SD2_DATA1__USDHC2_DATA1\t0x138e\n-\t\t\tMX91_PAD_SD2_DATA2__USDHC2_DATA2\t0x138e\n-\t\t\tMX91_PAD_SD2_DATA3__USDHC2_DATA3\t0x138e\n-\t\t\tMX91_PAD_SD2_VSELECT__USDHC2_VSELECT\t0x51e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SD2_CLK__USDHC2_CLK\t\t0x15fe\n-\t\t\tMX91_PAD_SD2_CMD__USDHC2_CMD\t\t0x13fe\n-\t\t\tMX91_PAD_SD2_DATA0__USDHC2_DATA0\t0x13fe\n-\t\t\tMX91_PAD_SD2_DATA1__USDHC2_DATA1\t0x13fe\n-\t\t\tMX91_PAD_SD2_DATA2__USDHC2_DATA2\t0x13fe\n-\t\t\tMX91_PAD_SD2_DATA3__USDHC2_DATA3\t0x13fe\n-\t\t\tMX91_PAD_SD2_VSELECT__USDHC2_VSELECT\t0x51e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2_gpio: usdhc2gpiogrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SD2_CD_B__GPIO3_IO0\t\t0x31e\n-\t\t>;\n-\t\tbootph-pre-ram;\n-\t\tbootph-some-ram;\n-\t};\n-\n-\tpinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SD2_CD_B__GPIO3_IO0\t\t0x51e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc2: usdhc2grp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SD2_CLK__USDHC2_CLK\t\t0x1582\n-\t\t\tMX91_PAD_SD2_CMD__USDHC2_CMD\t\t0x1382\n-\t\t\tMX91_PAD_SD2_DATA0__USDHC2_DATA0\t0x1382\n-\t\t\tMX91_PAD_SD2_DATA1__USDHC2_DATA1\t0x1382\n-\t\t\tMX91_PAD_SD2_DATA2__USDHC2_DATA2\t0x1382\n-\t\t\tMX91_PAD_SD2_DATA3__USDHC2_DATA3\t0x1382\n-\t\t\tMX91_PAD_SD2_VSELECT__USDHC2_VSELECT\t0x51e\n-\t\t>;\n-\t\tbootph-pre-ram;\n-\t\tbootph-some-ram;\n-\t};\n-\n-\tpinctrl_usdhc2_sleep: usdhc2sleepgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SD2_CLK__GPIO3_IO1\t\t0x51e\n-\t\t\tMX91_PAD_SD2_CMD__GPIO3_IO2\t\t0x51e\n-\t\t\tMX91_PAD_SD2_DATA0__GPIO3_IO3\t\t0x51e\n-\t\t\tMX91_PAD_SD2_DATA1__GPIO3_IO4\t\t0x51e\n-\t\t\tMX91_PAD_SD2_DATA2__GPIO3_IO5\t\t0x51e\n-\t\t\tMX91_PAD_SD2_DATA3__GPIO3_IO6\t\t0x51e\n-\t\t\tMX91_PAD_SD2_VSELECT__GPIO3_IO19\t0x51e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SD3_CLK__USDHC3_CLK\t\t0x158e\n-\t\t\tMX91_PAD_SD3_CMD__USDHC3_CMD\t\t0x138e\n-\t\t\tMX91_PAD_SD3_DATA0__USDHC3_DATA0\t0x138e\n-\t\t\tMX91_PAD_SD3_DATA1__USDHC3_DATA1\t0x138e\n-\t\t\tMX91_PAD_SD3_DATA2__USDHC3_DATA2\t0x138e\n-\t\t\tMX91_PAD_SD3_DATA3__USDHC3_DATA3\t0x138e\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SD3_CLK__USDHC3_CLK\t\t0x15fe\n-\t\t\tMX91_PAD_SD3_CMD__USDHC3_CMD\t\t0x13fe\n-\t\t\tMX91_PAD_SD3_DATA0__USDHC3_DATA0\t0x13fe\n-\t\t\tMX91_PAD_SD3_DATA1__USDHC3_DATA1\t0x13fe\n-\t\t\tMX91_PAD_SD3_DATA2__USDHC3_DATA2\t0x13fe\n-\t\t\tMX91_PAD_SD3_DATA3__USDHC3_DATA3\t0x13fe\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc3: usdhc3grp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SD3_CLK__USDHC3_CLK\t\t0x1582\n-\t\t\tMX91_PAD_SD3_CMD__USDHC3_CMD\t\t0x1382\n-\t\t\tMX91_PAD_SD3_DATA0__USDHC3_DATA0\t0x1382\n-\t\t\tMX91_PAD_SD3_DATA1__USDHC3_DATA1\t0x1382\n-\t\t\tMX91_PAD_SD3_DATA2__USDHC3_DATA2\t0x1382\n-\t\t\tMX91_PAD_SD3_DATA3__USDHC3_DATA3\t0x1382\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc3_sleep: usdhc3sleepgrp {\n-\t\tfsl,pins = <\n-\t\t\tMX91_PAD_SD3_CLK__GPIO3_IO20\t\t0x31e\n-\t\t\tMX91_PAD_SD3_CMD__GPIO3_IO21\t\t0x31e\n-\t\t\tMX91_PAD_SD3_DATA0__GPIO3_IO22\t\t0x31e\n-\t\t\tMX91_PAD_SD3_DATA1__GPIO3_IO23\t\t0x31e\n-\t\t\tMX91_PAD_SD3_DATA2__GPIO3_IO24\t\t0x31e\n-\t\t\tMX91_PAD_SD3_DATA3__GPIO3_IO25\t\t0x31e\n-\t\t>;\n-\t};\n-};\ndiff --git a/arch/arm/dts/imx91-pinfunc.h b/arch/arm/dts/imx91-pinfunc.h\ndeleted file mode 100644\nindex 5677928ab7c..00000000000\n--- a/arch/arm/dts/imx91-pinfunc.h\n+++ /dev/null\n@@ -1,770 +0,0 @@\n-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */\n-/*\n- * Copyright 2024 NXP\n- */\n-\n-#ifndef __DTS_IMX91_PINFUNC_H\n-#define __DTS_IMX91_PINFUNC_H\n-\n-/*\n- * The pin function ID is a tuple of\n- * \n- */\n-#define MX91_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01b0 0x03d8 0x00 0x00\n-#define MX91_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01b0 0x0000 0x01 0x00\n-#define MX91_PAD_DAP_TDI__CAN2_TX 0x0000 0x01b0 0x0000 0x03 0x00\n-#define MX91_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01b0 0x0000 0x04 0x00\n-#define MX91_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01b0 0x0000 0x05 0x00\n-#define MX91_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01b0 0x0488 0x06 0x00\n-\n-#define MX91_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01b4 0x03dc 0x00 0x00\n-#define MX91_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01b4 0x0000 0x04 0x00\n-#define MX91_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01b4 0x0000 0x05 0x00\n-#define MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01b4 0x0000 0x06 0x00\n-\n-#define MX91_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01b8 0x03d4 0x00 0x00\n-#define MX91_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01b8 0x0000 0x04 0x00\n-#define MX91_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01b8 0x0000 0x05 0x00\n-#define MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x01b8 0x0484 0x06 0x00\n-\n-#define MX91_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000c 0x01bc 0x0000 0x00 0x00\n-#define MX91_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000c 0x01bc 0x0000 0x01 0x00\n-#define MX91_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000c 0x01bc 0x0364 0x03 0x00\n-#define MX91_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000c 0x01bc 0x0000 0x04 0x00\n-#define MX91_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000c 0x01bc 0x0000 0x05 0x00\n-#define MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000c 0x01bc 0x048c 0x06 0x00\n-\n-#define MX91_PAD_GPIO_IO00__GPIO2_IO0 0x0010 0x01c0 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x01c0 0x03f4 0x01 0x00\n-#define MX91_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01c0 0x04bc 0x02 0x00\n-#define MX91_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01c0 0x0000 0x03 0x00\n-#define MX91_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01c0 0x0000 0x04 0x00\n-#define MX91_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x01c0 0x048c 0x05 0x01\n-#define MX91_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x01c0 0x0404 0x06 0x00\n-#define MX91_PAD_GPIO_IO00__FLEXIO1_FLEXIO0 0x0010 0x01c0 0x036c 0x07 0x00\n-\n-#define MX91_PAD_GPIO_IO01__GPIO2_IO1 0x0014 0x01c4 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x01c4 0x03f0 0x01 0x00\n-#define MX91_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA0 0x0014 0x01c4 0x0490 0x02 0x00\n-#define MX91_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01c4 0x0000 0x03 0x00\n-#define MX91_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x01c4 0x0000 0x04 0x00\n-#define MX91_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x01c4 0x0488 0x05 0x01\n-#define MX91_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x01c4 0x0400 0x06 0x00\n-#define MX91_PAD_GPIO_IO01__FLEXIO1_FLEXIO1 0x0014 0x01c4 0x0370 0x07 0x00\n-\n-#define MX91_PAD_GPIO_IO02__GPIO2_IO2 0x0018 0x01c8 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x01c8 0x03fc 0x01 0x00\n-#define MX91_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x0018 0x01c8 0x04c0 0x02 0x00\n-#define MX91_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01c8 0x0000 0x03 0x00\n-#define MX91_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01c8 0x0000 0x04 0x00\n-#define MX91_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01c8 0x0484 0x05 0x01\n-#define MX91_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x01c8 0x040c 0x06 0x00\n-#define MX91_PAD_GPIO_IO02__FLEXIO1_FLEXIO2 0x0018 0x01c8 0x0374 0x07 0x00\n-\n-#define MX91_PAD_GPIO_IO03__GPIO2_IO3 0x001c 0x01cc 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO03__LPI2C4_SCL 0x001c 0x01cc 0x03f8 0x01 0x00\n-#define MX91_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x001c 0x01cc 0x04b8 0x02 0x00\n-#define MX91_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x001c 0x01cc 0x0000 0x03 0x00\n-#define MX91_PAD_GPIO_IO03__LPSPI6_SCK 0x001c 0x01cc 0x0000 0x04 0x00\n-#define MX91_PAD_GPIO_IO03__LPUART5_RTS_B 0x001c 0x01cc 0x0000 0x05 0x00\n-#define MX91_PAD_GPIO_IO03__LPI2C6_SCL 0x001c 0x01cc 0x0408 0x06 0x00\n-#define MX91_PAD_GPIO_IO03__FLEXIO1_FLEXIO3 0x001c 0x01cc 0x0378 0x07 0x00\n-\n-#define MX91_PAD_GPIO_IO04__GPIO2_IO4 0x0020 0x01d0 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x01d0 0x0000 0x01 0x00\n-#define MX91_PAD_GPIO_IO04__PDM_CLK 0x0020 0x01d0 0x0000 0x02 0x00\n-#define MX91_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA0 0x0020 0x01d0 0x0000 0x03 0x00\n-#define MX91_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x01d0 0x0000 0x04 0x00\n-#define MX91_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x01d0 0x0000 0x05 0x00\n-#define MX91_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x01d0 0x040c 0x06 0x01\n-#define MX91_PAD_GPIO_IO04__FLEXIO1_FLEXIO4 0x0020 0x01d0 0x037c 0x07 0x00\n-\n-#define MX91_PAD_GPIO_IO05__GPIO2_IO5 0x0024 0x01d4 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x01d4 0x0000 0x01 0x00\n-#define MX91_PAD_GPIO_IO05__PDM_BIT_STREAM0 0x0024 0x01d4 0x04c4 0x02 0x00\n-#define MX91_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA1 0x0024 0x01d4 0x0000 0x03 0x00\n-#define MX91_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x01d4 0x0000 0x04 0x00\n-#define MX91_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x01d4 0x0000 0x05 0x00\n-#define MX91_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x01d4 0x0408 0x06 0x01\n-#define MX91_PAD_GPIO_IO05__FLEXIO1_FLEXIO5 0x0024 0x01d4 0x0380 0x07 0x00\n-\n-#define MX91_PAD_GPIO_IO06__GPIO2_IO6 0x0028 0x01d8 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x01d8 0x0000 0x01 0x00\n-#define MX91_PAD_GPIO_IO06__PDM_BIT_STREAM1 0x0028 0x01d8 0x04c8 0x02 0x00\n-#define MX91_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA2 0x0028 0x01d8 0x0000 0x03 0x00\n-#define MX91_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x01d8 0x0000 0x04 0x00\n-#define MX91_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x01d8 0x0000 0x05 0x00\n-#define MX91_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x01d8 0x0414 0x06 0x00\n-#define MX91_PAD_GPIO_IO06__FLEXIO1_FLEXIO6 0x0028 0x01d8 0x0384 0x07 0x00\n-\n-#define MX91_PAD_GPIO_IO07__GPIO2_IO7 0x002c 0x01dc 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO07__LPSPI3_PCS1 0x002c 0x01dc 0x0000 0x01 0x00\n-#define MX91_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA1 0x002c 0x01dc 0x0494 0x02 0x00\n-#define MX91_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA3 0x002c 0x01dc 0x0000 0x03 0x00\n-#define MX91_PAD_GPIO_IO07__LPSPI7_SCK 0x002c 0x01dc 0x0000 0x04 0x00\n-#define MX91_PAD_GPIO_IO07__LPUART6_RTS_B 0x002c 0x01dc 0x0000 0x05 0x00\n-#define MX91_PAD_GPIO_IO07__LPI2C7_SCL 0x002c 0x01dc 0x0410 0x06 0x00\n-#define MX91_PAD_GPIO_IO07__FLEXIO1_FLEXIO7 0x002c 0x01dc 0x0388 0x07 0x00\n-\n-#define MX91_PAD_GPIO_IO08__GPIO2_IO8 0x0030 0x01e0 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x01e0 0x0000 0x01 0x00\n-#define MX91_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA2 0x0030 0x01e0 0x0498 0x02 0x00\n-#define MX91_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA4 0x0030 0x01e0 0x0000 0x03 0x00\n-#define MX91_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x01e0 0x0000 0x04 0x00\n-#define MX91_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x01e0 0x0000 0x05 0x00\n-#define MX91_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x01e0 0x0414 0x06 0x01\n-#define MX91_PAD_GPIO_IO08__FLEXIO1_FLEXIO8 0x0030 0x01e0 0x038c 0x07 0x00\n-\n-#define MX91_PAD_GPIO_IO09__GPIO2_IO9 0x0034 0x01e4 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x01e4 0x0000 0x01 0x00\n-#define MX91_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA3 0x0034 0x01e4 0x049c 0x02 0x00\n-#define MX91_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA5 0x0034 0x01e4 0x0000 0x03 0x00\n-#define MX91_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x01e4 0x0000 0x04 0x00\n-#define MX91_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x01e4 0x0000 0x05 0x00\n-#define MX91_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x01e4 0x0410 0x06 0x01\n-#define MX91_PAD_GPIO_IO09__FLEXIO1_FLEXIO9 0x0034 0x01e4 0x0390 0x07 0x00\n-\n-#define MX91_PAD_GPIO_IO10__GPIO2_IO10 0x0038 0x01e8 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x01e8 0x0000 0x01 0x00\n-#define MX91_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA4 0x0038 0x01e8 0x04a0 0x02 0x00\n-#define MX91_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA6 0x0038 0x01e8 0x0000 0x03 0x00\n-#define MX91_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x01e8 0x0000 0x04 0x00\n-#define MX91_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x01e8 0x0000 0x05 0x00\n-#define MX91_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x01e8 0x041c 0x06 0x00\n-#define MX91_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x0038 0x01e8 0x0394 0x07 0x00\n-\n-#define MX91_PAD_GPIO_IO11__GPIO2_IO11 0x003c 0x01ec 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO11__LPSPI3_SCK 0x003c 0x01ec 0x0000 0x01 0x00\n-#define MX91_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA5 0x003c 0x01ec 0x04a4 0x02 0x00\n-#define MX91_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA7 0x003c 0x01ec 0x0000 0x03 0x00\n-#define MX91_PAD_GPIO_IO11__TPM5_EXTCLK 0x003c 0x01ec 0x0000 0x04 0x00\n-#define MX91_PAD_GPIO_IO11__LPUART7_RTS_B 0x003c 0x01ec 0x0000 0x05 0x00\n-#define MX91_PAD_GPIO_IO11__LPI2C8_SCL 0x003c 0x01ec 0x0418 0x06 0x00\n-#define MX91_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x003c 0x01ec 0x0398 0x07 0x00\n-\n-#define MX91_PAD_GPIO_IO12__GPIO2_IO12 0x0040 0x01f0 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x01f0 0x0000 0x01 0x00\n-#define MX91_PAD_GPIO_IO12__PDM_BIT_STREAM2 0x0040 0x01f0 0x04cc 0x02 0x00\n-#define MX91_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA8 0x0040 0x01f0 0x0000 0x03 0x00\n-#define MX91_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x01f0 0x0000 0x04 0x00\n-#define MX91_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x01f0 0x0000 0x05 0x00\n-#define MX91_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x01f0 0x041c 0x06 0x01\n-#define MX91_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x01f0 0x04dc 0x07 0x00\n-\n-#define MX91_PAD_GPIO_IO13__GPIO2_IO13 0x0044 0x01f4 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x01f4 0x0000 0x01 0x00\n-#define MX91_PAD_GPIO_IO13__PDM_BIT_STREAM3 0x0044 0x01f4 0x04d0 0x02 0x00\n-#define MX91_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA9 0x0044 0x01f4 0x0000 0x03 0x00\n-#define MX91_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x01f4 0x0000 0x04 0x00\n-#define MX91_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x01f4 0x0000 0x05 0x00\n-#define MX91_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x01f4 0x0418 0x06 0x01\n-#define MX91_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x0044 0x01f4 0x039c 0x07 0x00\n-\n-#define MX91_PAD_GPIO_IO14__GPIO2_IO14 0x0048 0x01f8 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x01f8 0x0474 0x01 0x00\n-#define MX91_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA6 0x0048 0x01f8 0x04a8 0x02 0x00\n-#define MX91_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x0048 0x01f8 0x0000 0x03 0x00\n-#define MX91_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x01f8 0x0000 0x04 0x00\n-#define MX91_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x01f8 0x0000 0x05 0x00\n-#define MX91_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x01f8 0x0480 0x06 0x00\n-#define MX91_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x0048 0x01f8 0x03a0 0x07 0x00\n-\n-#define MX91_PAD_GPIO_IO15__GPIO2_IO15 0x004c 0x01fc 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO15__LPUART3_RX 0x004c 0x01fc 0x0470 0x01 0x00\n-#define MX91_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA7 0x004c 0x01fc 0x04ac 0x02 0x00\n-#define MX91_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x004c 0x01fc 0x0000 0x03 0x00\n-#define MX91_PAD_GPIO_IO15__LPSPI8_SCK 0x004c 0x01fc 0x0000 0x04 0x00\n-#define MX91_PAD_GPIO_IO15__LPUART8_RTS_B 0x004c 0x01fc 0x0000 0x05 0x00\n-#define MX91_PAD_GPIO_IO15__LPUART4_RX 0x004c 0x01fc 0x047c 0x06 0x00\n-#define MX91_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x004c 0x01fc 0x03a4 0x07 0x00\n-\n-#define MX91_PAD_GPIO_IO16__GPIO2_IO16 0x0050 0x0200 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0200 0x0000 0x01 0x00\n-#define MX91_PAD_GPIO_IO16__PDM_BIT_STREAM2 0x0050 0x0200 0x04cc 0x02 0x01\n-#define MX91_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x0050 0x0200 0x0000 0x03 0x00\n-#define MX91_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0200 0x046c 0x04 0x00\n-#define MX91_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0200 0x0000 0x05 0x00\n-#define MX91_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0200 0x0478 0x06 0x00\n-#define MX91_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x0050 0x0200 0x03a8 0x07 0x00\n-\n-#define MX91_PAD_GPIO_IO17__GPIO2_IO17 0x0054 0x0204 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0204 0x0000 0x01 0x00\n-#define MX91_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA8 0x0054 0x0204 0x04b0 0x02 0x00\n-#define MX91_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x0054 0x0204 0x0000 0x03 0x00\n-#define MX91_PAD_GPIO_IO17__LPUART3_RTS_B 0x0054 0x0204 0x0000 0x04 0x00\n-#define MX91_PAD_GPIO_IO17__LPSPI4_PCS1 0x0054 0x0204 0x0000 0x05 0x00\n-#define MX91_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0204 0x0000 0x06 0x00\n-#define MX91_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x0054 0x0204 0x03ac 0x07 0x00\n-\n-#define MX91_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x0208 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x0208 0x04d8 0x01 0x00\n-#define MX91_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA9 0x0058 0x0208 0x04b4 0x02 0x00\n-#define MX91_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x0058 0x0208 0x0000 0x03 0x00\n-#define MX91_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x0208 0x0000 0x04 0x00\n-#define MX91_PAD_GPIO_IO18__LPSPI4_PCS0 0x0058 0x0208 0x0000 0x05 0x00\n-#define MX91_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x0208 0x0000 0x06 0x00\n-#define MX91_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x0058 0x0208 0x03b0 0x07 0x00\n-\n-#define MX91_PAD_GPIO_IO19__GPIO2_IO19 0x005c 0x020c 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005c 0x020c 0x04dc 0x01 0x01\n-#define MX91_PAD_GPIO_IO19__PDM_BIT_STREAM3 0x005c 0x020c 0x04d0 0x02 0x01\n-#define MX91_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x005c 0x020c 0x0000 0x03 0x00\n-#define MX91_PAD_GPIO_IO19__LPSPI5_SIN 0x005c 0x020c 0x0000 0x04 0x00\n-#define MX91_PAD_GPIO_IO19__LPSPI4_SIN 0x005c 0x020c 0x0000 0x05 0x00\n-#define MX91_PAD_GPIO_IO19__TPM6_CH2 0x005c 0x020c 0x0000 0x06 0x00\n-#define MX91_PAD_GPIO_IO19__SAI3_TX_DATA0 0x005c 0x020c 0x0000 0x07 0x00\n-\n-#define MX91_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0210 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO20__SAI3_RX_DATA0 0x0060 0x0210 0x0000 0x01 0x00\n-#define MX91_PAD_GPIO_IO20__PDM_BIT_STREAM0 0x0060 0x0210 0x04c4 0x02 0x01\n-#define MX91_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x0060 0x0210 0x0000 0x03 0x00\n-#define MX91_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0210 0x0000 0x04 0x00\n-#define MX91_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0210 0x0000 0x05 0x00\n-#define MX91_PAD_GPIO_IO20__TPM3_CH1 0x0060 0x0210 0x0000 0x06 0x00\n-#define MX91_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 0x0060 0x0210 0x03b4 0x07 0x00\n-\n-#define MX91_PAD_GPIO_IO21__GPIO2_IO21 0x0064 0x0214 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO21__SAI3_TX_DATA0 0x0064 0x0214 0x0000 0x01 0x00\n-#define MX91_PAD_GPIO_IO21__PDM_CLK 0x0064 0x0214 0x0000 0x02 0x00\n-#define MX91_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x0064 0x0214 0x0000 0x03 0x00\n-#define MX91_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0214 0x0000 0x04 0x00\n-#define MX91_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0214 0x0000 0x05 0x00\n-#define MX91_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0214 0x0000 0x06 0x00\n-#define MX91_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0214 0x04d8 0x07 0x01\n-\n-#define MX91_PAD_GPIO_IO22__GPIO2_IO22 0x0068 0x0218 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x0218 0x04e8 0x01 0x00\n-#define MX91_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x0218 0x04e4 0x02 0x00\n-#define MX91_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x0068 0x0218 0x0000 0x03 0x00\n-#define MX91_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x0218 0x0000 0x04 0x00\n-#define MX91_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x0218 0x0000 0x05 0x00\n-#define MX91_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x0218 0x0404 0x06 0x01\n-#define MX91_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x0068 0x0218 0x03b8 0x07 0x00\n-\n-#define MX91_PAD_GPIO_IO23__GPIO2_IO23 0x006c 0x021c 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO23__USDHC3_CMD 0x006c 0x021c 0x04ec 0x01 0x00\n-#define MX91_PAD_GPIO_IO23__SPDIF_OUT 0x006c 0x021c 0x0000 0x02 0x00\n-#define MX91_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x006c 0x021c 0x0000 0x03 0x00\n-#define MX91_PAD_GPIO_IO23__TPM6_CH1 0x006c 0x021c 0x0000 0x04 0x00\n-#define MX91_PAD_GPIO_IO23__LPI2C5_SCL 0x006c 0x021c 0x0400 0x06 0x01\n-#define MX91_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x006c 0x021c 0x03bc 0x07 0x00\n-\n-#define MX91_PAD_GPIO_IO24__GPIO2_IO24 0x0070 0x0220 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0220 0x04f0 0x01 0x00\n-#define MX91_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x0070 0x0220 0x0000 0x03 0x00\n-#define MX91_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0220 0x0000 0x04 0x00\n-#define MX91_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0220 0x0000 0x05 0x00\n-#define MX91_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0220 0x0000 0x06 0x00\n-#define MX91_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x0070 0x0220 0x03c0 0x07 0x00\n-\n-#define MX91_PAD_GPIO_IO25__GPIO2_IO25 0x0074 0x0224 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0224 0x04f4 0x01 0x00\n-#define MX91_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0224 0x0000 0x02 0x00\n-#define MX91_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x0074 0x0224 0x0000 0x03 0x00\n-#define MX91_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0224 0x0000 0x04 0x00\n-#define MX91_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0224 0x03d4 0x05 0x01\n-#define MX91_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0224 0x0000 0x06 0x00\n-#define MX91_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x0074 0x0224 0x03c4 0x07 0x00\n-\n-#define MX91_PAD_GPIO_IO26__GPIO2_IO26 0x0078 0x0228 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x0228 0x04f8 0x01 0x00\n-#define MX91_PAD_GPIO_IO26__PDM_BIT_STREAM1 0x0078 0x0228 0x04c8 0x02 0x01\n-#define MX91_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x0078 0x0228 0x0000 0x03 0x00\n-#define MX91_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x0228 0x0000 0x04 0x00\n-#define MX91_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x0228 0x03d8 0x05 0x01\n-#define MX91_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x0228 0x0000 0x06 0x00\n-#define MX91_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x0228 0x04e0 0x07 0x00\n-\n-#define MX91_PAD_GPIO_IO27__GPIO2_IO27 0x007c 0x022c 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO27__USDHC3_DATA3 0x007c 0x022c 0x04fc 0x01 0x00\n-#define MX91_PAD_GPIO_IO27__CAN2_RX 0x007c 0x022c 0x0364 0x02 0x01\n-#define MX91_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x007c 0x022c 0x0000 0x03 0x00\n-#define MX91_PAD_GPIO_IO27__TPM6_CH3 0x007c 0x022c 0x0000 0x04 0x00\n-#define MX91_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007c 0x022c 0x03dc 0x05 0x01\n-#define MX91_PAD_GPIO_IO27__LPSPI5_PCS1 0x007c 0x022c 0x0000 0x06 0x00\n-#define MX91_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x007c 0x022c 0x03c8 0x07 0x00\n-\n-#define MX91_PAD_GPIO_IO28__GPIO2_IO28 0x0080 0x0230 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0230 0x03f4 0x01 0x01\n-#define MX91_PAD_GPIO_IO28__CAN1_TX 0x0080 0x0230 0x0000 0x02 0x00\n-#define MX91_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x0080 0x0230 0x0000 0x07 0x00\n-\n-#define MX91_PAD_GPIO_IO29__GPIO2_IO29 0x0084 0x0234 0x0000 0x00 0x00\n-#define MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0234 0x03f0 0x01 0x01\n-#define MX91_PAD_GPIO_IO29__CAN1_RX 0x0084 0x0234 0x0360 0x02 0x00\n-#define MX91_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x0084 0x0234 0x0000 0x07 0x00\n-\n-#define MX91_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x0088 0x0238 0x0000 0x00 0x00\n-#define MX91_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x0088 0x0238 0x0000 0x04 0x00\n-#define MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x0088 0x0238 0x0000 0x05 0x00\n-\n-#define MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x008c 0x023c 0x0000 0x05 0x00\n-#define MX91_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 0x008c 0x023c 0x0000 0x00 0x00\n-#define MX91_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x008c 0x023c 0x03c8 0x04 0x01\n-\n-#define MX91_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x0090 0x0240 0x0000 0x00 0x00\n-#define MX91_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x0090 0x0240 0x0000 0x04 0x00\n-#define MX91_PAD_CCM_CLKO3__GPIO4_IO28 0x0090 0x0240 0x0000 0x05 0x00\n-\n-#define MX91_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x0094 0x0244 0x0000 0x00 0x00\n-#define MX91_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x0094 0x0244 0x0000 0x04 0x00\n-#define MX91_PAD_CCM_CLKO4__GPIO4_IO29 0x0094 0x0244 0x0000 0x05 0x00\n-\n-#define MX91_PAD_ENET1_MDC__ENET1_MDC 0x0098 0x0248 0x0000 0x00 0x00\n-#define MX91_PAD_ENET1_MDC__LPUART3_DCB_B 0x0098 0x0248 0x0000 0x01 0x00\n-#define MX91_PAD_ENET1_MDC__I3C2_SCL 0x0098 0x0248 0x03cc 0x02 0x00\n-#define MX91_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x0098 0x0248 0x0000 0x03 0x00\n-#define MX91_PAD_ENET1_MDC__FLEXIO2_FLEXIO0 0x0098 0x0248 0x0000 0x04 0x00\n-#define MX91_PAD_ENET1_MDC__GPIO4_IO0 0x0098 0x0248 0x0000 0x05 0x00\n-#define MX91_PAD_ENET1_MDC__LPI2C1_SCL 0x0098 0x0248 0x03e0 0x06 0x00\n-\n-#define MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x009c 0x024c 0x0000 0x00 0x00\n-#define MX91_PAD_ENET1_MDIO__LPUART3_RIN_B 0x009c 0x024c 0x0000 0x01 0x00\n-#define MX91_PAD_ENET1_MDIO__I3C2_SDA 0x009c 0x024c 0x03d0 0x02 0x00\n-#define MX91_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x009c 0x024c 0x0000 0x03 0x00\n-#define MX91_PAD_ENET1_MDIO__FLEXIO2_FLEXIO1 0x009c 0x024c 0x0000 0x04 0x00\n-#define MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x009c 0x024c 0x0000 0x05 0x00\n-#define MX91_PAD_ENET1_MDIO__LPI2C1_SDA 0x009c 0x024c 0x03e4 0x06 0x00\n-\n-#define MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x00a0 0x0250 0x0000 0x00 0x00\n-#define MX91_PAD_ENET1_TD3__CAN2_TX 0x00a0 0x0250 0x0000 0x02 0x00\n-#define MX91_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 0x00a0 0x0250 0x0000 0x03 0x00\n-#define MX91_PAD_ENET1_TD3__FLEXIO2_FLEXIO2 0x00a0 0x0250 0x0000 0x04 0x00\n-#define MX91_PAD_ENET1_TD3__GPIO4_IO2 0x00a0 0x0250 0x0000 0x05 0x00\n-#define MX91_PAD_ENET1_TD3__LPI2C2_SCL 0x00a0 0x0250 0x03e8 0x06 0x00\n-\n-#define MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x00a4 0x0254 0x0000 0x00 0x00\n-#define MX91_PAD_ENET1_TD2__ENET_QOS_CLOCK_GENERATE_CLK 0x00a4 0x0254 0x0000 0x01 0x00\n-#define MX91_PAD_ENET1_TD2__CAN2_RX 0x00a4 0x0254 0x0364 0x02 0x02\n-#define MX91_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 0x00a4 0x0254 0x0000 0x03 0x00\n-#define MX91_PAD_ENET1_TD2__FLEXIO2_FLEXIO3 0x00a4 0x0254 0x0000 0x04 0x00\n-#define MX91_PAD_ENET1_TD2__GPIO4_IO3 0x00a4 0x0254 0x0000 0x05 0x00\n-#define MX91_PAD_ENET1_TD2__LPI2C2_SDA 0x00a4 0x0254 0x03ec 0x06 0x00\n-\n-#define MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x00a8 0x0258 0x0000 0x00 0x00\n-#define MX91_PAD_ENET1_TD1__LPUART3_RTS_B 0x00a8 0x0258 0x0000 0x01 0x00\n-#define MX91_PAD_ENET1_TD1__I3C2_PUR 0x00a8 0x0258 0x0000 0x02 0x00\n-#define MX91_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 0x00a8 0x0258 0x0000 0x03 0x00\n-#define MX91_PAD_ENET1_TD1__FLEXIO2_FLEXIO4 0x00a8 0x0258 0x0000 0x04 0x00\n-#define MX91_PAD_ENET1_TD1__GPIO4_IO4 0x00a8 0x0258 0x0000 0x05 0x00\n-#define MX91_PAD_ENET1_TD1__I3C2_PUR_B 0x00a8 0x0258 0x0000 0x06 0x00\n-\n-#define MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x00ac 0x025c 0x0000 0x00 0x00\n-#define MX91_PAD_ENET1_TD0__LPUART3_TX 0x00ac 0x025c 0x0474 0x01 0x01\n-#define MX91_PAD_ENET1_TD0__FLEXIO2_FLEXIO5 0x00ac 0x025c 0x0000 0x04 0x00\n-#define MX91_PAD_ENET1_TD0__GPIO4_IO5 0x00ac 0x025c 0x0000 0x05 0x00\n-\n-#define MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x00b0 0x0260 0x0000 0x00 0x00\n-#define MX91_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x00b0 0x0260 0x0000 0x01 0x00\n-#define MX91_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO6 0x00b0 0x0260 0x0000 0x04 0x00\n-#define MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x00b0 0x0260 0x0000 0x05 0x00\n-#define MX91_PAD_ENET1_TX_CTL__LPSPI2_SCK 0x00b0 0x0260 0x043c 0x02 0x00\n-\n-#define MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x00b4 0x0264 0x0000 0x00 0x00\n-#define MX91_PAD_ENET1_TXC__ENET_QOS_TX_ER 0x00b4 0x0264 0x0000 0x01 0x00\n-#define MX91_PAD_ENET1_TXC__FLEXIO2_FLEXIO7 0x00b4 0x0264 0x0000 0x04 0x00\n-#define MX91_PAD_ENET1_TXC__GPIO4_IO7 0x00b4 0x0264 0x0000 0x05 0x00\n-#define MX91_PAD_ENET1_TXC__LPSPI2_SIN 0x00b4 0x0264 0x0440 0x02 0x00\n-\n-#define MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x00b8 0x0268 0x0000 0x00 0x00\n-#define MX91_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x00b8 0x0268 0x0000 0x01 0x00\n-#define MX91_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 0x00b8 0x0268 0x0000 0x03 0x00\n-#define MX91_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO8 0x00b8 0x0268 0x0000 0x04 0x00\n-#define MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x00b8 0x0268 0x0000 0x05 0x00\n-#define MX91_PAD_ENET1_RX_CTL__LPSPI2_PCS0 0x00b8 0x0268 0x0434 0x02 0x00\n-\n-#define MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x00bc 0x026c 0x0000 0x00 0x00\n-#define MX91_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x00bc 0x026c 0x0000 0x01 0x00\n-#define MX91_PAD_ENET1_RXC__FLEXIO2_FLEXIO9 0x00bc 0x026c 0x0000 0x04 0x00\n-#define MX91_PAD_ENET1_RXC__GPIO4_IO9 0x00bc 0x026c 0x0000 0x05 0x00\n-#define MX91_PAD_ENET1_RXC__LPSPI2_SOUT 0x00bc 0x026c 0x0444 0x02 0x00\n-\n-#define MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x00c0 0x0270 0x0000 0x00 0x00\n-#define MX91_PAD_ENET1_RD0__LPUART3_RX 0x00c0 0x0270 0x0470 0x01 0x01\n-#define MX91_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x00c0 0x0270 0x0000 0x04 0x00\n-#define MX91_PAD_ENET1_RD0__GPIO4_IO10 0x00c0 0x0270 0x0000 0x05 0x00\n-\n-#define MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x00c4 0x0274 0x0000 0x00 0x00\n-#define MX91_PAD_ENET1_RD1__LPUART3_CTS_B 0x00c4 0x0274 0x046c 0x01 0x01\n-#define MX91_PAD_ENET1_RD1__LPTMR2_ALT1 0x00c4 0x0274 0x0448 0x03 0x00\n-#define MX91_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x00c4 0x0274 0x0000 0x04 0x00\n-#define MX91_PAD_ENET1_RD1__GPIO4_IO11 0x00c4 0x0274 0x0000 0x05 0x00\n-\n-#define MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x00c8 0x0278 0x0000 0x00 0x00\n-#define MX91_PAD_ENET1_RD2__LPTMR2_ALT2 0x00c8 0x0278 0x044c 0x03 0x00\n-#define MX91_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x00c8 0x0278 0x0000 0x04 0x00\n-#define MX91_PAD_ENET1_RD2__GPIO4_IO12 0x00c8 0x0278 0x0000 0x05 0x00\n-\n-#define MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x00cc 0x027c 0x0000 0x00 0x00\n-#define MX91_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x00cc 0x027c 0x0000 0x02 0x00\n-#define MX91_PAD_ENET1_RD3__LPTMR2_ALT3 0x00cc 0x027c 0x0450 0x03 0x00\n-#define MX91_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x00cc 0x027c 0x0000 0x04 0x00\n-#define MX91_PAD_ENET1_RD3__GPIO4_IO13 0x00cc 0x027c 0x0000 0x05 0x00\n-\n-#define MX91_PAD_ENET2_MDC__ENET2_MDC 0x00d0 0x0280 0x0000 0x00 0x00\n-#define MX91_PAD_ENET2_MDC__LPUART4_DCB_B 0x00d0 0x0280 0x0000 0x01 0x00\n-#define MX91_PAD_ENET2_MDC__SAI2_RX_SYNC 0x00d0 0x0280 0x0000 0x02 0x00\n-#define MX91_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 0x00d0 0x0280 0x0000 0x04 0x00\n-#define MX91_PAD_ENET2_MDC__GPIO4_IO14 0x00d0 0x0280 0x0000 0x05 0x00\n-#define MX91_PAD_ENET2_MDC__MEDIAMIX_CAM_CLK 0x00d0 0x0280 0x04bc 0x06 0x01\n-\n-#define MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x00d4 0x0284 0x0000 0x00 0x00\n-#define MX91_PAD_ENET2_MDIO__LPUART4_RIN_B 0x00d4 0x0284 0x0000 0x01 0x00\n-#define MX91_PAD_ENET2_MDIO__SAI2_RX_BCLK 0x00d4 0x0284 0x0000 0x02 0x00\n-#define MX91_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 0x00d4 0x0284 0x0000 0x04 0x00\n-#define MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x00d4 0x0284 0x0000 0x05 0x00\n-#define MX91_PAD_ENET2_MDIO__MEDIAMIX_CAM_DATA0 0x00d4 0x0284 0x0490 0x06 0x01\n-\n-#define MX91_PAD_ENET2_TD3__SAI2_RX_DATA0 0x00d8 0x0288 0x0000 0x02 0x00\n-#define MX91_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 0x00d8 0x0288 0x0000 0x04 0x00\n-#define MX91_PAD_ENET2_TD3__GPIO4_IO16 0x00d8 0x0288 0x0000 0x05 0x00\n-#define MX91_PAD_ENET2_TD3__MEDIAMIX_CAM_VSYNC 0x00d8 0x0288 0x04c0 0x06 0x01\n-#define MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x00d8 0x0288 0x0000 0x00 0x00\n-\n-#define MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x00dc 0x028c 0x0000 0x00 0x00\n-#define MX91_PAD_ENET2_TD2__ENET2_TX_CLK2 0x00dc 0x028c 0x0000 0x01 0x00\n-#define MX91_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 0x00dc 0x028c 0x0000 0x04 0x00\n-#define MX91_PAD_ENET2_TD2__GPIO4_IO17 0x00dc 0x028c 0x0000 0x05 0x00\n-#define MX91_PAD_ENET2_TD2__MEDIAMIX_CAM_HSYNC 0x00dc 0x028c 0x04b8 0x06 0x01\n-\n-#define MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x00e0 0x0290 0x0000 0x00 0x00\n-#define MX91_PAD_ENET2_TD1__LPUART4_RTS_B 0x00e0 0x0290 0x0000 0x01 0x00\n-#define MX91_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x00e0 0x0290 0x0000 0x04 0x00\n-#define MX91_PAD_ENET2_TD1__GPIO4_IO18 0x00e0 0x0290 0x0000 0x05 0x00\n-#define MX91_PAD_ENET2_TD1__MEDIAMIX_CAM_DATA1 0x00e0 0x0290 0x0494 0x06 0x01\n-\n-#define MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x00e4 0x0294 0x0000 0x00 0x00\n-#define MX91_PAD_ENET2_TD0__LPUART4_TX 0x00e4 0x0294 0x0480 0x01 0x01\n-#define MX91_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x00e4 0x0294 0x0000 0x04 0x00\n-#define MX91_PAD_ENET2_TD0__GPIO4_IO19 0x00e4 0x0294 0x0000 0x05 0x00\n-#define MX91_PAD_ENET2_TD0__MEDIAMIX_CAM_DATA2 0x00e4 0x0294 0x0498 0x06 0x01\n-\n-#define MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x00e8 0x0298 0x0000 0x00 0x00\n-#define MX91_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x00e8 0x0298 0x0000 0x01 0x00\n-#define MX91_PAD_ENET2_TX_CTL__SAI2_TX_SYNC 0x00e8 0x0298 0x0000 0x02 0x00\n-#define MX91_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 0x00e8 0x0298 0x0000 0x04 0x00\n-#define MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x00e8 0x0298 0x0000 0x05 0x00\n-#define MX91_PAD_ENET2_TX_CTL__MEDIAMIX_CAM_DATA3 0x00e8 0x0298 0x049c 0x06 0x01\n-\n-#define MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x00ec 0x029c 0x0000 0x00 0x00\n-#define MX91_PAD_ENET2_TXC__ENET2_TX_ER 0x00ec 0x029c 0x0000 0x01 0x00\n-#define MX91_PAD_ENET2_TXC__SAI2_TX_BCLK 0x00ec 0x029c 0x0000 0x02 0x00\n-#define MX91_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 0x00ec 0x029c 0x0000 0x04 0x00\n-#define MX91_PAD_ENET2_TXC__GPIO4_IO21 0x00ec 0x029c 0x0000 0x05 0x00\n-#define MX91_PAD_ENET2_TXC__MEDIAMIX_CAM_DATA4 0x00ec 0x029c 0x04a0 0x06 0x01\n-\n-#define MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x00f0 0x02a0 0x0000 0x00 0x00\n-#define MX91_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x00f0 0x02a0 0x0000 0x01 0x00\n-#define MX91_PAD_ENET2_RX_CTL__SAI2_TX_DATA0 0x00f0 0x02a0 0x0000 0x02 0x00\n-#define MX91_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 0x00f0 0x02a0 0x0000 0x04 0x00\n-#define MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x00f0 0x02a0 0x0000 0x05 0x00\n-#define MX91_PAD_ENET2_RX_CTL__MEDIAMIX_CAM_DATA5 0x00f0 0x02a0 0x04a4 0x06 0x01\n-\n-#define MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x00f4 0x02a4 0x0000 0x00 0x00\n-#define MX91_PAD_ENET2_RXC__ENET2_RX_ER 0x00f4 0x02a4 0x0000 0x01 0x00\n-#define MX91_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x00f4 0x02a4 0x0000 0x04 0x00\n-#define MX91_PAD_ENET2_RXC__GPIO4_IO23 0x00f4 0x02a4 0x0000 0x05 0x00\n-#define MX91_PAD_ENET2_RXC__MEDIAMIX_CAM_DATA6 0x00f4 0x02a4 0x04a8 0x06 0x01\n-\n-#define MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x00f8 0x02a8 0x0000 0x00 0x00\n-#define MX91_PAD_ENET2_RD0__LPUART4_RX 0x00f8 0x02a8 0x047c 0x01 0x01\n-#define MX91_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x00f8 0x02a8 0x0000 0x04 0x00\n-#define MX91_PAD_ENET2_RD0__GPIO4_IO24 0x00f8 0x02a8 0x0000 0x05 0x00\n-#define MX91_PAD_ENET2_RD0__MEDIAMIX_CAM_DATA7 0x00f8 0x02a8 0x04ac 0x06 0x01\n-\n-#define MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x00fc 0x02ac 0x0000 0x00 0x00\n-#define MX91_PAD_ENET2_RD1__SPDIF_IN 0x00fc 0x02ac 0x04e4 0x01 0x01\n-#define MX91_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x00fc 0x02ac 0x0000 0x04 0x00\n-#define MX91_PAD_ENET2_RD1__GPIO4_IO25 0x00fc 0x02ac 0x0000 0x05 0x00\n-#define MX91_PAD_ENET2_RD1__MEDIAMIX_CAM_DATA8 0x00fc 0x02ac 0x04b0 0x06 0x01\n-\n-#define MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x0100 0x02b0 0x0000 0x00 0x00\n-#define MX91_PAD_ENET2_RD2__LPUART4_CTS_B 0x0100 0x02b0 0x0478 0x01 0x01\n-#define MX91_PAD_ENET2_RD2__SAI2_MCLK 0x0100 0x02b0 0x0000 0x02 0x00\n-#define MX91_PAD_ENET2_RD2__MQS2_RIGHT 0x0100 0x02b0 0x0000 0x03 0x00\n-#define MX91_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x0100 0x02b0 0x0000 0x04 0x00\n-#define MX91_PAD_ENET2_RD2__GPIO4_IO26 0x0100 0x02b0 0x0000 0x05 0x00\n-#define MX91_PAD_ENET2_RD2__MEDIAMIX_CAM_DATA9 0x0100 0x02b0 0x04b4 0x06 0x01\n-\n-#define MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x0104 0x02b4 0x0000 0x00 0x00\n-#define MX91_PAD_ENET2_RD3__SPDIF_OUT 0x0104 0x02b4 0x0000 0x01 0x00\n-#define MX91_PAD_ENET2_RD3__SPDIF_IN 0x0104 0x02b4 0x04e4 0x02 0x02\n-#define MX91_PAD_ENET2_RD3__MQS2_LEFT 0x0104 0x02b4 0x0000 0x03 0x00\n-#define MX91_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x0104 0x02b4 0x0000 0x04 0x00\n-#define MX91_PAD_ENET2_RD3__GPIO4_IO27 0x0104 0x02b4 0x0000 0x05 0x00\n-\n-#define MX91_PAD_SD1_CLK__FLEXIO1_FLEXIO8 0x0108 0x02b8 0x038c 0x04 0x01\n-#define MX91_PAD_SD1_CLK__GPIO3_IO8 0x0108 0x02b8 0x0000 0x05 0x00\n-#define MX91_PAD_SD1_CLK__USDHC1_CLK 0x0108 0x02b8 0x0000 0x00 0x00\n-#define MX91_PAD_SD1_CLK__LPSPI2_SCK 0x0108 0x02b8 0x043c 0x03 0x01\n-\n-#define MX91_PAD_SD1_CMD__USDHC1_CMD 0x010c 0x02bc 0x0000 0x00 0x00\n-#define MX91_PAD_SD1_CMD__FLEXIO1_FLEXIO9 0x010c 0x02bc 0x0390 0x04 0x01\n-#define MX91_PAD_SD1_CMD__GPIO3_IO9 0x010c 0x02bc 0x0000 0x05 0x00\n-#define MX91_PAD_SD1_CMD__LPSPI2_SIN 0x010c 0x02bc 0x0440 0x03 0x01\n-\n-#define MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x0110 0x02c0 0x0000 0x00 0x00\n-#define MX91_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 0x0110 0x02c0 0x0394 0x04 0x01\n-#define MX91_PAD_SD1_DATA0__GPIO3_IO10 0x0110 0x02c0 0x0000 0x05 0x00\n-#define MX91_PAD_SD1_DATA0__LPSPI2_PCS0 0x0110 0x02c0 0x0434 0x03 0x01\n-\n-#define MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x0114 0x02c4 0x0000 0x00 0x00\n-#define MX91_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 0x0114 0x02c4 0x0398 0x04 0x01\n-#define MX91_PAD_SD1_DATA1__GPIO3_IO11 0x0114 0x02c4 0x0000 0x05 0x00\n-#define MX91_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT 0x0114 0x02c4 0x0000 0x06 0x00\n-#define MX91_PAD_SD1_DATA1__LPSPI2_SOUT 0x0114 0x02c4 0x0444 0x03 0x01\n-\n-#define MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x0118 0x02c8 0x0000 0x00 0x00\n-#define MX91_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 0x0118 0x02c8 0x0000 0x04 0x00\n-#define MX91_PAD_SD1_DATA2__GPIO3_IO12 0x0118 0x02c8 0x0000 0x05 0x00\n-#define MX91_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY 0x0118 0x02c8 0x0000 0x06 0x00\n-#define MX91_PAD_SD1_DATA2__LPSPI2_PCS1 0x0118 0x02c8 0x0438 0x03 0x00\n-\n-#define MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x011c 0x02cc 0x0000 0x00 0x00\n-#define MX91_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x011c 0x02cc 0x0000 0x01 0x00\n-#define MX91_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 0x011c 0x02cc 0x039c 0x04 0x01\n-#define MX91_PAD_SD1_DATA3__GPIO3_IO13 0x011c 0x02cc 0x0000 0x05 0x00\n-#define MX91_PAD_SD1_DATA3__LPSPI1_PCS1 0x011c 0x02cc 0x0424 0x03 0x00\n-\n-#define MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x0120 0x02d0 0x0000 0x00 0x00\n-#define MX91_PAD_SD1_DATA4__FLEXSPI1_A_DATA4 0x0120 0x02d0 0x0000 0x01 0x00\n-#define MX91_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 0x0120 0x02d0 0x03a0 0x04 0x01\n-#define MX91_PAD_SD1_DATA4__GPIO3_IO14 0x0120 0x02d0 0x0000 0x05 0x00\n-#define MX91_PAD_SD1_DATA4__LPSPI1_PCS0 0x0120 0x02d0 0x0420 0x03 0x00\n-\n-#define MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x0124 0x02d4 0x0000 0x00 0x00\n-#define MX91_PAD_SD1_DATA5__FLEXSPI1_A_DATA5 0x0124 0x02d4 0x0000 0x01 0x00\n-#define MX91_PAD_SD1_DATA5__USDHC1_RESET_B 0x0124 0x02d4 0x0000 0x02 0x00\n-#define MX91_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 0x0124 0x02d4 0x03a4 0x04 0x01\n-#define MX91_PAD_SD1_DATA5__GPIO3_IO15 0x0124 0x02d4 0x0000 0x05 0x00\n-#define MX91_PAD_SD1_DATA5__LPSPI1_SIN 0x0124 0x02d4 0x042c 0x03 0x00\n-\n-#define MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x0128 0x02d8 0x0000 0x00 0x00\n-#define MX91_PAD_SD1_DATA6__FLEXSPI1_A_DATA6 0x0128 0x02d8 0x0000 0x01 0x00\n-#define MX91_PAD_SD1_DATA6__USDHC1_CD_B 0x0128 0x02d8 0x0000 0x02 0x00\n-#define MX91_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 0x0128 0x02d8 0x03a8 0x04 0x01\n-#define MX91_PAD_SD1_DATA6__GPIO3_IO16 0x0128 0x02d8 0x0000 0x05 0x00\n-#define MX91_PAD_SD1_DATA6__LPSPI1_SCK 0x0128 0x02d8 0x0428 0x03 0x00\n-\n-#define MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x012c 0x02dc 0x0000 0x00 0x00\n-#define MX91_PAD_SD1_DATA7__FLEXSPI1_A_DATA7 0x012c 0x02dc 0x0000 0x01 0x00\n-#define MX91_PAD_SD1_DATA7__USDHC1_WP 0x012c 0x02dc 0x0000 0x02 0x00\n-#define MX91_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 0x012c 0x02dc 0x03ac 0x04 0x01\n-#define MX91_PAD_SD1_DATA7__GPIO3_IO17 0x012c 0x02dc 0x0000 0x05 0x00\n-#define MX91_PAD_SD1_DATA7__LPSPI1_SOUT 0x012c 0x02dc 0x0430 0x03 0x00\n-\n-#define MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x0130 0x02e0 0x0000 0x00 0x00\n-#define MX91_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x0130 0x02e0 0x0000 0x01 0x00\n-#define MX91_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 0x0130 0x02e0 0x03b0 0x04 0x01\n-#define MX91_PAD_SD1_STROBE__GPIO3_IO18 0x0130 0x02e0 0x0000 0x05 0x00\n-\n-#define MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0134 0x02e4 0x0000 0x00 0x00\n-#define MX91_PAD_SD2_VSELECT__USDHC2_WP 0x0134 0x02e4 0x0000 0x01 0x00\n-#define MX91_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0134 0x02e4 0x0450 0x02 0x01\n-#define MX91_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x0134 0x02e4 0x0000 0x04 0x00\n-#define MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x0134 0x02e4 0x0000 0x05 0x00\n-#define MX91_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x0134 0x02e4 0x0368 0x06 0x00\n-\n-#define MX91_PAD_SD3_CLK__USDHC3_CLK 0x0138 0x02e8 0x04e8 0x00 0x01\n-#define MX91_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0138 0x02e8 0x0000 0x01 0x00\n-#define MX91_PAD_SD3_CLK__LPUART1_CTS_B 0x0138 0x02e8 0x0454 0x02 0x00\n-#define MX91_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x0138 0x02e8 0x03b4 0x04 0x01\n-#define MX91_PAD_SD3_CLK__GPIO3_IO20 0x0138 0x02e8 0x0000 0x05 0x00\n-\n-#define MX91_PAD_SD3_CMD__USDHC3_CMD 0x013c 0x02ec 0x04ec 0x00 0x01\n-#define MX91_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x013c 0x02ec 0x0000 0x01 0x00\n-#define MX91_PAD_SD3_CMD__LPUART1_RTS_B 0x013c 0x02ec 0x0000 0x02 0x00\n-#define MX91_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x013c 0x02ec 0x0000 0x04 0x00\n-#define MX91_PAD_SD3_CMD__GPIO3_IO21 0x013c 0x02ec 0x0000 0x05 0x00\n-\n-#define MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x0140 0x02f0 0x04f0 0x00 0x01\n-#define MX91_PAD_SD3_DATA0__FLEXSPI1_A_DATA0 0x0140 0x02f0 0x0000 0x01 0x00\n-#define MX91_PAD_SD3_DATA0__LPUART2_CTS_B 0x0140 0x02f0 0x0460 0x02 0x00\n-#define MX91_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x0140 0x02f0 0x03b8 0x04 0x01\n-#define MX91_PAD_SD3_DATA0__GPIO3_IO22 0x0140 0x02f0 0x0000 0x05 0x00\n-\n-#define MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x0144 0x02f4 0x04f4 0x00 0x01\n-#define MX91_PAD_SD3_DATA1__FLEXSPI1_A_DATA1 0x0144 0x02f4 0x0000 0x01 0x00\n-#define MX91_PAD_SD3_DATA1__LPUART2_RTS_B 0x0144 0x02f4 0x0000 0x02 0x00\n-#define MX91_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x0144 0x02f4 0x03bc 0x04 0x01\n-#define MX91_PAD_SD3_DATA1__GPIO3_IO23 0x0144 0x02f4 0x0000 0x05 0x00\n-\n-#define MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x0148 0x02f8 0x04f8 0x00 0x01\n-#define MX91_PAD_SD3_DATA2__LPI2C4_SDA 0x0148 0x02f8 0x03fc 0x02 0x01\n-#define MX91_PAD_SD3_DATA2__FLEXSPI1_A_DATA2 0x0148 0x02f8 0x0000 0x01 0x00\n-#define MX91_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x0148 0x02f8 0x03c0 0x04 0x01\n-#define MX91_PAD_SD3_DATA2__GPIO3_IO24 0x0148 0x02f8 0x0000 0x05 0x00\n-\n-#define MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x014c 0x02fc 0x04fc 0x00 0x01\n-#define MX91_PAD_SD3_DATA3__FLEXSPI1_A_DATA3 0x014c 0x02fc 0x0000 0x01 0x00\n-#define MX91_PAD_SD3_DATA3__LPI2C4_SCL 0x014c 0x02fc 0x03f8 0x02 0x01\n-#define MX91_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x014c 0x02fc 0x03c4 0x04 0x01\n-#define MX91_PAD_SD3_DATA3__GPIO3_IO25 0x014c 0x02fc 0x0000 0x05 0x00\n-\n-#define MX91_PAD_SD2_CD_B__USDHC2_CD_B 0x0150 0x0300 0x0000 0x00 0x00\n-#define MX91_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x0150 0x0300 0x0000 0x01 0x00\n-#define MX91_PAD_SD2_CD_B__I3C2_SCL 0x0150 0x0300 0x03cc 0x02 0x01\n-#define MX91_PAD_SD2_CD_B__FLEXIO1_FLEXIO0 0x0150 0x0300 0x036c 0x04 0x01\n-#define MX91_PAD_SD2_CD_B__GPIO3_IO0 0x0150 0x0300 0x0000 0x05 0x00\n-#define MX91_PAD_SD2_CD_B__LPI2C1_SCL 0x0150 0x0300 0x03e0 0x03 0x01\n-\n-#define MX91_PAD_SD2_CLK__USDHC2_CLK 0x0154 0x0304 0x0000 0x00 0x00\n-#define MX91_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x0154 0x0304 0x0000 0x01 0x00\n-#define MX91_PAD_SD2_CLK__I2C1_SDA 0x0154 0x0304 0x0000 0x03 0x00\n-#define MX91_PAD_SD2_CLK__I3C2_SDA 0x0154 0x0304 0x03d0 0x02 0x01\n-#define MX91_PAD_SD2_CLK__FLEXIO1_FLEXIO1 0x0154 0x0304 0x0370 0x04 0x01\n-#define MX91_PAD_SD2_CLK__GPIO3_IO1 0x0154 0x0304 0x0000 0x05 0x00\n-#define MX91_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0154 0x0304 0x0000 0x06 0x00\n-#define MX91_PAD_SD2_CLK__LPI2C1_SDA 0x0154 0x0304 0x03e4 0x03 0x01\n-\n-#define MX91_PAD_SD2_CMD__USDHC2_CMD 0x0158 0x0308 0x0000 0x00 0x00\n-#define MX91_PAD_SD2_CMD__ENET2_1588_EVENT0_IN 0x0158 0x0308 0x0000 0x01 0x00\n-#define MX91_PAD_SD2_CMD__I3C2_PUR 0x0158 0x0308 0x0000 0x02 0x00\n-#define MX91_PAD_SD2_CMD__I3C2_PUR_B 0x0158 0x0308 0x0000 0x03 0x00\n-#define MX91_PAD_SD2_CMD__FLEXIO1_FLEXIO2 0x0158 0x0308 0x0374 0x04 0x01\n-#define MX91_PAD_SD2_CMD__GPIO3_IO2 0x0158 0x0308 0x0000 0x05 0x00\n-#define MX91_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x0158 0x0308 0x0000 0x06 0x00\n-\n-#define MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x015c 0x030c 0x0000 0x00 0x00\n-#define MX91_PAD_SD2_DATA0__ENET2_1588_EVENT0_OUT 0x015c 0x030c 0x0000 0x01 0x00\n-#define MX91_PAD_SD2_DATA0__CAN2_TX 0x015c 0x030c 0x0000 0x02 0x00\n-#define MX91_PAD_SD2_DATA0__FLEXIO1_FLEXIO3 0x015c 0x030c 0x0378 0x04 0x01\n-#define MX91_PAD_SD2_DATA0__GPIO3_IO3 0x015c 0x030c 0x0000 0x05 0x00\n-#define MX91_PAD_SD2_DATA0__LPUART1_TX 0x015c 0x030c 0x045c 0x03 0x00\n-#define MX91_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x015c 0x030c 0x0000 0x06 0x00\n-\n-#define MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x0160 0x0310 0x0000 0x00 0x00\n-#define MX91_PAD_SD2_DATA1__ENET2_1588_EVENT1_IN 0x0160 0x0310 0x0000 0x01 0x00\n-#define MX91_PAD_SD2_DATA1__CAN2_RX 0x0160 0x0310 0x0364 0x02 0x03\n-#define MX91_PAD_SD2_DATA1__FLEXIO1_FLEXIO4 0x0160 0x0310 0x037c 0x04 0x01\n-#define MX91_PAD_SD2_DATA1__GPIO3_IO4 0x0160 0x0310 0x0000 0x05 0x00\n-#define MX91_PAD_SD2_DATA1__LPUART1_RX 0x0160 0x0310 0x0458 0x03 0x00\n-#define MX91_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x0160 0x0310 0x0000 0x06 0x00\n-\n-#define MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x0164 0x0314 0x0000 0x00 0x00\n-#define MX91_PAD_SD2_DATA2__ENET2_1588_EVENT1_OUT 0x0164 0x0314 0x0000 0x01 0x00\n-#define MX91_PAD_SD2_DATA2__MQS2_RIGHT 0x0164 0x0314 0x0000 0x02 0x00\n-#define MX91_PAD_SD2_DATA2__FLEXIO1_FLEXIO5 0x0164 0x0314 0x0380 0x04 0x01\n-#define MX91_PAD_SD2_DATA2__GPIO3_IO5 0x0164 0x0314 0x0000 0x05 0x00\n-#define MX91_PAD_SD2_DATA2__LPUART2_TX 0x0164 0x0314 0x0468 0x03 0x00\n-#define MX91_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0164 0x0314 0x0000 0x06 0x00\n-\n-#define MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x0168 0x0318 0x0000 0x00 0x00\n-#define MX91_PAD_SD2_DATA3__LPTMR2_ALT1 0x0168 0x0318 0x0448 0x01 0x01\n-#define MX91_PAD_SD2_DATA3__MQS2_LEFT 0x0168 0x0318 0x0000 0x02 0x00\n-#define MX91_PAD_SD2_DATA3__FLEXIO1_FLEXIO6 0x0168 0x0318 0x0384 0x04 0x01\n-#define MX91_PAD_SD2_DATA3__GPIO3_IO6 0x0168 0x0318 0x0000 0x05 0x00\n-#define MX91_PAD_SD2_DATA3__LPUART2_RX 0x0168 0x0318 0x0464 0x03 0x00\n-#define MX91_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0168 0x0318 0x0000 0x06 0x00\n-\n-#define MX91_PAD_SD2_RESET_B__USDHC2_RESET_B 0x016c 0x031c 0x0000 0x00 0x00\n-#define MX91_PAD_SD2_RESET_B__LPTMR2_ALT2 0x016c 0x031c 0x044c 0x01 0x01\n-#define MX91_PAD_SD2_RESET_B__FLEXIO1_FLEXIO7 0x016c 0x031c 0x0388 0x04 0x01\n-#define MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x016c 0x031c 0x0000 0x05 0x00\n-#define MX91_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x016c 0x031c 0x0000 0x06 0x00\n-\n-#define MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x0170 0x0320 0x03e0 0x00 0x02\n-#define MX91_PAD_I2C1_SCL__I3C1_SCL 0x0170 0x0320 0x0000 0x01 0x00\n-#define MX91_PAD_I2C1_SCL__LPUART1_DCB_B 0x0170 0x0320 0x0000 0x02 0x00\n-#define MX91_PAD_I2C1_SCL__TPM2_CH0 0x0170 0x0320 0x0000 0x03 0x00\n-#define MX91_PAD_I2C1_SCL__GPIO1_IO0 0x0170 0x0320 0x0000 0x05 0x00\n-\n-#define MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x0174 0x0324 0x03e4 0x00 0x02\n-#define MX91_PAD_I2C1_SDA__I3C1_SDA 0x0174 0x0324 0x0000 0x01 0x00\n-#define MX91_PAD_I2C1_SDA__LPUART1_RIN_B 0x0174 0x0324 0x0000 0x02 0x00\n-#define MX91_PAD_I2C1_SDA__TPM2_CH1 0x0174 0x0324 0x0000 0x03 0x00\n-#define MX91_PAD_I2C1_SDA__GPIO1_IO1 0x0174 0x0324 0x0000 0x05 0x00\n-\n-#define MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x0178 0x0328 0x03e8 0x00 0x01\n-#define MX91_PAD_I2C2_SCL__I3C1_PUR 0x0178 0x0328 0x0000 0x01 0x00\n-#define MX91_PAD_I2C2_SCL__LPUART2_DCB_B 0x0178 0x0328 0x0000 0x02 0x00\n-#define MX91_PAD_I2C2_SCL__TPM2_CH2 0x0178 0x0328 0x0000 0x03 0x00\n-#define MX91_PAD_I2C2_SCL__SAI1_RX_SYNC 0x0178 0x0328 0x0000 0x04 0x00\n-#define MX91_PAD_I2C2_SCL__GPIO1_IO2 0x0178 0x0328 0x0000 0x05 0x00\n-#define MX91_PAD_I2C2_SCL__I3C1_PUR_B 0x0178 0x0328 0x0000 0x06 0x00\n-\n-#define MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x017c 0x032c 0x03ec 0x00 0x01\n-#define MX91_PAD_I2C2_SDA__LPUART2_RIN_B 0x017c 0x032c 0x0000 0x02 0x00\n-#define MX91_PAD_I2C2_SDA__TPM2_CH3 0x017c 0x032c 0x0000 0x03 0x00\n-#define MX91_PAD_I2C2_SDA__SAI1_RX_BCLK 0x017c 0x032c 0x0000 0x04 0x00\n-#define MX91_PAD_I2C2_SDA__GPIO1_IO3 0x017c 0x032c 0x0000 0x05 0x00\n-\n-#define MX91_PAD_UART1_RXD__LPUART1_RX 0x0180 0x0330 0x0458 0x00 0x01\n-#define MX91_PAD_UART1_RXD__ELE_UART_RX 0x0180 0x0330 0x0000 0x01 0x00\n-#define MX91_PAD_UART1_RXD__LPSPI2_SIN 0x0180 0x0330 0x0440 0x02 0x02\n-#define MX91_PAD_UART1_RXD__TPM1_CH0 0x0180 0x0330 0x0000 0x03 0x00\n-#define MX91_PAD_UART1_RXD__GPIO1_IO4 0x0180 0x0330 0x0000 0x05 0x00\n-\n-#define MX91_PAD_UART1_TXD__LPUART1_TX 0x0184 0x0334 0x045c 0x00 0x01\n-#define MX91_PAD_UART1_TXD__ELE_UART_TX 0x0184 0x0334 0x0000 0x01 0x00\n-#define MX91_PAD_UART1_TXD__LPSPI2_PCS0 0x0184 0x0334 0x0434 0x02 0x02\n-#define MX91_PAD_UART1_TXD__TPM1_CH1 0x0184 0x0334 0x0000 0x03 0x00\n-#define MX91_PAD_UART1_TXD__GPIO1_IO5 0x0184 0x0334 0x0000 0x05 0x00\n-\n-#define MX91_PAD_UART2_RXD__LPUART2_RX 0x0188 0x0338 0x0464 0x00 0x01\n-#define MX91_PAD_UART2_RXD__LPUART1_CTS_B 0x0188 0x0338 0x0454 0x01 0x01\n-#define MX91_PAD_UART2_RXD__LPSPI2_SOUT 0x0188 0x0338 0x0444 0x02 0x02\n-#define MX91_PAD_UART2_RXD__TPM1_CH2 0x0188 0x0338 0x0000 0x03 0x00\n-#define MX91_PAD_UART2_RXD__SAI1_MCLK 0x0188 0x0338 0x04d4 0x04 0x00\n-#define MX91_PAD_UART2_RXD__GPIO1_IO6 0x0188 0x0338 0x0000 0x05 0x00\n-\n-#define MX91_PAD_UART2_TXD__LPUART2_TX 0x018c 0x033c 0x0468 0x00 0x01\n-#define MX91_PAD_UART2_TXD__LPUART1_RTS_B 0x018c 0x033c 0x0000 0x01 0x00\n-#define MX91_PAD_UART2_TXD__LPSPI2_SCK 0x018c 0x033c 0x043c 0x02 0x02\n-#define MX91_PAD_UART2_TXD__TPM1_CH3 0x018c 0x033c 0x0000 0x03 0x00\n-#define MX91_PAD_UART2_TXD__GPIO1_IO7 0x018c 0x033c 0x0000 0x05 0x00\n-#define MX91_PAD_UART2_TXD__SAI3_TX_SYNC 0x018c 0x033c 0x04e0 0x07 0x02\n-\n-#define MX91_PAD_PDM_CLK__PDM_CLK 0x0190 0x0340 0x0000 0x00 0x00\n-#define MX91_PAD_PDM_CLK__MQS1_LEFT 0x0190 0x0340 0x0000 0x01 0x00\n-#define MX91_PAD_PDM_CLK__LPTMR1_ALT1 0x0190 0x0340 0x0000 0x04 0x00\n-#define MX91_PAD_PDM_CLK__GPIO1_IO8 0x0190 0x0340 0x0000 0x05 0x00\n-#define MX91_PAD_PDM_CLK__CAN1_TX 0x0190 0x0340 0x0000 0x06 0x00\n-\n-#define MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x0194 0x0344 0x04c4 0x00 0x02\n-#define MX91_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x0194 0x0344 0x0000 0x01 0x00\n-#define MX91_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x0194 0x0344 0x0424 0x02 0x01\n-#define MX91_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x0194 0x0344 0x0000 0x03 0x00\n-#define MX91_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x0194 0x0344 0x0000 0x04 0x00\n-#define MX91_PAD_PDM_BIT_STREAM0__GPIO1_IO9 0x0194 0x0344 0x0000 0x05 0x00\n-#define MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x0194 0x0344 0x0360 0x06 0x01\n-\n-#define MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x0198 0x0348 0x04c8 0x00 0x02\n-#define MX91_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x0198 0x0348 0x0438 0x02 0x01\n-#define MX91_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x0198 0x0348 0x0000 0x03 0x00\n-#define MX91_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 0x0198 0x0348 0x0000 0x04 0x00\n-#define MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x0198 0x0348 0x0000 0x05 0x00\n-#define MX91_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 0x0198 0x0348 0x0368 0x06 0x01\n-\n-#define MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x019c 0x034c 0x0000 0x00 0x00\n-#define MX91_PAD_SAI1_TXFS__SAI1_TX_DATA1 0x019c 0x034c 0x0000 0x01 0x00\n-#define MX91_PAD_SAI1_TXFS__LPSPI1_PCS0 0x019c 0x034c 0x0420 0x02 0x01\n-#define MX91_PAD_SAI1_TXFS__LPUART2_DTR_B 0x019c 0x034c 0x0000 0x03 0x00\n-#define MX91_PAD_SAI1_TXFS__MQS1_LEFT 0x019c 0x034c 0x0000 0x04 0x00\n-#define MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x019c 0x034c 0x0000 0x05 0x00\n-\n-#define MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x01a0 0x0350 0x0000 0x00 0x00\n-#define MX91_PAD_SAI1_TXC__LPUART2_CTS_B 0x01a0 0x0350 0x0460 0x01 0x01\n-#define MX91_PAD_SAI1_TXC__LPSPI1_SIN 0x01a0 0x0350 0x042c 0x02 0x01\n-#define MX91_PAD_SAI1_TXC__LPUART1_DSR_B 0x01a0 0x0350 0x0000 0x03 0x00\n-#define MX91_PAD_SAI1_TXC__CAN1_RX 0x01a0 0x0350 0x0360 0x04 0x02\n-#define MX91_PAD_SAI1_TXC__GPIO1_IO12 0x01a0 0x0350 0x0000 0x05 0x00\n-\n-#define MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x01a4 0x0354 0x0000 0x00 0x00\n-#define MX91_PAD_SAI1_TXD0__LPUART2_RTS_B 0x01a4 0x0354 0x0000 0x01 0x00\n-#define MX91_PAD_SAI1_TXD0__LPSPI1_SCK 0x01a4 0x0354 0x0428 0x02 0x01\n-#define MX91_PAD_SAI1_TXD0__LPUART1_DTR_B 0x01a4 0x0354 0x0000 0x03 0x00\n-#define MX91_PAD_SAI1_TXD0__CAN1_TX 0x01a4 0x0354 0x0000 0x04 0x00\n-#define MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x01a4 0x0354 0x0000 0x05 0x00\n-#define MX91_PAD_SAI1_TXD0__SAI1_MCLK 0x01a4 0x0354 0x04d4 0x06 0x01\n-\n-#define MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x01a8 0x0358 0x0000 0x00 0x00\n-#define MX91_PAD_SAI1_RXD0__SAI1_MCLK 0x01a8 0x0358 0x04d4 0x01 0x02\n-#define MX91_PAD_SAI1_RXD0__LPSPI1_SOUT 0x01a8 0x0358 0x0430 0x02 0x01\n-#define MX91_PAD_SAI1_RXD0__LPUART2_DSR_B 0x01a8 0x0358 0x0000 0x03 0x00\n-#define MX91_PAD_SAI1_RXD0__MQS1_RIGHT 0x01a8 0x0358 0x0000 0x04 0x00\n-#define MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x01a8 0x0358 0x0000 0x05 0x00\n-\n-#define MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x01ac 0x035c 0x0000 0x00 0x00\n-#define MX91_PAD_WDOG_ANY__GPIO1_IO15 0x01ac 0x035c 0x0000 0x05 0x00\n-#endif /* __DTS_IMX91_PINFUNC_H */\ndiff --git a/arch/arm/dts/imx91.dtsi b/arch/arm/dts/imx91.dtsi\ndeleted file mode 100644\nindex 9963f0bb5ce..00000000000\n--- a/arch/arm/dts/imx91.dtsi\n+++ /dev/null\n@@ -1,53 +0,0 @@\n-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n-/*\n- * Copyright 2024 NXP\n- */\n-\n-#include \"imx91-pinfunc.h\"\n-#include \"imx93.dtsi\"\n-\n-/delete-node/ &A55_1;\n-/delete-node/ &mlmix;\n-/delete-node/ &mu1;\n-/delete-node/ &mu2;\n-\n-&clk {\n-\tcompatible = \"fsl,imx91-ccm\";\n-};\n-\n-&eqos {\n-\tclocks = <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,\n-\t\t\t<&clk IMX91_CLK_ENET1_QOS_TSN_GATE>,\n-\t\t\t<&clk IMX91_CLK_ENET_TIMER>,\n-\t\t\t<&clk IMX91_CLK_ENET1_QOS_TSN>,\n-\t\t\t<&clk IMX91_CLK_ENET1_QOS_TSN_GATE>;\n-\tassigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,\n-\t\t\t\t<&clk IMX91_CLK_ENET1_QOS_TSN>;\n-\tassigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,\n-\t\t\t\t\t<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;\n-};\n-\n-&fec {\n-\tclocks = <&clk IMX91_CLK_ENET2_REGULAR_GATE>,\n-\t\t\t<&clk IMX91_CLK_ENET2_REGULAR_GATE>,\n-\t\t\t<&clk IMX91_CLK_ENET_TIMER>,\n-\t\t\t<&clk IMX91_CLK_ENET2_REGULAR>,\n-\t\t\t<&clk IMX93_CLK_DUMMY>;\n-\tassigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,\n-\t\t\t\t<&clk IMX91_CLK_ENET2_REGULAR>;\n-\tassigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,\n-\t\t\t\t\t<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;\n-\tassigned-clock-rates = <100000000>, <250000000>;\n-};\n-\n-&iomuxc {\n-\tcompatible = \"fsl,imx91-iomuxc\";\n-};\n-\n-&tmu {\n-\tstatus = \"disabled\";\n-};\n-\n-&{/thermal-zones/cpu-thermal/cooling-maps/map0} {\n-\tcooling-device = <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;\n-};\ndiff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig\nindex f072e6a9e3d..94958fc3c46 100644\n--- a/arch/arm/mach-imx/imx9/Kconfig\n+++ b/arch/arm/mach-imx/imx9/Kconfig\n@@ -68,6 +68,7 @@ config TARGET_IMX91_11X11_EVK\n \tselect IMX91\n \timply BOOTSTD_FULL\n \timply BOOTSTD_BOOTCOMMAND\n+\timply OF_UPSTREAM\n \n config TARGET_IMX91_11X11_FRDM\n \tbool \"imx91_11x11_frdm\"\n@@ -76,6 +77,7 @@ config TARGET_IMX91_11X11_FRDM\n \tselect IMX9_LPDDR4X\n \timply BOOTSTD_FULL\n \timply BOOTSTD_BOOTCOMMAND\n+\timply OF_UPSTREAM\n \n config TARGET_IMX93_9X9_QSB\n \tbool \"imx93_qsb\"\ndiff --git a/configs/imx91_11x11_evk_defconfig b/configs/imx91_11x11_evk_defconfig\nindex 0d353b6c428..49d168ac940 100644\n--- a/configs/imx91_11x11_evk_defconfig\n+++ b/configs/imx91_11x11_evk_defconfig\n@@ -11,7 +11,7 @@ CONFIG_ENV_SIZE=0x4000\n CONFIG_ENV_OFFSET=0x700000\n CONFIG_IMX_CONFIG=\"arch/arm/mach-imx/imx9/imximage.cfg\"\n CONFIG_DM_GPIO=y\n-CONFIG_DEFAULT_DEVICE_TREE=\"imx91-11x11-evk\"\n+CONFIG_DEFAULT_DEVICE_TREE=\"freescale/imx91-11x11-evk\"\n CONFIG_TARGET_IMX91_11X11_EVK=y\n CONFIG_OF_LIBFDT_OVERLAY=y\n CONFIG_SYS_MONITOR_LEN=524288\ndiff --git a/configs/imx91_11x11_evk_inline_ecc_defconfig b/configs/imx91_11x11_evk_inline_ecc_defconfig\nindex 5c14ed9113e..9d713ca70d8 100644\n--- a/configs/imx91_11x11_evk_inline_ecc_defconfig\n+++ b/configs/imx91_11x11_evk_inline_ecc_defconfig\n@@ -11,7 +11,7 @@ CONFIG_ENV_SIZE=0x4000\n CONFIG_ENV_OFFSET=0x700000\n CONFIG_IMX_CONFIG=\"arch/arm/mach-imx/imx9/imximage.cfg\"\n CONFIG_DM_GPIO=y\n-CONFIG_DEFAULT_DEVICE_TREE=\"imx91-11x11-evk\"\n+CONFIG_DEFAULT_DEVICE_TREE=\"freescale/imx91-11x11-evk\"\n CONFIG_TARGET_IMX91_11X11_EVK=y\n CONFIG_OF_LIBFDT_OVERLAY=y\n CONFIG_SYS_MONITOR_LEN=524288\ndiff --git a/configs/imx91_11x11_frdm_defconfig b/configs/imx91_11x11_frdm_defconfig\nindex a4e0a54c4bb..6405ac7912e 100644\n--- a/configs/imx91_11x11_frdm_defconfig\n+++ b/configs/imx91_11x11_frdm_defconfig\n@@ -10,7 +10,7 @@ CONFIG_ENV_SIZE=0x4000\n CONFIG_ENV_OFFSET=0x700000\n CONFIG_IMX_CONFIG=\"arch/arm/mach-imx/imx9/imximage.cfg\"\n CONFIG_DM_GPIO=y\n-CONFIG_DEFAULT_DEVICE_TREE=\"imx91-11x11-frdm\"\n+CONFIG_DEFAULT_DEVICE_TREE=\"freescale/imx91-11x11-frdm\"\n CONFIG_TARGET_IMX91_11X11_FRDM=y\n CONFIG_OF_LIBFDT_OVERLAY=y\n CONFIG_SYS_MONITOR_LEN=524288\n","prefixes":["RESEND"]}