{"id":2230925,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230925/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260430-7ulp-v1-1-f54e8c481f54@nxp.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.1/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260430-7ulp-v1-1-f54e8c481f54@nxp.com>","date":"2026-04-30T08:39:56","name":"[v1] imx7ulp: Switch to OF_UPSTREAM","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"c426c3306930f9f086db36738dfe74359810d29a","submitter":{"id":80695,"url":"http://patchwork.ozlabs.org/api/1.1/people/80695/?format=json","name":"Alice Guo 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a4da6101-3721-4731-ab26-08dea693b455","X-MS-Exchange-CrossTenant-AuthSource":"PAXPR04MB9644.eurprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"30 Apr 2026 08:37:25.6464 (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"686ea1d3-bc2b-4c6f-a92c-d99c5c301635","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n D7SLSP3JFRiRxzHBqQ5bhrmlltSdrzkK7tamADXTHDVvcZEoQx3bxnbvjJjLw6FuCWDR6v+h/Y97VIPu9Dhjtg==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DBBPR04MB7820","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"From: Alice Guo \n\nMigrate i.MX7ULP boards to use OF_UPSTREAM feature, which allows U-Boot\nto directly use device trees from the Linux kernel upstream.\n\nSigned-off-by: Alice Guo \n---\n arch/arm/dts/imx7ulp-com.dts | 79 ------\n arch/arm/dts/imx7ulp-evk.dts | 133 -----------\n arch/arm/dts/imx7ulp.dtsi | 461 ------------------------------------\n arch/arm/mach-imx/mx7ulp/Kconfig | 2 +\n configs/mx7ulp_com_defconfig | 2 +-\n configs/mx7ulp_evk_defconfig | 2 +-\n configs/mx7ulp_evk_plugin_defconfig | 2 +-\n 7 files changed, 5 insertions(+), 676 deletions(-)\n\n\n---\nbase-commit: 4433253ecf2041f9362a763bb6cb79960921ac7e\nchange-id: 20260430-7ulp-13563ce4c88e\n\nBest regards,\n-- \nAlice Guo ","diff":"diff --git a/arch/arm/dts/imx7ulp-com.dts b/arch/arm/dts/imx7ulp-com.dts\ndeleted file mode 100644\nindex d76fea3b35c..00000000000\n--- a/arch/arm/dts/imx7ulp-com.dts\n+++ /dev/null\n@@ -1,79 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0\n-//\n-// Copyright 2019 NXP\n-\n-/dts-v1/;\n-\n-#include \"imx7ulp.dtsi\"\n-#include \n-\n-/ {\n-\tmodel = \"Embedded Artists i.MX7ULP COM\";\n-\tcompatible = \"ea,imx7ulp-com\", \"fsl,imx7ulp\";\n-\n-\tchosen {\n-\t\tstdout-path = &lpuart4;\n-\t};\n-\n-\tmemory@60000000 {\n-\t\tdevice_type = \"memory\";\n-\t\treg = <0x60000000 0x4000000>;\n-\t};\n-};\n-\n-&lpuart4 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_lpuart4>;\n-\tstatus = \"okay\";\n-};\n-\n-&usbotg1 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_usbotg1_id>;\n-\tsrp-disable;\n-\thnp-disable;\n-\tadp-disable;\n-\tstatus = \"okay\";\n-};\n-\n-&usdhc0 {\n-\tassigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;\n-\tassigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_usdhc0>;\n-\tnon-removable;\n-\tbus-width = <8>;\n-\tno-1-8-v;\n-\tstatus = \"okay\";\n-};\n-\n-&iomuxc1 {\n-\tpinctrl_lpuart4: lpuart4grp {\n-\t\tfsl,pins = <\n-\t\t\tIMX7ULP_PAD_PTC3__LPUART4_RX\t0x3\n-\t\t\tIMX7ULP_PAD_PTC2__LPUART4_TX\t0x3\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usbotg1_id: otg1idgrp {\n-\t\tfsl,pins = <\n-\t\t\tIMX7ULP_PAD_PTC13__USB0_ID\t0x10003\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc0: usdhc0grp {\n-\t\tfsl,pins = <\n-\t\t\tIMX7ULP_PAD_PTD1__SDHC0_CMD\t0x43\n-\t\t\tIMX7ULP_PAD_PTD2__SDHC0_CLK\t0x10042\n-\t\t\tIMX7ULP_PAD_PTD3__SDHC0_D7\t0x43\n-\t\t\tIMX7ULP_PAD_PTD4__SDHC0_D6\t0x43\n-\t\t\tIMX7ULP_PAD_PTD5__SDHC0_D5\t0x43\n-\t\t\tIMX7ULP_PAD_PTD6__SDHC0_D4\t0x43\n-\t\t\tIMX7ULP_PAD_PTD7__SDHC0_D3\t0x43\n-\t\t\tIMX7ULP_PAD_PTD8__SDHC0_D2\t0x43\n-\t\t\tIMX7ULP_PAD_PTD9__SDHC0_D1\t0x43\n-\t\t\tIMX7ULP_PAD_PTD10__SDHC0_D0\t0x43\n-\t\t\tIMX7ULP_PAD_PTD11__SDHC0_DQS\t0x42\n-\t\t>;\n-\t};\n-};\ndiff --git a/arch/arm/dts/imx7ulp-evk.dts b/arch/arm/dts/imx7ulp-evk.dts\ndeleted file mode 100644\nindex eff51e113db..00000000000\n--- a/arch/arm/dts/imx7ulp-evk.dts\n+++ /dev/null\n@@ -1,133 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0+\n-/*\n- * Copyright 2016 Freescale Semiconductor, Inc.\n- * Copyright 2017-2018 NXP\n- * Dong Aisheng \n- */\n-\n-/dts-v1/;\n-\n-#include \"imx7ulp.dtsi\"\n-\n-/ {\n-\tmodel = \"NXP i.MX7ULP EVK\";\n-\tcompatible = \"fsl,imx7ulp-evk\", \"fsl,imx7ulp\";\n-\n-\tchosen {\n-\t\tstdout-path = &lpuart4;\n-\t};\n-\n-\tmemory@60000000 {\n-\t\tdevice_type = \"memory\";\n-\t\treg = <0x60000000 0x40000000>;\n-\t};\n-\n-\tbacklight {\n-\t\tcompatible = \"pwm-backlight\";\n-\t\tpwms = <&tpm4 1 50000 0>;\n-\t\tbrightness-levels = <0 20 25 30 35 40 100>;\n-\t\tdefault-brightness-level = <6>;\n-\t\tstatus = \"okay\";\n-\t};\n-\n-\treg_usb_otg1_vbus: regulator-usb-otg1-vbus {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_usbotg1_vbus>;\n-\t\tregulator-name = \"usb_otg1_vbus\";\n-\t\tregulator-min-microvolt = <5000000>;\n-\t\tregulator-max-microvolt = <5000000>;\n-\t\tgpio = <&gpio_ptc 0 GPIO_ACTIVE_HIGH>;\n-\t\tenable-active-high;\n-\t};\n-\n-\treg_vsd_3v3: regulator-vsd-3v3 {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"VSD_3V3\";\n-\t\tregulator-min-microvolt = <3300000>;\n-\t\tregulator-max-microvolt = <3300000>;\n-\t\tpinctrl-names = \"default\";\n-\t\tpinctrl-0 = <&pinctrl_usdhc0_rst>;\n-\t\tgpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>;\n-\t\tenable-active-high;\n-\t};\n-};\n-\n-&lpuart4 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_lpuart4>;\n-\tstatus = \"okay\";\n-};\n-\n-&tpm4 {\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_pwm0>;\n-\tstatus = \"okay\";\n-};\n-\n-&usbotg1 {\n-\tvbus-supply = <®_usb_otg1_vbus>;\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_usbotg1_id>;\n-\tsrp-disable;\n-\thnp-disable;\n-\tadp-disable;\n-\tdisable-over-current;\n-\tstatus = \"okay\";\n-};\n-\n-&usdhc0 {\n-\tassigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;\n-\tassigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>;\n-\tpinctrl-names = \"default\";\n-\tpinctrl-0 = <&pinctrl_usdhc0>;\n-\tcd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>;\n-\tvmmc-supply = <®_vsd_3v3>;\n-\tstatus = \"okay\";\n-};\n-\n-&iomuxc1 {\n-\tpinctrl_lpuart4: lpuart4grp {\n-\t\tfsl,pins = <\n-\t\t\tIMX7ULP_PAD_PTC3__LPUART4_RX\t0x3\n-\t\t\tIMX7ULP_PAD_PTC2__LPUART4_TX\t0x3\n-\t\t>;\n-\t\tbias-pull-up;\n-\t};\n-\n-\tpinctrl_pwm0: pwm0grp {\n-\t\tfsl,pins = <\n-\t\t\tIMX7ULP_PAD_PTF2__TPM4_CH1\t0x2\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usbotg1_vbus: otg1vbusgrp {\n-\t\tfsl,pins = <\n-\t\t\tIMX7ULP_PAD_PTC0__PTC0\t\t0x20000\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usbotg1_id: otg1idgrp {\n-\t\tfsl,pins = <\n-\t\t\tIMX7ULP_PAD_PTC13__USB0_ID\t0x10003\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc0: usdhc0grp {\n-\t\tfsl,pins = <\n-\t\t\tIMX7ULP_PAD_PTD1__SDHC0_CMD\t0x43\n-\t\t\tIMX7ULP_PAD_PTD2__SDHC0_CLK\t0x40\n-\t\t\tIMX7ULP_PAD_PTD7__SDHC0_D3\t0x43\n-\t\t\tIMX7ULP_PAD_PTD8__SDHC0_D2\t0x43\n-\t\t\tIMX7ULP_PAD_PTD9__SDHC0_D1\t0x43\n-\t\t\tIMX7ULP_PAD_PTD10__SDHC0_D0\t0x43\n-\t\t\tIMX7ULP_PAD_PTC10__PTC10\t0x3\t/* CD */\n-\t\t>;\n-\t};\n-\n-\tpinctrl_usdhc0_rst: usdhc0-gpio-rst-grp {\n-\t\tfsl,pins = <\n-\t\t\tIMX7ULP_PAD_PTD0__PTD0\t\t0x3\n-\t\t>;\n-\t};\n-};\ndiff --git a/arch/arm/dts/imx7ulp.dtsi b/arch/arm/dts/imx7ulp.dtsi\ndeleted file mode 100644\nindex bcec98b9641..00000000000\n--- a/arch/arm/dts/imx7ulp.dtsi\n+++ /dev/null\n@@ -1,461 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0+\n-/*\n- * Copyright (C) 2016 Freescale Semiconductor, Inc.\n- * Copyright 2017-2018 NXP\n- * Dong Aisheng \n- */\n-\n-#include \n-#include \n-#include \n-\n-#include \"imx7ulp-pinfunc.h\"\n-\n-/ {\n-\tinterrupt-parent = <&intc>;\n-\n-\t#address-cells = <1>;\n-\t#size-cells = <1>;\n-\n-\taliases {\n-\t\tgpio0 = &gpio_ptc;\n-\t\tgpio1 = &gpio_ptd;\n-\t\tgpio2 = &gpio_pte;\n-\t\tgpio3 = &gpio_ptf;\n-\t\ti2c0 = &lpi2c6;\n-\t\ti2c1 = &lpi2c7;\n-\t\tmmc0 = &usdhc0;\n-\t\tmmc1 = &usdhc1;\n-\t\tserial0 = &lpuart4;\n-\t\tserial1 = &lpuart5;\n-\t\tserial2 = &lpuart6;\n-\t\tserial3 = &lpuart7;\n-\t\tusbphy0 = &usbphy1;\n-\t};\n-\n-\tcpus {\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <0>;\n-\n-\t\tcpu0: cpu@f00 {\n-\t\t\tcompatible = \"arm,cortex-a7\";\n-\t\t\tdevice_type = \"cpu\";\n-\t\t\treg = <0xf00>;\n-\t\t};\n-\t};\n-\n-\tintc: interrupt-controller@40021000 {\n-\t\tcompatible = \"arm,cortex-a7-gic\";\n-\t\t#interrupt-cells = <3>;\n-\t\tinterrupt-controller;\n-\t\treg = <0x40021000 0x1000>,\n-\t\t <0x40022000 0x1000>;\n-\t};\n-\n-\trosc: clock-rosc {\n-\t\tcompatible = \"fixed-clock\";\n-\t\tclock-frequency = <32768>;\n-\t\tclock-output-names = \"rosc\";\n-\t\t#clock-cells = <0>;\n-\t};\n-\n-\tsosc: clock-sosc {\n-\t\tcompatible = \"fixed-clock\";\n-\t\tclock-frequency = <24000000>;\n-\t\tclock-output-names = \"sosc\";\n-\t\t#clock-cells = <0>;\n-\t};\n-\n-\tsirc: clock-sirc {\n-\t\tcompatible = \"fixed-clock\";\n-\t\tclock-frequency = <16000000>;\n-\t\tclock-output-names = \"sirc\";\n-\t\t#clock-cells = <0>;\n-\t};\n-\n-\tfirc: clock-firc {\n-\t\tcompatible = \"fixed-clock\";\n-\t\tclock-frequency = <48000000>;\n-\t\tclock-output-names = \"firc\";\n-\t\t#clock-cells = <0>;\n-\t};\n-\n-\tupll: clock-upll {\n-\t\tcompatible = \"fixed-clock\";\n-\t\tclock-frequency = <480000000>;\n-\t\tclock-output-names = \"upll\";\n-\t\t#clock-cells = <0>;\n-\t};\n-\n-\tahbbridge0: bus@40000000 {\n-\t\tcompatible = \"simple-bus\";\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <1>;\n-\t\treg = <0x40000000 0x800000>;\n-\t\tranges;\n-\n-\t\tedma1: dma-controller@40080000 {\n-\t\t\t#dma-cells = <2>;\n-\t\t\tcompatible = \"fsl,imx7ulp-edma\";\n-\t\t\treg = <0x40080000 0x2000>,\n-\t\t\t\t<0x40210000 0x1000>;\n-\t\t\tdma-channels = <32>;\n-\t\t\tinterrupts = ,\n-\t\t\t\t ,\n-\t\t\t\t ,\n-\t\t\t\t ,\n-\t\t\t\t ,\n-\t\t\t\t ,\n-\t\t\t\t ,\n-\t\t\t\t ,\n-\t\t\t\t ,\n-\t\t\t\t ,\n-\t\t\t\t ,\n-\t\t\t\t ,\n-\t\t\t\t ,\n-\t\t\t\t ,\n-\t\t\t\t ,\n-\t\t\t\t ,\n-\t\t\t\t ;\n-\t\t\tclock-names = \"dma\", \"dmamux0\";\n-\t\t\tclocks = <&pcc2 IMX7ULP_CLK_DMA1>,\n-\t\t\t\t <&pcc2 IMX7ULP_CLK_DMA_MUX1>;\n-\t\t};\n-\n-\t\tcrypto: crypto@40240000 {\n-\t\t\tcompatible = \"fsl,sec-v4.0\";\n-\t\t\t#address-cells = <1>;\n-\t\t\t#size-cells = <1>;\n-\t\t\treg = <0x40240000 0x10000>;\n-\t\t\tranges = <0 0x40240000 0x10000>;\n-\t\t\tclocks = <&pcc2 IMX7ULP_CLK_CAAM>,\n-\t\t\t\t <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;\n-\t\t\tclock-names = \"aclk\", \"ipg\";\n-\n-\t\t\tsec_jr0: jr@1000 {\n-\t\t\t\tcompatible = \"fsl,sec-v4.0-job-ring\";\n-\t\t\t\treg = <0x1000 0x1000>;\n-\t\t\t\tinterrupts = ;\n-\t\t\t};\n-\n-\t\t\tsec_jr1: jr@2000 {\n-\t\t\t\tcompatible = \"fsl,sec-v4.0-job-ring\";\n-\t\t\t\treg = <0x2000 0x1000>;\n-\t\t\t\tinterrupts = ;\n-\t\t\t};\n-\t\t};\n-\n-\t\tlpuart4: serial@402d0000 {\n-\t\t\tcompatible = \"fsl,imx7ulp-lpuart\";\n-\t\t\treg = <0x402d0000 0x1000>;\n-\t\t\tinterrupts = ;\n-\t\t\tclocks = <&pcc2 IMX7ULP_CLK_LPUART4>;\n-\t\t\tclock-names = \"ipg\";\n-\t\t\tassigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;\n-\t\t\tassigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;\n-\t\t\tassigned-clock-rates = <24000000>;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tlpuart5: serial@402e0000 {\n-\t\t\tcompatible = \"fsl,imx7ulp-lpuart\";\n-\t\t\treg = <0x402e0000 0x1000>;\n-\t\t\tinterrupts = ;\n-\t\t\tclocks = <&pcc2 IMX7ULP_CLK_LPUART5>;\n-\t\t\tclock-names = \"ipg\";\n-\t\t\tassigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;\n-\t\t\tassigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;\n-\t\t\tassigned-clock-rates = <48000000>;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\ttpm4: pwm@40250000 {\n-\t\t\tcompatible = \"fsl,imx7ulp-pwm\";\n-\t\t\treg = <0x40250000 0x1000>;\n-\t\t\tassigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;\n-\t\t\tassigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;\n-\t\t\tclocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;\n-\t\t\t#pwm-cells = <3>;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\ttpm5: tpm@40260000 {\n-\t\t\tcompatible = \"fsl,imx7ulp-tpm\";\n-\t\t\treg = <0x40260000 0x1000>;\n-\t\t\tinterrupts = ;\n-\t\t\tclocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,\n-\t\t\t\t <&pcc2 IMX7ULP_CLK_LPTPM5>;\n-\t\t\tclock-names = \"ipg\", \"per\";\n-\t\t};\n-\n-\t\tusbotg1: usb@40330000 {\n-\t\t\tcompatible = \"fsl,imx7ulp-usb\", \"fsl,imx6ul-usb\";\n-\t\t\treg = <0x40330000 0x200>;\n-\t\t\tinterrupts = ;\n-\t\t\tclocks = <&pcc2 IMX7ULP_CLK_USB0>;\n-\t\t\tphys = <&usbphy1>;\n-\t\t\tfsl,usbmisc = <&usbmisc1 0>;\n-\t\t\tahb-burst-config = <0x0>;\n-\t\t\ttx-burst-size-dword = <0x8>;\n-\t\t\trx-burst-size-dword = <0x8>;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tusbmisc1: usbmisc@40330200 {\n-\t\t\tcompatible = \"fsl,imx7ulp-usbmisc\", \"fsl,imx7d-usbmisc\";\n-\t\t\t#index-cells = <1>;\n-\t\t\treg = <0x40330200 0x200>;\n-\t\t};\n-\n-\t\tusbphy1: usb-phy@40350000 {\n-\t\t\tcompatible = \"fsl,imx7ulp-usbphy\", \"fsl,imx6ul-usbphy\";\n-\t\t\treg = <0x40350000 0x1000>;\n-\t\t\tinterrupts = ;\n-\t\t\tclocks = <&pcc2 IMX7ULP_CLK_USB_PHY>;\n-\t\t\t#phy-cells = <0>;\n-\t\t};\n-\n-\t\tusdhc0: mmc@40370000 {\n-\t\t\tcompatible = \"fsl,imx7ulp-usdhc\", \"fsl,imx6sx-usdhc\";\n-\t\t\treg = <0x40370000 0x10000>;\n-\t\t\tinterrupts = ;\n-\t\t\tclocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,\n-\t\t\t\t <&scg1 IMX7ULP_CLK_NIC1_DIV>,\n-\t\t\t\t <&pcc2 IMX7ULP_CLK_USDHC0>;\n-\t\t\tclock-names = \"ipg\", \"ahb\", \"per\";\n-\t\t\tbus-width = <4>;\n-\t\t\tfsl,tuning-start-tap = <20>;\n-\t\t\tfsl,tuning-step = <2>;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tusdhc1: mmc@40380000 {\n-\t\t\tcompatible = \"fsl,imx7ulp-usdhc\", \"fsl,imx6sx-usdhc\";\n-\t\t\treg = <0x40380000 0x10000>;\n-\t\t\tinterrupts = ;\n-\t\t\tclocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,\n-\t\t\t\t <&scg1 IMX7ULP_CLK_NIC1_DIV>,\n-\t\t\t\t <&pcc2 IMX7ULP_CLK_USDHC1>;\n-\t\t\tclock-names = \"ipg\", \"ahb\", \"per\";\n-\t\t\tbus-width = <4>;\n-\t\t\tfsl,tuning-start-tap = <20>;\n-\t\t\tfsl,tuning-step = <2>;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tscg1: clock-controller@403e0000 {\n-\t\t\tcompatible = \"fsl,imx7ulp-scg1\";\n-\t\t\treg = <0x403e0000 0x10000>;\n-\t\t\tclocks = <&rosc>, <&sosc>, <&sirc>,\n-\t\t\t\t <&firc>, <&upll>;\n-\t\t\tclock-names = \"rosc\", \"sosc\", \"sirc\",\n-\t\t\t\t \"firc\", \"upll\";\n-\t\t\t#clock-cells = <1>;\n-\t\t};\n-\n-\t\twdog1: watchdog@403d0000 {\n-\t\t\tcompatible = \"fsl,imx7ulp-wdt\";\n-\t\t\treg = <0x403d0000 0x10000>;\n-\t\t\tinterrupts = ;\n-\t\t\tclocks = <&pcc2 IMX7ULP_CLK_WDG1>;\n-\t\t\tassigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;\n-\t\t\tassigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;\n-\t\t\ttimeout-sec = <40>;\n-\t\t};\n-\n-\t\tpcc2: clock-controller@403f0000 {\n-\t\t\tcompatible = \"fsl,imx7ulp-pcc2\";\n-\t\t\treg = <0x403f0000 0x10000>;\n-\t\t\t#clock-cells = <1>;\n-\t\t\tclocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,\n-\t\t\t\t <&scg1 IMX7ULP_CLK_NIC1_DIV>,\n-\t\t\t\t <&scg1 IMX7ULP_CLK_DDR_DIV>,\n-\t\t\t\t <&scg1 IMX7ULP_CLK_APLL_PFD2>,\n-\t\t\t\t <&scg1 IMX7ULP_CLK_APLL_PFD1>,\n-\t\t\t\t <&scg1 IMX7ULP_CLK_APLL_PFD0>,\n-\t\t\t\t <&scg1 IMX7ULP_CLK_UPLL>,\n-\t\t\t\t <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,\n-\t\t\t\t <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,\n-\t\t\t\t <&scg1 IMX7ULP_CLK_ROSC>,\n-\t\t\t\t <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;\n-\t\t\tclock-names = \"nic1_bus_clk\", \"nic1_clk\", \"ddr_clk\",\n-\t\t\t\t \"apll_pfd2\", \"apll_pfd1\", \"apll_pfd0\",\n-\t\t\t\t \"upll\", \"sosc_bus_clk\",\n-\t\t\t\t \"firc_bus_clk\", \"rosc\", \"spll_bus_clk\";\n-\t\t\tassigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;\n-\t\t\tassigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;\n-\t\t};\n-\n-\t\tsmc1: clock-controller@40410000 {\n-\t\t\tcompatible = \"fsl,imx7ulp-smc1\";\n-\t\t\treg = <0x40410000 0x1000>;\n-\t\t\t#clock-cells = <1>;\n-\t\t\tclocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,\n-\t\t\t\t <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;\n-\t\t\tclock-names = \"divcore\", \"hsrun_divcore\";\n-\t\t};\n-\n-\t\tpcc3: clock-controller@40b30000 {\n-\t\t\tcompatible = \"fsl,imx7ulp-pcc3\";\n-\t\t\treg = <0x40b30000 0x10000>;\n-\t\t\t#clock-cells = <1>;\n-\t\t\tclocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,\n-\t\t\t\t <&scg1 IMX7ULP_CLK_NIC1_DIV>,\n-\t\t\t\t <&scg1 IMX7ULP_CLK_DDR_DIV>,\n-\t\t\t\t <&scg1 IMX7ULP_CLK_APLL_PFD2>,\n-\t\t\t\t <&scg1 IMX7ULP_CLK_APLL_PFD1>,\n-\t\t\t\t <&scg1 IMX7ULP_CLK_APLL_PFD0>,\n-\t\t\t\t <&scg1 IMX7ULP_CLK_UPLL>,\n-\t\t\t\t <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,\n-\t\t\t\t <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,\n-\t\t\t\t <&scg1 IMX7ULP_CLK_ROSC>,\n-\t\t\t\t <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;\n-\t\t\tclock-names = \"nic1_bus_clk\", \"nic1_clk\", \"ddr_clk\",\n-\t\t\t\t \"apll_pfd2\", \"apll_pfd1\", \"apll_pfd0\",\n-\t\t\t\t \"upll\", \"sosc_bus_clk\",\n-\t\t\t\t \"firc_bus_clk\", \"rosc\", \"spll_bus_clk\";\n-\t\t};\n-\t};\n-\n-\tahbbridge1: bus@40800000 {\n-\t\tcompatible = \"simple-bus\";\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <1>;\n-\t\treg = <0x40800000 0x800000>;\n-\t\tranges;\n-\n-\t\tlpi2c6: i2c@40a40000 {\n-\t\t\tcompatible = \"fsl,imx7ulp-lpi2c\";\n-\t\t\treg = <0x40a40000 0x10000>;\n-\t\t\tinterrupts = ;\n-\t\t\tclocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;\n-\t\t\tclock-names = \"ipg\";\n-\t\t\tassigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;\n-\t\t\tassigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;\n-\t\t\tassigned-clock-rates = <48000000>;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tlpi2c7: i2c@40a50000 {\n-\t\t\tcompatible = \"fsl,imx7ulp-lpi2c\";\n-\t\t\treg = <0x40a50000 0x10000>;\n-\t\t\tinterrupts = ;\n-\t\t\tclocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;\n-\t\t\tclock-names = \"ipg\";\n-\t\t\tassigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;\n-\t\t\tassigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;\n-\t\t\tassigned-clock-rates = <48000000>;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tlpuart6: serial@40a60000 {\n-\t\t\tcompatible = \"fsl,imx7ulp-lpuart\";\n-\t\t\treg = <0x40a60000 0x1000>;\n-\t\t\tinterrupts = ;\n-\t\t\tclocks = <&pcc3 IMX7ULP_CLK_LPUART6>;\n-\t\t\tclock-names = \"ipg\";\n-\t\t\tassigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;\n-\t\t\tassigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;\n-\t\t\tassigned-clock-rates = <48000000>;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tlpuart7: serial@40a70000 {\n-\t\t\tcompatible = \"fsl,imx7ulp-lpuart\";\n-\t\t\treg = <0x40a70000 0x1000>;\n-\t\t\tinterrupts = ;\n-\t\t\tclocks = <&pcc3 IMX7ULP_CLK_LPUART7>;\n-\t\t\tclock-names = \"ipg\";\n-\t\t\tassigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;\n-\t\t\tassigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;\n-\t\t\tassigned-clock-rates = <48000000>;\n-\t\t\tstatus = \"disabled\";\n-\t\t};\n-\n-\t\tmemory-controller@40ab0000 {\n-\t\t\tcompatible = \"fsl,imx7ulp-mmdc\", \"fsl,imx6q-mmdc\";\n-\t\t\treg = <0x40ab0000 0x1000>;\n-\t\t\tclocks = <&pcc3 IMX7ULP_CLK_MMDC>;\n-\t\t};\n-\n-\t\tiomuxc1: pinctrl@40ac0000 {\n-\t\t\tcompatible = \"fsl,imx7ulp-iomuxc1\";\n-\t\t\treg = <0x40ac0000 0x1000>;\n-\t\t};\n-\n-\t\tgpio_ptc: gpio@40ae0000 {\n-\t\t\tcompatible = \"fsl,imx7ulp-gpio\", \"fsl,vf610-gpio\";\n-\t\t\treg = <0x40ae0000 0x1000 0x400f0000 0x40>;\n-\t\t\tgpio-controller;\n-\t\t\t#gpio-cells = <2>;\n-\t\t\tinterrupts = ;\n-\t\t\tinterrupt-controller;\n-\t\t\t#interrupt-cells = <2>;\n-\t\t\tclocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,\n-\t\t\t\t <&pcc3 IMX7ULP_CLK_PCTLC>;\n-\t\t\tclock-names = \"gpio\", \"port\";\n-\t\t\tgpio-ranges = <&iomuxc1 0 0 20>;\n-\t\t};\n-\n-\t\tgpio_ptd: gpio@40af0000 {\n-\t\t\tcompatible = \"fsl,imx7ulp-gpio\", \"fsl,vf610-gpio\";\n-\t\t\treg = <0x40af0000 0x1000 0x400f0040 0x40>;\n-\t\t\tgpio-controller;\n-\t\t\t#gpio-cells = <2>;\n-\t\t\tinterrupts = ;\n-\t\t\tinterrupt-controller;\n-\t\t\t#interrupt-cells = <2>;\n-\t\t\tclocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,\n-\t\t\t\t <&pcc3 IMX7ULP_CLK_PCTLD>;\n-\t\t\tclock-names = \"gpio\", \"port\";\n-\t\t\tgpio-ranges = <&iomuxc1 0 32 12>;\n-\t\t};\n-\n-\t\tgpio_pte: gpio@40b00000 {\n-\t\t\tcompatible = \"fsl,imx7ulp-gpio\", \"fsl,vf610-gpio\";\n-\t\t\treg = <0x40b00000 0x1000 0x400f0080 0x40>;\n-\t\t\tgpio-controller;\n-\t\t\t#gpio-cells = <2>;\n-\t\t\tinterrupts = ;\n-\t\t\tinterrupt-controller;\n-\t\t\t#interrupt-cells = <2>;\n-\t\t\tclocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,\n-\t\t\t\t <&pcc3 IMX7ULP_CLK_PCTLE>;\n-\t\t\tclock-names = \"gpio\", \"port\";\n-\t\t\tgpio-ranges = <&iomuxc1 0 64 16>;\n-\t\t};\n-\n-\t\tgpio_ptf: gpio@40b10000 {\n-\t\t\tcompatible = \"fsl,imx7ulp-gpio\", \"fsl,vf610-gpio\";\n-\t\t\treg = <0x40b10000 0x1000 0x400f00c0 0x40>;\n-\t\t\tgpio-controller;\n-\t\t\t#gpio-cells = <2>;\n-\t\t\tinterrupts = ;\n-\t\t\tinterrupt-controller;\n-\t\t\t#interrupt-cells = <2>;\n-\t\t\tclocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,\n-\t\t\t\t <&pcc3 IMX7ULP_CLK_PCTLF>;\n-\t\t\tclock-names = \"gpio\", \"port\";\n-\t\t\tgpio-ranges = <&iomuxc1 0 96 20>;\n-\t\t};\n-\t};\n-\n-\tm4aips1: bus@41080000 {\n-\t\tcompatible = \"simple-bus\";\n-\t\t#address-cells = <1>;\n-\t\t#size-cells = <1>;\n-\t\treg = <0x41080000 0x80000>;\n-\t\tranges;\n-\n-\t\tsim: sim@410a3000 {\n-\t\t\tcompatible = \"fsl,imx7ulp-sim\", \"syscon\";\n-\t\t\treg = <0x410a3000 0x1000>;\n-\t\t};\n-\n-\t\tocotp: efuse@410a6000 {\n-\t\t\tcompatible = \"fsl,imx7ulp-ocotp\", \"syscon\";\n-\t\t\treg = <0x410a6000 0x4000>;\n-\t\t\tclocks = <&scg1 IMX7ULP_CLK_DUMMY>;\n-\t\t};\n-\t};\n-};\ndiff --git a/arch/arm/mach-imx/mx7ulp/Kconfig b/arch/arm/mach-imx/mx7ulp/Kconfig\nindex e8cb58bc89f..eac3a2ad6af 100644\n--- a/arch/arm/mach-imx/mx7ulp/Kconfig\n+++ b/arch/arm/mach-imx/mx7ulp/Kconfig\n@@ -35,6 +35,7 @@ config TARGET_MX7ULP_COM\n \tselect SPL_SEPARATE_BSS if SPL\n \tselect SPL_SERIAL if SPL\n \tselect SUPPORT_SPL\n+\timply OF_UPSTREAM\n \n config TARGET_MX7ULP_EVK\n \tbool \"Support mx7ulp EVK board\"\n@@ -42,6 +43,7 @@ config TARGET_MX7ULP_EVK\n \tselect SYS_ARCH_TIMER\n \tselect FSL_CAAM\n \tselect ARCH_MISC_INIT\n+\timply OF_UPSTREAM\n \n endchoice\n \ndiff --git a/configs/mx7ulp_com_defconfig b/configs/mx7ulp_com_defconfig\nindex a49cb2a728f..d63168fe886 100644\n--- a/configs/mx7ulp_com_defconfig\n+++ b/configs/mx7ulp_com_defconfig\n@@ -7,7 +7,7 @@ CONFIG_SF_DEFAULT_SPEED=40000000\n CONFIG_ENV_SIZE=0x2000\n CONFIG_ENV_OFFSET=0xC0000\n CONFIG_DM_GPIO=y\n-CONFIG_DEFAULT_DEVICE_TREE=\"imx7ulp-com\"\n+CONFIG_DEFAULT_DEVICE_TREE=\"nxp/imx/imx7ulp-com\"\n CONFIG_LDO_ENABLED_MODE=y\n CONFIG_TARGET_MX7ULP_COM=y\n CONFIG_SYS_BOOTM_LEN=0x1000000\ndiff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig\nindex 98b99dd78e1..6a42acc16ef 100644\n--- a/configs/mx7ulp_evk_defconfig\n+++ b/configs/mx7ulp_evk_defconfig\n@@ -6,7 +6,7 @@ CONFIG_NR_DRAM_BANKS=1\n CONFIG_ENV_SIZE=0x2000\n CONFIG_ENV_OFFSET=0xC0000\n CONFIG_DM_GPIO=y\n-CONFIG_DEFAULT_DEVICE_TREE=\"imx7ulp-evk\"\n+CONFIG_DEFAULT_DEVICE_TREE=\"nxp/imx/imx7ulp-evk\"\n CONFIG_TARGET_MX7ULP_EVK=y\n CONFIG_SYS_BOOTM_LEN=0x1000000\n CONFIG_SYS_LOAD_ADDR=0x60800000\ndiff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig\nindex af0efbd3ebf..148b706d17a 100644\n--- a/configs/mx7ulp_evk_plugin_defconfig\n+++ b/configs/mx7ulp_evk_plugin_defconfig\n@@ -6,7 +6,7 @@ CONFIG_NR_DRAM_BANKS=1\n CONFIG_ENV_SIZE=0x2000\n CONFIG_ENV_OFFSET=0xC0000\n CONFIG_DM_GPIO=y\n-CONFIG_DEFAULT_DEVICE_TREE=\"imx7ulp-evk\"\n+CONFIG_DEFAULT_DEVICE_TREE=\"nxp/imx/imx7ulp-evk\"\n CONFIG_TARGET_MX7ULP_EVK=y\n CONFIG_SYS_BOOTM_LEN=0x1000000\n CONFIG_SYS_LOAD_ADDR=0x60800000\n","prefixes":["v1"]}