{"id":2230917,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230917/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/20260430082121.15562-1-chenglulu@loongson.cn/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/1.1/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260430082121.15562-1-chenglulu@loongson.cn>","date":"2026-04-30T08:21:21","name":"LoongArch: Fix ICE caused by incomplete split conditions [PR125057].","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"d36e878576c307db8acd07474ba4b8b8b6ec3a99","submitter":{"id":82960,"url":"http://patchwork.ozlabs.org/api/1.1/people/82960/?format=json","name":"Lulu Cheng","email":"chenglulu@loongson.cn"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/20260430082121.15562-1-chenglulu@loongson.cn/mbox/","series":[{"id":502231,"url":"http://patchwork.ozlabs.org/api/1.1/series/502231/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=502231","date":"2026-04-30T08:21:21","name":"LoongArch: Fix ICE caused by incomplete split conditions [PR125057].","version":1,"mbox":"http://patchwork.ozlabs.org/series/502231/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230917/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230917/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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bh=FRut+XTNqa1J4pbgLB/oCOHJkeUO/2C1Gyj87ioBEcI=;\n h=From:To:Subject:Date:Message-Id:MIME-Version;\n b=XvUrNAZSWwRNpwPx+PlLwEfniKFIZCR4G9EWcJ8whFEnufsS9gYM+F/XSeEIz3wE+fJroxKoKekD6CZQ1ixK7IpH3IzaBjP3Fhal7HiIqISOaKF2Xo2lG5K2f1/b1g65WEBoOKaYH/zij/YjETuQ96WmVB0qPbp+QuZqnC8sIeA=","ARC-Authentication-Results":"i=1; server2.sourceware.org","From":"Lulu Cheng ","To":"gcc-patches@gcc.gnu.org,\n\tchenglulu@loongson.cn","Cc":"xry111@xry111.site,\n\ti@xen0n.name,\n\txuchenghua@loongson.cn","Subject":"[PATCH] LoongArch: Fix ICE caused by incomplete split conditions\n [PR125057].","Date":"Thu, 30 Apr 2026 16:21:21 +0800","Message-Id":"<20260430082121.15562-1-chenglulu@loongson.cn>","X-Mailer":"git-send-email 2.20.1","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-CM-TRANSID":"qMiowJDx6+CsEPNp7fx3AA--.32713S2","X-CM-SenderInfo":"xfkh0wpoxo3qxorr0wxvrqhubq/","X-Coremail-Antispam":"1Uk129KBj93XoWxKF4DKF4fuF43AFy5KFWkZrc_yoW7Ar1UpF\n y7uwnxtF48JFn3Xr17Ga4rXF43tF97Wr42va4Syw10kFZrGryqg3ZYyr9xWF13XayF9rW2\n qrnY9w15u3WUXwbCm3ZEXasCq-sJn29KB7ZKAUJUUUU5529EdanIXcx71UUUUU7KY7ZEXa\n sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU\n 0xBIdaVrnRJUUUkFb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2\n IYs7xG6rWj6s0DM7CIcVAFz4kK6r106r15M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v\n e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI\n 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK\n xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx\n 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1Y6r17McIj6I8E87Iv\n 67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2\n Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02\n 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF0x\n vE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE\n 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6x\n kF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x07j1YL9UUUUU=","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"Since the split conditions in loongarch_split_vector_move are incomplete,\nthe following RTL:\n\n\t(set (reg:V4DI 32 $f0) (subreg:V4DI (reg:V2DI 32 $f0) 0))\n\nis incorrectly split, leading to an ICE.\n\nThis patch fixes the issue by completing the split conditions.\n\n\tPR target/125057\n\ngcc/ChangeLog:\n\n\t* config/loongarch/loongarch.cc\n\t(loongarch_split_vector_move): Complete the split condition.\n\t* config/loongarch/loongarch.h (LSX_REG_RTX_P): Delete.\n\t(LASX_REG_RTX_P): Delete.\n\t(GP_REG_RTX_P): Define macro.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/loongarch/vector/lasx/pr125057.c: New test.\n\t* gcc.target/loongarch/vector/lsx/lsx-mov-2.c: New test.\n\n---\n gcc/config/loongarch/loongarch.cc | 41 +++++++++++++++++--\n gcc/config/loongarch/loongarch.h | 3 +-\n .../loongarch/vector/lasx/pr125057.c | 25 +++++++++++\n .../loongarch/vector/lsx/lsx-mov-2.c | 13 ++++++\n 4 files changed, 76 insertions(+), 6 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lasx/pr125057.c\n create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-mov-2.c","diff":"diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc\nindex 134ed47afdf..4a0a9bafa81 100644\n--- a/gcc/config/loongarch/loongarch.cc\n+++ b/gcc/config/loongarch/loongarch.cc\n@@ -5108,8 +5108,37 @@ loongarch_split_vector_move (rtx dest, rtx src)\n machine_mode mode = GET_MODE (dest);\n bool lsx_p = LSX_SUPPORTED_MODE_P (mode);\n \n- if (FP_REG_RTX_P (dest))\n- {\n+ if (FP_REG_RTX_P (dest) && GP_REG_RTX_P (src))\n+ {\n+ /* Since the LoongArch architecture has not yet implemented vector\n+ parameter passing, the following operations are required when\n+ a function returns a vector type that needs to be passed to a\n+ vector register.\n+\n+ As shown in the following instruction sequence:\n+\n+ (call_insn 5 6 12 2 (parallel [\n+\t (set (reg:V2DI 4 $r4)\n+\t\t (call (mem:SI (symbol_ref:DI (\"bar\"))\n+\t\t\t\t(const_int 0 [0])))\n+\t\t (clobber (reg:SI 1 $r1)))]))\n+ (insn 12 5 7 2 (set (reg:V2DI 32 $f0)\n+\t\t\t (reg:V2DI 4 $r4)))\n+\n+ insn 12 will be split here as follows:\n+ (insn 15 5 16 2 (set (reg:V2DI 32 $f0)\n+\t\t\t (vec_merge:V2DI\n+\t\t\t\t(vec_duplicate:V2DI (reg:DI 4 $r4))\n+\t\t\t\t(reg:V2DI 32 $f0)\n+\t\t\t\t(const_int 1 [0x1]))))\n+ (insn 16 15 7 2 (set (reg:V2DI 32 $f0)\n+\t\t\t (vec_merge:V2DI\n+\t\t\t\t(vec_duplicate:V2DI (reg:DI 5 $r5 [+8 ]))\n+\t\t\t\t(reg:V2DI 32 $f0)\n+\t\t\t\t(const_int 2 [0x2]))))\n+\n+ This can be reproduced with the test case lsx-mov-2.c.\n+ */\n gcc_assert (!MEM_P (src));\n \n rtx (*gen_vinsgr2vr_d) (rtx, rtx, rtx, rtx);\n@@ -5138,8 +5167,12 @@ loongarch_split_vector_move (rtx dest, rtx src)\n \t\t\t\t\t GEN_INT (1 << index)));\n \t}\n }\n- else if (FP_REG_RTX_P (src))\n+ else if (FP_REG_RTX_P (src) && GP_REG_RTX_P (dest))\n {\n+ /* Transfer vector data from vector registers to GPRs, generally\n+\t for vector argument handling.\n+\t This can be reproduced with the test case lsx-mov-1.c.\n+ */\n gcc_assert (!MEM_P (dest));\n \n rtx (*gen_vpickve2gr_d) (rtx, rtx, rtx);\n@@ -5166,7 +5199,7 @@ loongarch_split_vector_move (rtx dest, rtx src)\n \t emit_insn (gen_vpickve2gr_d (d, new_src, GEN_INT (index)));\n \t}\n }\n- else\n+ else if (GP_REG_RTX_P (src) && GP_REG_RTX_P (dest))\n {\n /* This part of the code is designed to handle the following situations:\n \t (set (reg:V2DI 4 $r4)\ndiff --git a/gcc/config/loongarch/loongarch.h b/gcc/config/loongarch/loongarch.h\nindex b2a3def11ad..1059eee37ca 100644\n--- a/gcc/config/loongarch/loongarch.h\n+++ b/gcc/config/loongarch/loongarch.h\n@@ -368,8 +368,7 @@ along with GCC; see the file COPYING3. If not see\n ((unsigned int) ((int) (REGNO) - LASX_REG_FIRST) < LASX_REG_NUM)\n \n #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))\n-#define LSX_REG_RTX_P(X) (REG_P (X) && LSX_REG_P (REGNO (X)))\n-#define LASX_REG_RTX_P(X) (REG_P (X) && LASX_REG_P (REGNO (X)))\n+#define GP_REG_RTX_P(X) (REG_P (X) && GP_REG_P (REGNO (X)))\n \n /* Select a register mode required for caller save of hard regno REGNO. */\n #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \\\ndiff --git a/gcc/testsuite/gcc.target/loongarch/vector/lasx/pr125057.c b/gcc/testsuite/gcc.target/loongarch/vector/lasx/pr125057.c\nnew file mode 100644\nindex 00000000000..698bddd8d08\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/loongarch/vector/lasx/pr125057.c\n@@ -0,0 +1,25 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-mlasx -O2\" } */\n+\n+#include \n+#include \n+\n+#define TEST(to, from)\t\t\t\t\t\t\t\t\\\n+__m256i\t\t\t\t\t\t\t\t\t\t\\\n+vext2xv_##to##_##from (const short *p)\t\t\t\t\t\t\\\n+{\t\t\t\t\t\t\t\t\t\t\\\n+ return __lasx_vext2xv_##to##_##from (__lasx_cast_128 (__lsx_vld (p, 0)));\t\\\n+}\n+\n+TEST (h, b)\n+TEST (w, b)\n+TEST (d, b)\n+TEST (w, h)\n+TEST (d, h)\n+TEST (d, w)\n+TEST (hu, bu)\n+TEST (wu, bu)\n+TEST (du, bu)\n+TEST (wu, hu)\n+TEST (du, hu)\n+TEST (du, wu)\ndiff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-mov-2.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-mov-2.c\nnew file mode 100644\nindex 00000000000..9b3ac47fad6\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-mov-2.c\n@@ -0,0 +1,13 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-mlsx -O2\" } */\n+\n+#include \n+\n+extern __m128i bar (void);\n+extern int *p;\n+\n+void\n+foo ()\n+{\n+ __lsx_vst (bar(), (void *)p, 0);\n+}\n","prefixes":[]}