{"id":2230881,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230881/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430071315.354333-9-zhenzhong.duan@intel.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260430071315.354333-9-zhenzhong.duan@intel.com>","date":"2026-04-30T07:13:04","name":"[v4,08/15] intel_iommu: Use IOMMU_NO_PASID and delete PASID_0","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"4b5704db6a54b651fd4ab2227f857d15e6b069a5","submitter":{"id":81636,"url":"http://patchwork.ozlabs.org/api/1.1/people/81636/?format=json","name":"Duan, Zhenzhong","email":"zhenzhong.duan@intel.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430071315.354333-9-zhenzhong.duan@intel.com/mbox/","series":[{"id":502222,"url":"http://patchwork.ozlabs.org/api/1.1/series/502222/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502222","date":"2026-04-30T07:12:57","name":"intel_iommu: Enable PASID support for passthrough device","version":4,"mbox":"http://patchwork.ozlabs.org/series/502222/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230881/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230881/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=T/NlAFpL;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Thu, 30 Apr 2026 03:14:04 -0400","from orviesa007.jf.intel.com ([10.64.159.147])\n by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 30 Apr 2026 00:14:01 -0700","from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229])\n by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 30 Apr 2026 00:13:59 -0700"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1777533243; x=1809069243;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=QgQEKzeierZ7H50tnMUbHnRlrfJCILNdeLaWJtSesh0=;\n b=T/NlAFpLpWvNLHbDtT8nwQfovbNc8apLZ0OfQUq0xtbo8B9yWAhR8d0N\n /X4uLXylBmBlF4AfguuwvB7ZBRo/2rdlbjGg70ingsSuzAFCTvD6Nf3Bl\n uDWX0anYu84FxwrHSIMeOgCjZTVKqSj9anE05nsVlC5rzG3qZsiIprEWP\n kACvGsywD2B0A17CeeUSAeigVXMNQG8tQnTvXSkRYd1MoS0VtoAJBZVdb\n T8WTRjyCq8EdEnU+TE/j6WLD3Nv3530zRyMN98LEnvAjBvgmL2p/LEs1z\n krdd5O4ItihAT6hPJO5PacJJJSQmuNhNusXrC3TOTsaFrvtHQn6mP6Mv/ w==;","X-CSE-ConnectionGUID":["7kOLKJYBR2G+Erwz2JetEg==","0dC+3/8hRyGaBClBp/nIzw=="],"X-CSE-MsgGUID":["fWdTL0DsTiW6dI+Im/4Vfw==","JzGx2nQcQNyLR1bGp8GE4w=="],"X-IronPort-AV":["E=McAfee;i=\"6800,10657,11771\"; a=\"81051629\"","E=Sophos;i=\"6.23,207,1770624000\"; d=\"scan'208\";a=\"81051629\"","E=Sophos;i=\"6.23,207,1770624000\"; d=\"scan'208\";a=\"234771533\""],"X-ExtLoop1":"1","From":"Zhenzhong Duan ","To":"qemu-devel@nongnu.org","Cc":"alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com,\n jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,\n skolothumtho@nvidia.com, joao.m.martins@oracle.com,\n clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com,\n xudong.hao@intel.com, Zhenzhong Duan ","Subject":"[PATCH v4 08/15] intel_iommu: Use IOMMU_NO_PASID and delete PASID_0","Date":"Thu, 30 Apr 2026 03:13:04 -0400","Message-ID":"<20260430071315.354333-9-zhenzhong.duan@intel.com>","X-Mailer":"git-send-email 2.47.3","In-Reply-To":"<20260430071315.354333-1-zhenzhong.duan@intel.com>","References":"<20260430071315.354333-1-zhenzhong.duan@intel.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=192.198.163.13;\n envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com","X-Spam_score_int":"-43","X-Spam_score":"-4.4","X-Spam_bar":"----","X-Spam_report":"(-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"In previous patch we introduced a global macro IOMMU_NO_PASID(0) for\nRequests-without-PASID, this makes the local macro PASID_0 redundant.\nDelete it and use IOMMU_NO_PASID instead.\n\nSuggested-by: Yi Liu \nSigned-off-by: Zhenzhong Duan \nTested-by: Xudong Hao \n---\n hw/i386/intel_iommu_internal.h | 1 -\n hw/i386/intel_iommu.c | 21 +++++++++++----------\n hw/i386/intel_iommu_accel.c | 2 +-\n 3 files changed, 12 insertions(+), 12 deletions(-)","diff":"diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h\nindex c7e107fe87..0141316f83 100644\n--- a/hw/i386/intel_iommu_internal.h\n+++ b/hw/i386/intel_iommu_internal.h\n@@ -615,7 +615,6 @@ typedef struct VTDRootEntry VTDRootEntry;\n #define VTD_CTX_ENTRY_LEGACY_SIZE 16\n #define VTD_CTX_ENTRY_SCALABLE_SIZE 32\n \n-#define PASID_0 0\n #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(aw) (0x1e0ULL | ~VTD_HAW_MASK(aw))\n #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL\n #define VTD_SM_CONTEXT_ENTRY_PRE 0x10ULL\ndiff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c\nindex 74642d8123..4d1b262d56 100644\n--- a/hw/i386/intel_iommu.c\n+++ b/hw/i386/intel_iommu.c\n@@ -100,7 +100,8 @@ static void vtd_pasid_cache_reset_locked(IntelIOMMUState *s)\n *\n * Requests-without-PASID:\n * - PCI subsystem: Uses PCI_NO_PASID (-1) to indicate no PASID present\n- * - VT-d IOMMU: Uses PASID_0 (0) to index the PASID table for translation\n+ * - VT-d IOMMU: Uses IOMMU_NO_PASID (0) to index the PASID table for\n+ * translation\n *\n * Requests-with-PASID:\n * - Both subsystems use identical PASID values (1-0xFFFFF)\n@@ -114,7 +115,7 @@ static void vtd_pasid_cache_reset_locked(IntelIOMMUState *s)\n */\n static uint32_t vtd_pasid_to_pci_pasid(uint32_t pasid)\n {\n- if (pasid == PASID_0) {\n+ if (pasid == IOMMU_NO_PASID) {\n pasid = PCI_NO_PASID;\n }\n return pasid;\n@@ -969,7 +970,7 @@ int vtd_ce_get_pasid_entry(IntelIOMMUState *s, VTDContextEntry *ce,\n dma_addr_t pasid_dir_base;\n \n if (pasid == PCI_NO_PASID) {\n- pasid = PASID_0;\n+ pasid = IOMMU_NO_PASID;\n }\n pasid_dir_base = VTD_CE_GET_PASID_DIR_TABLE(ce);\n return vtd_get_pe_from_pasid_table(s, pasid_dir_base, pasid, pe);\n@@ -986,7 +987,7 @@ static int vtd_ce_get_pasid_fpd(IntelIOMMUState *s,\n VTDPASIDEntry pe;\n \n if (pasid == PCI_NO_PASID) {\n- pasid = PASID_0;\n+ pasid = IOMMU_NO_PASID;\n }\n pasid_dir_base = VTD_CE_GET_PASID_DIR_TABLE(ce);\n \n@@ -1529,9 +1530,9 @@ static int vtd_ce_pasid_0_check(IntelIOMMUState *s, VTDContextEntry *ce)\n \n /*\n * Make sure in Scalable Mode, a present context entry\n- * has valid pasid entry setting at PASID_0.\n+ * has valid pasid entry setting at IOMMU_NO_PASID.\n */\n- return vtd_ce_get_pasid_entry(s, ce, &pe, PASID_0);\n+ return vtd_ce_get_pasid_entry(s, ce, &pe, IOMMU_NO_PASID);\n }\n \n /* Map a device to its corresponding domain (context-entry) */\n@@ -1592,7 +1593,7 @@ int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,\n }\n } else {\n /*\n- * Check if the programming of pasid setting of PASID_0\n+ * Check if the programming of pasid setting of IOMMU_NO_PASID\n * is valid, and thus avoids to check pasid entry fetching\n * result in future helper function calling.\n */\n@@ -2150,7 +2151,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,\n vtd_iommu_lock(s);\n \n if (pasid == PCI_NO_PASID && s->root_scalable) {\n- pasid = PASID_0;\n+ pasid = IOMMU_NO_PASID;\n }\n \n /* Try to fetch pte from IOTLB */\n@@ -2515,7 +2516,7 @@ static void vtd_iotlb_domain_invalidate(IntelIOMMUState *s, uint16_t domain_id)\n }\n \n /*\n- * There is no pasid field in iotlb invalidation descriptor, so PASID_0\n+ * There is no pasid field in iotlb invalidation descriptor, so IOMMU_NO_PASID\n * is passed as parameter. Piotlb invalidation supports pasid, pasid in its\n * descriptor is passed. In both cases, pasid is converted to PCI pasid\n * before checking with vtd_as->pasid.\n@@ -2586,7 +2587,7 @@ static void vtd_iotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id,\n vtd_iommu_lock(s);\n g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_page, &info);\n vtd_iommu_unlock(s);\n- vtd_iotlb_page_invalidate_notify(s, domain_id, addr, am, PASID_0);\n+ vtd_iotlb_page_invalidate_notify(s, domain_id, addr, am, IOMMU_NO_PASID);\n }\n \n /* Flush IOTLB\ndiff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c\nindex bd1236c070..8940d240a1 100644\n--- a/hw/i386/intel_iommu_accel.c\n+++ b/hw/i386/intel_iommu_accel.c\n@@ -217,7 +217,7 @@ static void vtd_flush_host_piotlb_locked(gpointer key, gpointer value,\n \n did = VTD_SM_PASID_ENTRY_DID(&pc_entry->pasid_entry);\n \n- if (piotlb_info->domain_id == did && piotlb_info->pasid == PASID_0) {\n+ if (piotlb_info->domain_id == did && piotlb_info->pasid == IOMMU_NO_PASID) {\n HostIOMMUDeviceIOMMUFD *hiodi =\n HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->hiod);\n uint32_t entry_num = 1; /* Only implement one request for simplicity */\n","prefixes":["v4","08/15"]}