{"id":2230863,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230863/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260430-sm6350-lpi-tlmm-v2-1-81d068025b97@fairphone.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/1.1/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260430-sm6350-lpi-tlmm-v2-1-81d068025b97@fairphone.com>","date":"2026-04-30T07:10:41","name":"[v2,1/5] dt-bindings: pinctrl: qcom: Add SM6350 LPI pinctrl","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"b2a535970b0bd7e9163482353667126664b92a43","submitter":{"id":83060,"url":"http://patchwork.ozlabs.org/api/1.1/people/83060/?format=json","name":"Luca Weiss","email":"luca.weiss@fairphone.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/patch/20260430-sm6350-lpi-tlmm-v2-1-81d068025b97@fairphone.com/mbox/","series":[{"id":502221,"url":"http://patchwork.ozlabs.org/api/1.1/series/502221/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=502221","date":"2026-04-30T07:10:40","name":"Add LPASS LPI pin controller support for SM6350","version":2,"mbox":"http://patchwork.ozlabs.org/series/502221/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230863/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230863/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=fairphone.com header.i=@fairphone.com\n header.a=rsa-sha256 header.s=fair header.b=TxFoCeyO;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260430-sm6350-lpi-tlmm-v2-1-81d068025b97@fairphone.com>","References":"<20260430-sm6350-lpi-tlmm-v2-0-81d068025b97@fairphone.com>","In-Reply-To":"<20260430-sm6350-lpi-tlmm-v2-0-81d068025b97@fairphone.com>","To":"Bjorn Andersson ,\n Linus Walleij , Rob Herring ,\n Krzysztof Kozlowski ,\n Conor Dooley , Konrad Dybcio ,\n Srinivas Kandagatla ","Cc":"~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org,\n linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n Luca Weiss ","X-Mailer":"b4 0.15.2","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1777533047; l=4264;\n i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id;\n bh=++Zm2pL/MChTSAhZsB+/yIpS7A5i7sldIEDzeeK5d+0=;\n b=wCxpg9VKhtvBlcsVwO+rhrpLgpZq7Tffn+P+K4ExFHjmHauGEt94udWS7U9SIxL/oWz1gsCD8\n YAwzsMMudU1C45c+O5zWc0Fk9EldsqOPdJRynW98+F78rtn2U4FyM8S","X-Developer-Key":"i=luca.weiss@fairphone.com; a=ed25519;\n pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8="},"content":"Add bindings for pin controller in Low Power Audio SubSystem (LPASS).\n\nSigned-off-by: Luca Weiss \n---\n .../pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml | 124 +++++++++++++++++++++\n 1 file changed, 124 insertions(+)","diff":"diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml\nnew file mode 100644\nindex 000000000000..4903b2d37d89\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml\n@@ -0,0 +1,124 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Qualcomm SM6350 SoC LPASS LPI TLMM\n+\n+maintainers:\n+ - Luca Weiss \n+\n+description:\n+ Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem\n+ (LPASS) Low Power Island (LPI) of Qualcomm SM6350 SoC.\n+\n+properties:\n+ compatible:\n+ const: qcom,sm6350-lpass-lpi-pinctrl\n+\n+ reg:\n+ items:\n+ - description: LPASS LPI TLMM Control and Status registers\n+ - description: LPASS LPI MCC registers\n+\n+ clocks:\n+ items:\n+ - description: LPASS Core voting clock\n+ - description: LPASS Audio voting clock\n+\n+ clock-names:\n+ items:\n+ - const: core\n+ - const: audio\n+\n+patternProperties:\n+ \"-state$\":\n+ oneOf:\n+ - $ref: \"#/$defs/qcom-sm6350-lpass-state\"\n+ - patternProperties:\n+ \"-pins$\":\n+ $ref: \"#/$defs/qcom-sm6350-lpass-state\"\n+ additionalProperties: false\n+\n+$defs:\n+ qcom-sm6350-lpass-state:\n+ type: object\n+ description:\n+ Pinctrl node's client devices use subnodes for desired pin configuration.\n+ Client device subnodes use below standard properties.\n+ $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state\n+ unevaluatedProperties: false\n+\n+ properties:\n+ pins:\n+ description:\n+ List of gpio pins affected by the properties specified in this\n+ subnode.\n+ items:\n+ pattern: \"^gpio([0-9]|1[0-4])$\"\n+\n+ function:\n+ enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk,\n+ dmic3_data, gpio, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk,\n+ i2s2_data, i2s2_ws, qua_mi2s_data, qua_mi2s_sclk, qua_mi2s_ws,\n+ swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_data, wsa_swr_clk,\n+ wsa_swr_data ]\n+ description:\n+ Specify the alternative function to be configured for the specified\n+ pins.\n+\n+allOf:\n+ - $ref: qcom,lpass-lpi-common.yaml#\n+\n+required:\n+ - compatible\n+ - reg\n+ - clocks\n+ - clock-names\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ #include \n+\n+ lpass_tlmm: pinctrl@33c0000 {\n+ compatible = \"qcom,sm6350-lpass-lpi-pinctrl\";\n+ reg = <0x033c0000 0x20000>,\n+ <0x03550000 0x10000>;\n+ gpio-controller;\n+ #gpio-cells = <2>;\n+ gpio-ranges = <&lpass_tlmm 0 0 15>;\n+\n+ clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,\n+ <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;\n+ clock-names = \"core\",\n+ \"audio\";\n+\n+ i2s1_active: i2s1-active-state {\n+ clk-pins {\n+ pins = \"gpio6\";\n+ function = \"i2s1_clk\";\n+ drive-strength = <8>;\n+ bias-disable;\n+ output-high;\n+ };\n+\n+ ws-pins {\n+ pins = \"gpio7\";\n+ function = \"i2s1_ws\";\n+ drive-strength = <8>;\n+ bias-disable;\n+ output-high;\n+ };\n+\n+ data-pins {\n+ pins = \"gpio8\", \"gpio9\";\n+ function = \"i2s1_data\";\n+ drive-strength = <8>;\n+ bias-disable;\n+ output-high;\n+ };\n+ };\n+ };\n","prefixes":["v2","1/5"]}