{"id":2230852,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230852/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/afL5YJsapiuhNZ3A@cowardly-lion.the-meissners.org/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/1.1/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"","date":"2026-04-30T06:40:32","name":"GCC 17, PowerPC Dense Math V7 (patch 2/7) -- Use wD in mma.md","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"4f473172c30fcc8b6a130ed24d89e4ef345ef6da","submitter":{"id":73991,"url":"http://patchwork.ozlabs.org/api/1.1/people/73991/?format=json","name":"Michael Meissner","email":"meissner@linux.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/afL5YJsapiuhNZ3A@cowardly-lion.the-meissners.org/mbox/","series":[{"id":502213,"url":"http://patchwork.ozlabs.org/api/1.1/series/502213/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=502213","date":"2026-04-30T06:40:32","name":"GCC 17, PowerPC Dense Math V7 (patch 2/7) -- Use wD in mma.md","version":1,"mbox":"http://patchwork.ozlabs.org/series/502213/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230852/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230852/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=iIZ/85O3;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"","X-TM-AS-GCONF":"00","X-Proofpoint-ORIG-GUID":"ceyChDt_UafxmrZ_vO-WAGO6UhgGXUmU","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDMwMDA2MCBTYWx0ZWRfX6sCJx91KywWw\n 3ewICh/KotWDuQ586H3KS6sAU2l+yu8ApCOluV9XoygObFvXu+oxHKNbQXSwgQ74obRwYJad+oM\n pwuUvWQde5BIELP9bnFY6qMJfc5Mn7Nn5RIyHcaroGjDwNsAbUDdMa1Ufe909jQsiC54nCXitsZ\n QTsn7GOiddffJgw6/X07x3XChPinB40FzJW3WKnEtPS1vJJrfURRBZ6suWfj92IuDWmORkehy1V\n 0fGEzfQKQUTCUPJ1XFfBDSgvSslhyTjfOjZPeu2l7i0l7UC22wYON/UKEN+KSNwcSclkqiOkuKW\n KQbAcRe+DTJQB5owaJLwwqI0uBESDJh/LQgeGKae21V9XnHifLBUuEA8rkAMa2CUG7/PBpCn3c0\n uzXR3+GnSDf7CfA277EWXzpqUS1S8WERYTjKNcBZEU76o49fUHBtV916RlxMaqVGUqEZgN6kJ7r\n nbnvkQLIECqBcVgPd/w==","X-Authority-Analysis":"v=2.4 cv=VZLH+lp9 c=1 sm=1 tr=0 ts=69f2f966 cx=c_pps\n a=GFwsV6G8L6GxiO2Y/PsHdQ==:117 a=GFwsV6G8L6GxiO2Y/PsHdQ==:17\n a=kj9zAlcOel0A:10 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=RnoormkPH1_aCDwRdu11:22 a=V8glGbnc2Ofi9Qvn3v5h:22 a=mDV3o1hIAAAA:8\n a=VnNF1IyMAAAA:8 a=4FFjvpyAOt5rtwv9xHkA:9 a=3ZKOabzyN94A:10 a=CjuIK1q_8ugA:10","X-Proofpoint-GUID":"ceyChDt_UafxmrZ_vO-WAGO6UhgGXUmU","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-30_02,2026-04-28_01,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n clxscore=1015 suspectscore=0 adultscore=0 lowpriorityscore=0 phishscore=0\n spamscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 impostorscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604300060","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"This is part two of the dense math register patches for the PowerPC.\nThis is the 7th version of the dense math patches.\n\nVersion 6 of the dense math register patches were posted on April 21st,\n2026.\n\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-April/713352.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-April/713353.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-April/713354.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-April/713355.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-April/713356.html\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-April/713357.html\n\nThis patch needs the -mcpu=future patch posted on April 8th, 2026:\n\n * https://gcc.gnu.org/pipermail/gcc-patches/2026-April/712532.html\n\nThis patch changes mma.md to use the wD constraint and accumulator_operand\npredicate that were added in the previous patch instead of using the d constrant\nand vsx_register_operand predicate. This is in anticipation of adding dense\nmath registers in a future patch.\n\nIn addition, I added a comment in front of each insn to indicate which\ninstructions are being generated.\n\nOriginaly, these changes were in patch #4 in the V6 patches. I have removed\nthese patches switching to use wD from the other part of the patch adding dense\nmath register support.\n\nI have built bootstrap little endian compilers on power10 systems, and\nbig endian compiler on power9 systems. There were no regression in the\ntests. Can I add the patches to the GCC trunk after the -mcpu=future\npatch is applied and GCC 17 has opened up?\n\n2026-04-29 Michael Meissner \n\ngcc/\n\n\t* config/rs6000/mma.md (mma_): Use the wD constraint and\n\taccumulator_operand predicate for all MMA instructions taking\n\taccumulator operands.\n\t(mma_): Likewise.\n\t(mma_\"): Likewise.\n\t(mma_): Likewise.\n\t(mma_): Likewise.\n\t(mma_): Likewise.\n\t(mma_\"): Likewise.\n\t(mma_): Likewise.\n\t(mma_): Likewise.\n\t(mma_): Likewise.\n\t(mma_): Likewise.\n\t(mma_): Likewise.\n\t(mma_): Likewise.\n\t(mma_): Likewise.\n---\n gcc/config/rs6000/mma.md | 83 ++++++++++++++++++++++++++++++----------\n 1 file changed, 62 insertions(+), 21 deletions(-)","diff":"diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md\nindex 1103f1fc037..87139dd41e8 100644\n--- a/gcc/config/rs6000/mma.md\n+++ b/gcc/config/rs6000/mma.md\n@@ -522,8 +522,15 @@ (define_insn \"mma_xxsetaccz\"\n \"xxsetaccz %A0\"\n [(set_attr \"type\" \"mma\")])\n \n+\f\n+;; MMA operations below.\n+\n+;; Instructions:\n+;; xvi4ger8 xvi8ger4 xvi16ger2 xvi16ger2s xvf16ger2\n+;; xvbf16ger2 xvf32ger\n+\n (define_insn \"mma_\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d,&d\")\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n \t(unspec:XO [(match_operand:V16QI 1 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")]\n \t\t MMA_VV))]\n@@ -531,9 +538,15 @@ (define_insn \"mma_\"\n \" %A0,%x1,%x2\"\n [(set_attr \"type\" \"mma\")])\n \n+;; Instructions:\n+;; xvi4ger8pp xvi8ger4pp xvi8ger4spp xvi16ger2pp xvi16ger2spp\n+;; xvf16ger2pp xvf16ger2pn xvf16ger2np xvf16ger2nn xvbf16ger2pp\n+;; xvbf16ger2pn xvbf16ger2np xvbf16ger2nn xvf32gerpp xvf32gerpn\n+;; xvf32gernp xvf32gernn\n+\n (define_insn \"mma_\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d,&d\")\n-\t(unspec:XO [(match_operand:XO 1 \"fpr_reg_operand\" \"0,0\")\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n+\t(unspec:XO [(match_operand:XO 1 \"accumulator_operand\" \"0,0\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 3 \"vsx_register_operand\" \"v,?wa\")]\n \t\t MMA_AVV))]\n@@ -541,8 +554,10 @@ (define_insn \"mma_\"\n \" %A0,%x2,%x3\"\n [(set_attr \"type\" \"mma\")])\n \n+;; Instruction: xvf64ger\n+\n (define_insn \"mma_\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d,&d\")\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n \t(unspec:XO [(match_operand:OO 1 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")]\n \t\t MMA_PV))]\n@@ -550,9 +565,11 @@ (define_insn \"mma_\"\n \" %A0,%x1,%x2\"\n [(set_attr \"type\" \"mma\")])\n \n+;; Instructions: xvf64gerpp xvf64gerpn xvf64gernp xvf64gernn\n+\n (define_insn \"mma_\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d,&d\")\n-\t(unspec:XO [(match_operand:XO 1 \"fpr_reg_operand\" \"0,0\")\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n+\t(unspec:XO [(match_operand:XO 1 \"accumulator_operand\" \"0,0\")\n \t\t (match_operand:OO 2 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 3 \"vsx_register_operand\" \"v,?wa\")]\n \t\t MMA_APV))]\n@@ -560,8 +577,10 @@ (define_insn \"mma_\"\n \" %A0,%x2,%x3\"\n [(set_attr \"type\" \"mma\")])\n \n+;; Instruction: pmxvi4ger8\n+\n (define_insn \"mma_\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d,&d\")\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n \t(unspec:XO [(match_operand:V16QI 1 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:SI 3 \"const_0_to_15_operand\" \"n,n\")\n@@ -573,9 +592,11 @@ (define_insn \"mma_\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n \n+;; Instruction: pmxvi4ger8pp\n+\n (define_insn \"mma_\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d,&d\")\n-\t(unspec:XO [(match_operand:XO 1 \"fpr_reg_operand\" \"0,0\")\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n+\t(unspec:XO [(match_operand:XO 1 \"accumulator_operand\" \"0,0\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 3 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:SI 4 \"const_0_to_15_operand\" \"n,n\")\n@@ -587,8 +608,11 @@ (define_insn \"mma_\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n \n+;; Instructions:\n+;; pmxvi16ger2 pmxvi16ger2s pmxvf16ger2 pmxvbf16ger2\n+\n (define_insn \"mma_\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d,&d\")\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n \t(unspec:XO [(match_operand:V16QI 1 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:SI 3 \"const_0_to_15_operand\" \"n,n\")\n@@ -600,9 +624,14 @@ (define_insn \"mma_\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n \n+;; Instructions:\n+;; pmxvi16ger2pp pmxvi16ger2spp pmxvf16ger2pp pmxvf16ger2pn\n+;; pmxvf16ger2np pmxvf16ger2nn pmxvbf16ger2pp pmxvbf16ger2pn\n+;; pmxvbf16ger2np pmxvbf16ger2nn\n+\n (define_insn \"mma_\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d,&d\")\n-\t(unspec:XO [(match_operand:XO 1 \"fpr_reg_operand\" \"0,0\")\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n+\t(unspec:XO [(match_operand:XO 1 \"accumulator_operand\" \"0,0\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 3 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:SI 4 \"const_0_to_15_operand\" \"n,n\")\n@@ -614,8 +643,10 @@ (define_insn \"mma_\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n \n+;; Instruction: pmxvf32ger\n+\n (define_insn \"mma_\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d,&d\")\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n \t(unspec:XO [(match_operand:V16QI 1 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:SI 3 \"const_0_to_15_operand\" \"n,n\")\n@@ -626,9 +657,11 @@ (define_insn \"mma_\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n \n+;; Instructions: pmxvf32gerpp pmxvf32gerpn pmxvf32gernp pmxvf32gernn\n+\n (define_insn \"mma_\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d,&d\")\n-\t(unspec:XO [(match_operand:XO 1 \"fpr_reg_operand\" \"0,0\")\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n+\t(unspec:XO [(match_operand:XO 1 \"accumulator_operand\" \"0,0\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 3 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:SI 4 \"const_0_to_15_operand\" \"n,n\")\n@@ -639,8 +672,10 @@ (define_insn \"mma_\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n \n+;; Instruction: pmxvf64ger\n+\n (define_insn \"mma_\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d,&d\")\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n \t(unspec:XO [(match_operand:OO 1 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:SI 3 \"const_0_to_15_operand\" \"n,n\")\n@@ -651,9 +686,11 @@ (define_insn \"mma_\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n \n+;; Instructions: pmxvf64gerpp pmxvf64gerpn pmxvf64gernp pmxvf64gernn\n+\n (define_insn \"mma_\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d,&d\")\n-\t(unspec:XO [(match_operand:XO 1 \"fpr_reg_operand\" \"0,0\")\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n+\t(unspec:XO [(match_operand:XO 1 \"accumulator_operand\" \"0,0\")\n \t\t (match_operand:OO 2 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 3 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:SI 4 \"const_0_to_15_operand\" \"n,n\")\n@@ -664,8 +701,10 @@ (define_insn \"mma_\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n \n+;; Instruction: pmxvi8ger4\n+\n (define_insn \"mma_\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d,&d\")\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n \t(unspec:XO [(match_operand:V16QI 1 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:SI 3 \"const_0_to_15_operand\" \"n,n\")\n@@ -677,9 +716,11 @@ (define_insn \"mma_\"\n [(set_attr \"type\" \"mma\")\n (set_attr \"prefixed\" \"yes\")])\n \n+;; Instructions: pmxvi8ger4pp pmxvi8ger4spp\n+\n (define_insn \"mma_\"\n- [(set (match_operand:XO 0 \"fpr_reg_operand\" \"=&d,&d\")\n-\t(unspec:XO [(match_operand:XO 1 \"fpr_reg_operand\" \"0,0\")\n+ [(set (match_operand:XO 0 \"accumulator_operand\" \"=&wD,&wD\")\n+\t(unspec:XO [(match_operand:XO 1 \"accumulator_operand\" \"0,0\")\n \t\t (match_operand:V16QI 2 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:V16QI 3 \"vsx_register_operand\" \"v,?wa\")\n \t\t (match_operand:SI 4 \"const_0_to_15_operand\" \"n,n\")\n","prefixes":[]}