{"id":2230760,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230760/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-45-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260430002046.59739-45-richard.henderson@linaro.org>","date":"2026-04-30T00:20:43","name":"[v3,44/47] target/arm: Implement FMLALB, FMLALT (FP8 to FP16) for SVE","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"60332435fbdd3bfd4ad5d861b9198d9009d13b61","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.1/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-45-richard.henderson@linaro.org/mbox/","series":[{"id":502175,"url":"http://patchwork.ozlabs.org/api/1.1/series/502175/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502175","date":"2026-04-30T00:20:06","name":"target/arm: Implement FEAT_FP8","version":3,"mbox":"http://patchwork.ozlabs.org/series/502175/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230760/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230760/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=kXSa6HVh;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5Zkx5NWgz1yHv\n\tfor ; Thu, 30 Apr 2026 10:27:53 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wIFE1-00074U-4v; Wed, 29 Apr 2026 20:25:53 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wIFDm-0006UC-84\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:25:39 -0400","from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wIFDi-0007V7-A0\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:25:35 -0400","by mail-pf1-x42f.google.com with SMTP id\n d2e1a72fcca58-82fb2d0c5d1so992915b3a.0\n for ; Wed, 29 Apr 2026 17:25:32 -0700 (PDT)","from stoup.. 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helo=mail-pf1-x42f.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Richard Henderson \n---\n target/arm/cpu-features.h | 5 +++++\n target/arm/tcg/translate-sve.c | 33 +++++++++++++++++++++++++++++++++\n target/arm/tcg/sve.decode | 7 +++++++\n 3 files changed, 45 insertions(+)","diff":"diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex db31ac6b6b..1cefb21b0e 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1531,6 +1531,11 @@ static inline bool isar_feature_aa64_sve_b16b16(const ARMISARegisters *id)\n return FIELD_EX64_IDREG(id, ID_AA64ZFR0, B16B16);\n }\n \n+static inline bool isar_feature_aa64_ssve_f8fma(const ARMISARegisters *id)\n+{\n+ return FIELD_EX64_IDREG(id, ID_AA64SMFR0, SF8FMA);\n+}\n+\n static inline bool isar_feature_aa64_sme_b16b16(const ARMISARegisters *id)\n {\n return FIELD_EX64_IDREG(id, ID_AA64SMFR0, B16B16);\ndiff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c\nindex ea0d66178e..aa785fa0c3 100644\n--- a/target/arm/tcg/translate-sve.c\n+++ b/target/arm/tcg/translate-sve.c\n@@ -8336,3 +8336,36 @@ static bool trans_LUTI4_2h(DisasContext *s, arg_LUTI4_2h *a)\n }\n return true;\n }\n+\n+static bool do_fmla_fp8(DisasContext *s, arg_rxx *a, gen_helper_gvec_3_ptr *fn)\n+{\n+ bool fp8fma = dc_isar_feature(aa64_f8fma, s);\n+ bool ssve_fp8fma = dc_isar_feature(aa64_ssve_f8fma, s);\n+ bool ok = false;\n+\n+ /* Feature detection and enabling are complex here. */\n+ if (!(ssve_fp8fma || (fp8fma && dc_isar_feature(aa64_sve2, s)))) {\n+ return false;\n+ }\n+ if (fpmr_access_check(s)) {\n+ if (fp8fma) {\n+ s->is_nonstreaming = !ssve_fp8fma;\n+ ok = sve_access_check(s);\n+ } else {\n+ ok = sme_sm_enabled_check(s);\n+ }\n+ }\n+\n+ if (ok) {\n+ unsigned vsz = vec_full_reg_size(s);\n+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),\n+ vec_full_reg_offset(s, a->rn),\n+ vec_full_reg_offset(s, a->rm),\n+ tcg_env, vsz, vsz,\n+ a->idxn | (a->idxm << 2), fn);\n+ }\n+ return true;\n+}\n+\n+TRANS(FMLAL_hb, do_fmla_fp8, a, gen_helper_gvec_fmla_hb)\n+TRANS(FMLAL_idx_hb, do_fmla_fp8, a, gen_helper_gvec_fmla_idx_hb)\ndiff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode\nindex a11ea08eb3..e6c8e8fec3 100644\n--- a/target/arm/tcg/sve.decode\n+++ b/target/arm/tcg/sve.decode\n@@ -29,6 +29,7 @@\n %imm9_16_10 16:s6 10:3\n %size_23 23:2\n %dtype_23_13 23:2 13:2\n+%index4_19_10 19:2 10:2\n %index3_22_19 22:1 19:2\n %index3_22_17 22:1 17:2\n %index3_22_12 22:2 12:1\n@@ -73,6 +74,7 @@\n &rri rd rn imm\n &rr_dbm rd rn dbm\n &rrri rd rn rm imm\n+&rxx rd rn rm idxn idxm\n &rri_esz rd rn imm esz\n &rrri_esz rd rn rm imm esz\n &rrr_esz rd rn rm esz\n@@ -1864,6 +1866,8 @@ BFMLALT_zzzw 01100100 11 1 ..... 10 0 00 1 ..... ..... @rda_rn_rm_ex esz=2\n BFMLSLB_zzzw 01100100 11 1 ..... 10 1 00 0 ..... ..... @rda_rn_rm_ex esz=2\n BFMLSLT_zzzw 01100100 11 1 ..... 10 1 00 1 ..... ..... @rda_rn_rm_ex esz=2\n \n+FMLAL_hb 01100100 10 1 rm:5 100 idxn:1 10 rn:5 rd:5 &rxx idxm=0\n+\n ### SVE2 floating-point dot-product\n FDOT_zzzz 01100100 00 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2\n BFDOT_zzzz 01100100 01 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_ex esz=2\n@@ -1880,6 +1884,9 @@ BFMLALT_zzxw 01100100 11 1 ..... 0100.1 ..... ..... @rrxr_3a esz=2\n BFMLSLB_zzxw 01100100 11 1 ..... 0110.0 ..... ..... @rrxr_3a esz=2\n BFMLSLT_zzxw 01100100 11 1 ..... 0110.1 ..... ..... @rrxr_3a esz=2\n \n+FMLAL_idx_hb 01100100 idxn:1 01 .. rm:3 0101 .. rn:5 rd:5 \\\n+ &rxx idxm=%index4_19_10\n+\n ### SVE2 floating-point dot-product (indexed)\n \n FDOT_zzxz 01100100 00 1 ..... 010000 ..... ..... @rrxr_2 esz=2\n","prefixes":["v3","44/47"]}