{"id":2230759,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230759/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-44-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260430002046.59739-44-richard.henderson@linaro.org>","date":"2026-04-30T00:20:42","name":"[v3,43/47] target/arm: Implement FMLALB, FMLALT for AdvSIMD","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"428517c6a2545d8b41c6642ea4caa7f9365bfd8d","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.1/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-44-richard.henderson@linaro.org/mbox/","series":[{"id":502175,"url":"http://patchwork.ozlabs.org/api/1.1/series/502175/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502175","date":"2026-04-30T00:20:06","name":"target/arm: Implement FEAT_FP8","version":3,"mbox":"http://patchwork.ozlabs.org/series/502175/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230759/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230759/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=tfJ9SpDL;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5ZkX3Sgmz1yHv\n\tfor ; Thu, 30 Apr 2026 10:27:32 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wIFE3-0007S3-Gt; Wed, 29 Apr 2026 20:25:55 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wIFDm-0006UI-AO\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:25:40 -0400","from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wIFDg-0007UZ-Gc\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:25:35 -0400","by mail-pg1-x530.google.com with SMTP id\n 41be03b00d2f7-c70f91776fcso111892a12.0\n for ; Wed, 29 Apr 2026 17:25:30 -0700 (PDT)","from stoup.. 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helo=mail-pg1-x530.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Richard Henderson \n---\n target/arm/cpu-features.h | 5 ++\n target/arm/tcg/helper-fp8-defs.h | 3 +\n target/arm/tcg/fp8_helper.c | 105 +++++++++++++++++++++++++++++++\n target/arm/tcg/translate-a64.c | 16 +++++\n target/arm/tcg/a64.decode | 8 +++\n 5 files changed, 137 insertions(+)","diff":"diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex 535c1e4792..db31ac6b6b 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1576,6 +1576,11 @@ static inline bool isar_feature_aa64_f8cvt(const ARMISARegisters *id)\n return FIELD_EX64_IDREG(id, ID_AA64FPFR0, F8CVT);\n }\n \n+static inline bool isar_feature_aa64_f8fma(const ARMISARegisters *id)\n+{\n+ return FIELD_EX64_IDREG(id, ID_AA64FPFR0, F8FMA);\n+}\n+\n /*\n * Combinations of feature tests, for ease of use with TRANS_FEAT.\n */\ndiff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-defs.h\nindex 36ae977431..7aa8366d94 100644\n--- a/target/arm/tcg/helper-fp8-defs.h\n+++ b/target/arm/tcg/helper-fp8-defs.h\n@@ -23,3 +23,6 @@ DEF_HELPER_FLAGS_4(sve2_fcvtnb_bs, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sve2_fcvtnt_bs, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sme2_fcvt_bs, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sme2_fcvtn_bs, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n+\n+DEF_HELPER_FLAGS_5(gvec_fmla_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\n+DEF_HELPER_FLAGS_5(gvec_fmla_idx_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\ndiff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c\nindex f0f03298d1..4825316b3b 100644\n--- a/target/arm/tcg/fp8_helper.c\n+++ b/target/arm/tcg/fp8_helper.c\n@@ -848,3 +848,108 @@ void HELPER(sme2_fcvtn_bs)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n \n fp8_finish(env, &ctx);\n }\n+\n+static FloatParts64 unpack_fp8(uint8_t x, FPMRType type, float_status *s)\n+{\n+ switch (type) {\n+ case OFP8_E5M2:\n+ return float8_e5m2_unpack_canonical(x, s);\n+ case OFP8_E4M3:\n+ return float8_e4m3_unpack_canonical(x, s);\n+ default:\n+ return parts64_default_nan(s);\n+ }\n+}\n+\n+static void f8muladd(FloatParts64 *a, const FloatParts64 *b,\n+ const FloatParts64 *c, int scale, float_status *s)\n+{\n+ /*\n+ * Because of default_nan_mode, NaNs need no special handling.\n+ * We'll simply get the default NaN out at the end of the sequence.\n+ */\n+ *a = parts64_mul(a, b, s);\n+ *a = parts64_scalbn(a, scale, s);\n+ *a = parts64_addsub(a, c, s, false);\n+}\n+\n+void HELPER(gvec_fmla_hb)(void *vd, void *vn, void *vm,\n+ CPUARMState *env, uint32_t desc)\n+{\n+ float_status stat = env->vfp.fp_status[FPST_A64];\n+ bool high = extract32(desc, SIMD_DATA_SHIFT, 1);\n+ size_t oprsz = simd_oprsz(desc);\n+ size_t nelem = oprsz / 2;\n+ uint8_t *n = vn;\n+ uint8_t *m = vm;\n+ float16 *d = vd;\n+\n+ uint64_t fpmr = env->vfp.fpmr;\n+ FPMRType fmt_n = FIELD_EX64(fpmr, FPMR, F8S1);\n+ FPMRType fmt_m = FIELD_EX64(fpmr, FPMR, F8S2);\n+ int scale = -((fpmr >> R_FPMR_LSCALE_SHIFT) & 0xf);\n+\n+ set_flush_to_zero(0, &stat);\n+ set_flush_inputs_to_zero(0, &stat);\n+ set_default_nan_mode(true, &stat);\n+ set_float_rounding_mode(FIELD_EX64(fpmr, FPMR, OSM)\n+ ? float_round_nearest_even_max\n+ : float_round_nearest_even, &stat);\n+\n+ for (size_t i = 0; i < nelem; i++) {\n+ FloatParts64 p0 = unpack_fp8(n[H1(2 * i + high)], fmt_n, &stat);\n+ FloatParts64 p1 = unpack_fp8(m[H1(2 * i + high)], fmt_m, &stat);\n+ FloatParts64 p2 = float16_unpack_canonical(d[H2(i)], &stat);\n+\n+ f8muladd(&p0, &p1, &p2, scale, &stat);\n+ d[H2(i)] = float16_round_pack_canonical(&p0, &stat);\n+ }\n+\n+ float_raise(get_float_exception_flags(&stat)\n+ & ~float_flag_input_denormal_used,\n+ &env->vfp.fp_status[FPST_A64]);\n+ clear_tail(vd, oprsz, simd_maxsz(desc));\n+}\n+\n+void HELPER(gvec_fmla_idx_hb)(void *vd, void *vn, void *vm,\n+ CPUARMState *env, uint32_t desc)\n+{\n+ float_status stat = env->vfp.fp_status[FPST_A64];\n+ bool idx_n = extract32(desc, SIMD_DATA_SHIFT, 1);\n+ size_t idx_m = extract32(desc, SIMD_DATA_SHIFT + 2, 4);\n+ size_t oprsz = simd_oprsz(desc);\n+ size_t nelem = oprsz / 2;\n+ uint8_t *n = vn;\n+ uint8_t *m = vm;\n+ float16 *d = vd;\n+\n+ uint64_t fpmr = env->vfp.fpmr;\n+ FPMRType fmt_n = FIELD_EX64(fpmr, FPMR, F8S1);\n+ FPMRType fmt_m = FIELD_EX64(fpmr, FPMR, F8S2);\n+ int scale = -((fpmr >> R_FPMR_LSCALE_SHIFT) & 0xf);\n+\n+ set_flush_to_zero(0, &stat);\n+ set_flush_inputs_to_zero(0, &stat);\n+ set_default_nan_mode(true, &stat);\n+ set_float_rounding_mode(FIELD_EX64(fpmr, FPMR, OSM)\n+ ? float_round_nearest_even_max\n+ : float_round_nearest_even, &stat);\n+\n+ for (size_t seg = 0; seg < nelem; seg += 8) {\n+ FloatParts64 p1 = unpack_fp8(m[H1(2 * seg + idx_m)], fmt_m, &stat);\n+\n+ for (size_t j = 0; j < 8; j++) {\n+ size_t i = seg + j;\n+ FloatParts64 p0 = unpack_fp8(n[H1(2 * i + idx_n)], fmt_n, &stat);\n+ FloatParts64 p2 = float16_unpack_canonical(d[H2(i)], &stat);\n+\n+ f8muladd(&p0, &p1, &p2, scale, &stat);\n+ d[H2(i)] = float16_round_pack_canonical(&p0, &stat);\n+ }\n+ }\n+\n+ float_raise(get_float_exception_flags(&stat)\n+ & ~float_flag_input_denormal_used,\n+ &env->vfp.fp_status[FPST_A64]);\n+ clear_tail(vd, oprsz, simd_maxsz(desc));\n+}\ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex ee71c63116..1c1d4ad2f7 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -7384,6 +7384,22 @@ TRANS_FEAT(FMLSL_vi, aa64_fhm, do_fmlal_idx, a, true, false)\n TRANS_FEAT(FMLAL2_vi, aa64_fhm, do_fmlal_idx, a, false, true)\n TRANS_FEAT(FMLSL2_vi, aa64_fhm, do_fmlal_idx, a, true, true)\n \n+static bool do_fmla_fp8(DisasContext *s, arg_rxx *a,\n+ gen_helper_gvec_3_ptr *fn)\n+{\n+ if (fpmr_access_check(s) && fp_access_check(s)) {\n+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),\n+ vec_full_reg_offset(s, a->rn),\n+ vec_full_reg_offset(s, a->rm),\n+ tcg_env, 16, vec_full_reg_size(s),\n+ a->idxn | (a->idxm << 2), fn);\n+ }\n+ return true;\n+}\n+\n+TRANS_FEAT(FMLAL_hb_v, aa64_f8fma, do_fmla_fp8, a, gen_helper_gvec_fmla_hb)\n+TRANS_FEAT(FMLAL_hb_vi, aa64_f8fma, do_fmla_fp8, a, gen_helper_gvec_fmla_idx_hb)\n+\n static bool do_int3_vector_idx(DisasContext *s, arg_qrrx_e *a,\n gen_helper_gvec_3 * const fns[2])\n {\ndiff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode\nindex 6aea3ce89f..b89e83ce76 100644\n--- a/target/arm/tcg/a64.decode\n+++ b/target/arm/tcg/a64.decode\n@@ -25,6 +25,7 @@\n %esz_hsd 22:2 !function=xor_2\n %hl 11:1 21:1\n %hlm 11:1 20:2\n+%hlm4 11:1 19:3\n \n &r rn\n &rrr rd rn rm\n@@ -38,6 +39,7 @@\n &rri_e rd rn imm esz\n &rrr_e rd rn rm esz\n &rrx_e rd rn rm idx esz\n+&rxx rd rn rm idxn idxm\n &rrrr_e rd rn rm ra esz\n &qrr_e q rd rn esz\n &qrri_e q rd rn imm esz\n@@ -1204,6 +1206,9 @@ FSCALE 0.10 1110 1.1 ..... 11111 1 ..... ..... @qrrr_sd\n FCVTN_bh 0.00 1110 010 ..... 11110 1 ..... ..... @qrrr_h\n FCVTN_bs 0.00 1110 000 ..... 11110 1 ..... ..... @qrrr_h\n \n+FMLAL_hb_v 0 idxn:1 00 1110 110 rm:5 11111 1 rn:5 rd:5 \\\n+ &rxx idxm=0\n+\n ### Advanced SIMD scalar x indexed element\n \n FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h\n@@ -1322,6 +1327,9 @@ SQDMLAL_vi 0.00 1111 10 . ..... 0011 . 0 ..... ..... @qrrx_s\n SQDMLSL_vi 0.00 1111 01 .. .... 0111 . 0 ..... ..... @qrrx_h\n SQDMLSL_vi 0.00 1111 10 . ..... 0111 . 0 ..... ..... @qrrx_s\n \n+FMLAL_hb_vi 0 idxn:1 00 1111 11 ... rm:3 0000 . 0 rn:5 rd:5 \\\n+ &rxx idxm=%hlm4\n+\n # Floating-point conditional select\n \n FCSEL 0001 1110 .. 1 rm:5 cond:4 11 rn:5 rd:5 esz=%esz_hsd\n","prefixes":["v3","43/47"]}