{"id":2230758,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230758/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-42-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260430002046.59739-42-richard.henderson@linaro.org>","date":"2026-04-30T00:20:40","name":"[v3,41/47] target/arm: Implement LUTI4 (four registers, 8-bit)","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"2d79471139e9db86da43040844f27855bba1c1a3","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.1/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-42-richard.henderson@linaro.org/mbox/","series":[{"id":502175,"url":"http://patchwork.ozlabs.org/api/1.1/series/502175/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502175","date":"2026-04-30T00:20:06","name":"target/arm: Implement FEAT_FP8","version":3,"mbox":"http://patchwork.ozlabs.org/series/502175/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230758/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230758/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=d6Cvgm27;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5ZkR1cNDz1yHv\n\tfor ; Thu, 30 Apr 2026 10:27:27 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wIFE1-00074s-7q; Wed, 29 Apr 2026 20:25:53 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wIFDi-0006S3-Lt\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:25:37 -0400","from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wIFDe-0007Tv-Ht\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:25:34 -0400","by mail-pg1-x52d.google.com with SMTP id\n 41be03b00d2f7-c76c067bc51so101177a12.0\n for ; Wed, 29 Apr 2026 17:25:26 -0700 (PDT)","from stoup.. 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","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Richard Henderson \n---\n target/arm/cpu-features.h | 5 +++++\n target/arm/tcg/helper-defs.h | 1 +\n target/arm/tcg/translate-sme.c | 6 ++++++\n target/arm/tcg/vec_helper.c | 14 ++++++++++++++\n target/arm/tcg/sme.decode | 6 ++++++\n 5 files changed, 32 insertions(+)","diff":"diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex 4b228b4f3b..535c1e4792 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1629,6 +1629,11 @@ static inline bool isar_feature_aa64_sme2_f8cvt(const ARMISARegisters *id)\n return isar_feature_aa64_sme2(id) && isar_feature_aa64_f8cvt(id);\n }\n \n+static inline bool isar_feature_aa64_sme2p1_lutv2(const ARMISARegisters *id)\n+{\n+ return isar_feature_aa64_sme2p1(id) && isar_feature_aa64_sme_lutv2(id);\n+}\n+\n static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id)\n {\n return isar_feature_aa64_sve(id) && isar_feature_aa64_sme_sve_i8mm(id);\ndiff --git a/target/arm/tcg/helper-defs.h b/target/arm/tcg/helper-defs.h\nindex 05ccf795e8..8ec6c16319 100644\n--- a/target/arm/tcg/helper-defs.h\n+++ b/target/arm/tcg/helper-defs.h\n@@ -1120,6 +1120,7 @@ DEF_HELPER_FLAGS_4(sme2_luti4_2b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sme2_luti4_2h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sme2_luti4_2s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n \n+DEF_HELPER_FLAGS_4(sme2_luti4_4b, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sme2_luti4_4h, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sme2_luti4_4s, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n \ndiff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c\nindex 214427db1f..0af133c1c4 100644\n--- a/target/arm/tcg/translate-sme.c\n+++ b/target/arm/tcg/translate-sme.c\n@@ -1846,6 +1846,9 @@ TRANS_FEAT(LUTI4_c_2s, aa64_sme2, do_lut, a, gen_helper_sme2_luti4_2s, false)\n TRANS_FEAT(LUTI4_c_4h, aa64_sme2, do_lut, a, gen_helper_sme2_luti4_4h, false)\n TRANS_FEAT(LUTI4_c_4s, aa64_sme2, do_lut, a, gen_helper_sme2_luti4_4s, false)\n \n+TRANS_FEAT(LUTI4_c_4b, aa64_sme_lutv2, do_lut, a,\n+ gen_helper_sme2_luti4_4b, false)\n+\n static bool do_lut_s4(DisasContext *s, arg_lut *a, gen_helper_gvec_2_ptr *fn)\n {\n return !(a->zd & 0b01100) && do_lut(s, a, fn, true);\n@@ -1866,3 +1869,6 @@ TRANS_FEAT(LUTI4_s_2b, aa64_sme2p1, do_lut_s8, a, gen_helper_sme2_luti4_2b)\n TRANS_FEAT(LUTI4_s_2h, aa64_sme2p1, do_lut_s8, a, gen_helper_sme2_luti4_2h)\n \n TRANS_FEAT(LUTI4_s_4h, aa64_sme2p1, do_lut_s4, a, gen_helper_sme2_luti4_4h)\n+\n+TRANS_FEAT(LUTI4_s_4b, aa64_sme2p1_lutv2, do_lut_s4, a,\n+ gen_helper_sme2_luti4_4b)\ndiff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c\nindex f0dc11bc8a..20ecdb0a9e 100644\n--- a/target/arm/tcg/vec_helper.c\n+++ b/target/arm/tcg/vec_helper.c\n@@ -3346,6 +3346,20 @@ DO_SME2_LUT(4,4,s, 4)\n \n #undef DO_SME2_LUT\n \n+void helper_sme2_luti4_4b(void *zd, void *zn, CPUARMState *env, uint32_t desc)\n+{\n+ unsigned vl = simd_oprsz(desc);\n+ unsigned strided = extract32(desc, SIMD_DATA_SHIFT, 1);\n+ unsigned dstride = !strided ? 1 : 4;\n+ uint64_t indexes[ARM_MAX_VQ * 4];\n+\n+ memcpy(&indexes, zn, vl);\n+ memcpy((void *)&indexes + vl, zn + sizeof(ARMVectorReg), vl);\n+\n+ do_lut_b(zd, indexes, (void *)env->za_state.zt0, vl, 0,\n+ dstride * sizeof(ARMVectorReg), 4, 32, 4);\n+}\n+\n void HELPER(gvec_luti2_b)(void *vd, void *vn, void *vm, uint32_t desc)\n {\n unsigned part = simd_data(desc);\ndiff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode\nindex 339de72b8a..495330aed7 100644\n--- a/target/arm/tcg/sme.decode\n+++ b/target/arm/tcg/sme.decode\n@@ -1014,8 +1014,14 @@ LUTI4_c_2s 1100 0000 1000 101 idx:2 1 10 00 zn:5 .... 0 &lut zd=%zd_ax2\n LUTI4_c_4h 1100 0000 1000 101 idx:1 10 01 00 zn:5 ... 00 &lut zd=%zd_ax4\n LUTI4_c_4s 1100 0000 1000 101 idx:1 10 10 00 zn:5 ... 00 &lut zd=%zd_ax4\n \n+LUTI4_c_4b 1100 0000 1000 101 1 00 00 00 ....0 ...00 \\\n+ &lut zd=%zd_ax4 zn=%zn_ax2 idx=0\n+\n # LUTI4, strided (must check zd alignment)\n LUTI4_s_2b 1100 0000 1001 101 idx:2 1 00 00 zn:5 zd:5 &lut\n LUTI4_s_2h 1100 0000 1001 101 idx:2 1 01 00 zn:5 zd:5 &lut\n \n LUTI4_s_4h 1100 0000 1001 101 idx:1 10 01 00 zn:5 zd:5 &lut\n+\n+LUTI4_s_4b 1100 0000 1001 101 1 00 00 00 ....0 zd:5 \\\n+ &lut zn=%zn_ax2 idx=0\n","prefixes":["v3","41/47"]}