{"id":2230755,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230755/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-27-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260430002046.59739-27-richard.henderson@linaro.org>","date":"2026-04-30T00:20:25","name":"[v3,26/47] target/arm: Implement F1CVT, F1CVTLT, F2CVT, F2CVTLT for SVE","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"6791bda48e75efd8df105e8aedb196ca166992b4","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.1/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-27-richard.henderson@linaro.org/mbox/","series":[{"id":502175,"url":"http://patchwork.ozlabs.org/api/1.1/series/502175/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502175","date":"2026-04-30T00:20:06","name":"target/arm: Implement FEAT_FP8","version":3,"mbox":"http://patchwork.ozlabs.org/series/502175/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230755/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230755/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=t0lkkA+X;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5Zjy3mYPz1yHv\n\tfor ; Thu, 30 Apr 2026 10:27:02 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wIFAI-00078J-Dx; Wed, 29 Apr 2026 20:22:02 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wIFA8-0006sh-MN\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:21:53 -0400","from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wIFA6-0006Q5-KD\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:21:52 -0400","by mail-pf1-x42f.google.com with SMTP id\n d2e1a72fcca58-82418b0178cso197148b3a.1\n for ; Wed, 29 Apr 2026 17:21:50 -0700 (PDT)","from stoup.. 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helo=mail-pf1-x42f.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Richard Henderson \n---\n target/arm/tcg/helper-fp8-defs.h | 1 +\n target/arm/tcg/fp8_helper.c | 28 ++++++++++++++++++++++++++++\n target/arm/tcg/translate-sve.c | 9 +++++++++\n target/arm/tcg/sve.decode | 5 +++++\n 4 files changed, 43 insertions(+)","diff":"diff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-defs.h\nindex 718463422b..3021dafd44 100644\n--- a/target/arm/tcg/helper-fp8-defs.h\n+++ b/target/arm/tcg/helper-fp8-defs.h\n@@ -9,3 +9,4 @@ DEF_HELPER_FLAGS_4(sme2_bfcvt_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sme2_bfcvtl_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n \n DEF_HELPER_FLAGS_4(advsimd_fcvtl_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n+DEF_HELPER_FLAGS_4(sve2_fcvt_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\ndiff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c\nindex 2739cdb343..2d5fd688cc 100644\n--- a/target/arm/tcg/fp8_helper.c\n+++ b/target/arm/tcg/fp8_helper.c\n@@ -221,6 +221,34 @@ void HELPER(sve2_bfcvt)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n fp8_finish(env, &ctx);\n }\n \n+void HELPER(sve2_fcvt_hb)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n+{\n+ FP8Context ctx = fp8_src_start(env, desc, 0xf);\n+ uint8_t *n = vn;\n+ uint16_t *d = vd;\n+ size_t nelem = simd_oprsz(desc) / 2;\n+\n+ switch (ctx.f8fmt) {\n+ case OFP8_E5M2:\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float8_e5m2 e = n[H1(2 * i + ctx.high)];\n+ d[H2(i)] = fcvt_fp8e5m2_to_f16(e, ctx.scale, &ctx.stat);\n+ }\n+ break;\n+ case OFP8_E4M3:\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float8_e4m3 e = n[H1(2 * i + ctx.high)];\n+ d[H2(i)] = fcvt_fp8e4m3_to_f16(e, ctx.scale, &ctx.stat);\n+ }\n+ break;\n+ default:\n+ float16_invalid_input(d, nelem, &ctx.stat);\n+ break;\n+ }\n+\n+ fp8_finish(env, &ctx);\n+}\n+\n void HELPER(sme2_bfcvt_hb)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n {\n FP8Context ctx = fp8_src_start(env, desc, 0x3f);\ndiff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c\nindex 9bab5feb93..5200f3d034 100644\n--- a/target/arm/tcg/translate-sve.c\n+++ b/target/arm/tcg/translate-sve.c\n@@ -4081,6 +4081,15 @@ static bool do_f8cvt(DisasContext *s, arg_rr_esz *a,\n return true;\n }\n \n+TRANS_FEAT(F1CVT, aa64_sme2_or_sve2_f8cvt, do_f8cvt, a,\n+ gen_helper_sve2_fcvt_hb, false, false)\n+TRANS_FEAT(F2CVT, aa64_sme2_or_sve2_f8cvt, do_f8cvt, a,\n+ gen_helper_sve2_fcvt_hb, true, false)\n+TRANS_FEAT(F1CVTLT, aa64_sme2_or_sve2_f8cvt, do_f8cvt, a,\n+ gen_helper_sve2_fcvt_hb, false, true)\n+TRANS_FEAT(F2CVTLT, aa64_sme2_or_sve2_f8cvt, do_f8cvt, a,\n+ gen_helper_sve2_fcvt_hb, true, true)\n+\n TRANS_FEAT(BF1CVT, aa64_sme2_or_sve2_f8cvt, do_f8cvt, a,\n gen_helper_sve2_bfcvt, false, false)\n TRANS_FEAT(BF2CVT, aa64_sme2_or_sve2_f8cvt, do_f8cvt, a,\ndiff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode\nindex e7984fa8e0..ca110f4bc1 100644\n--- a/target/arm/tcg/sve.decode\n+++ b/target/arm/tcg/sve.decode\n@@ -1091,6 +1091,11 @@ FMINQV 01100100 .. 010 111 101 ... ..... ..... @rd_pg_rn\n FRECPE 01100101 .. 001 110 001100 ..... ..... @rd_rn\n FRSQRTE 01100101 .. 001 111 001100 ..... ..... @rd_rn\n \n+F1CVT 01100101 00 001 000 001100 ..... ..... @rd_rn_e0\n+F2CVT 01100101 00 001 000 001101 ..... ..... @rd_rn_e0\n+F1CVTLT 01100101 00 001 001 001100 ..... ..... @rd_rn_e0\n+F2CVTLT 01100101 00 001 001 001101 ..... ..... @rd_rn_e0\n+\n BF1CVT 01100101 00 001 000 001110 ..... ..... @rd_rn_e0\n BF2CVT 01100101 00 001 000 001111 ..... ..... @rd_rn_e0\n BF1CVTLT 01100101 00 001 001 001110 ..... ..... @rd_rn_e0\n","prefixes":["v3","26/47"]}