{"id":2230746,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230746/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-25-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260430002046.59739-25-richard.henderson@linaro.org>","date":"2026-04-30T00:20:23","name":"[v3,24/47] target/arm: Implement BF1CVT, BF1CVTL, BF2CVT, BF2CVTL for SME","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"0f561c47759a39079282c00af269524c8e07c0f0","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.1/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-25-richard.henderson@linaro.org/mbox/","series":[{"id":502175,"url":"http://patchwork.ozlabs.org/api/1.1/series/502175/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502175","date":"2026-04-30T00:20:06","name":"target/arm: Implement FEAT_FP8","version":3,"mbox":"http://patchwork.ozlabs.org/series/502175/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230746/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230746/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=bkutybNX;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5Zj26mNZz1yJr\n\tfor ; Thu, 30 Apr 2026 10:26:14 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wIFAK-0007JB-Ms; Wed, 29 Apr 2026 20:22:04 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wIFA5-0006pf-RD\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:21:51 -0400","from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wIFA2-0006Ns-N1\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:21:48 -0400","by mail-pf1-x433.google.com with SMTP id\n d2e1a72fcca58-82d0b68837aso190803b3a.2\n for ; Wed, 29 Apr 2026 17:21:45 -0700 (PDT)","from stoup.. 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helo=mail-pf1-x433.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Richard Henderson \n---\n target/arm/tcg/helper-fp8-defs.h | 2 +\n target/arm/tcg/fp8_helper.c | 79 ++++++++++++++++++++++++++++++++\n target/arm/tcg/translate-sme.c | 19 ++++++++\n target/arm/tcg/sme.decode | 5 ++\n 4 files changed, 105 insertions(+)","diff":"diff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-defs.h\nindex 18ff483bb0..966f83d796 100644\n--- a/target/arm/tcg/helper-fp8-defs.h\n+++ b/target/arm/tcg/helper-fp8-defs.h\n@@ -5,3 +5,5 @@\n \n DEF_HELPER_FLAGS_4(advsimd_bfcvtl, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sve2_bfcvt, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n+DEF_HELPER_FLAGS_4(sme2_bfcvt_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n+DEF_HELPER_FLAGS_4(sme2_bfcvtl_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\ndiff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c\nindex a4c7c44e6f..7598871f87 100644\n--- a/target/arm/tcg/fp8_helper.c\n+++ b/target/arm/tcg/fp8_helper.c\n@@ -164,3 +164,82 @@ void HELPER(sve2_bfcvt)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n \n fp8_finish(env, &ctx);\n }\n+\n+void HELPER(sme2_bfcvt_hb)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n+{\n+ FP8Context ctx = fp8_src_start(env, desc, 0x3f);\n+ uint8_t *n = vn;\n+ uint16_t *d0 = vd;\n+ uint16_t *d1 = vd + sizeof(ARMVectorReg);\n+ size_t oprsz = simd_oprsz(desc);\n+ size_t nelem = oprsz / 2;\n+ ARMVectorReg scratch;\n+\n+ if (vectors_overlap(vd, 2, vn, 1)) {\n+ n = memcpy(&scratch, vn, oprsz);\n+ }\n+\n+ switch (ctx.f8fmt) {\n+ case OFP8_E5M2:\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float8_e5m2 e = n[H1(i)];\n+ d0[H2(i)] = fcvt_fp8e5m2_to_b16(e, ctx.scale, &ctx.stat);\n+ }\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float8_e5m2 e = n[H1(i) + nelem];\n+ d1[H2(i)] = fcvt_fp8e5m2_to_b16(e, ctx.scale, &ctx.stat);\n+ }\n+ break;\n+ case OFP8_E4M3:\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float8_e4m3 e = n[H1(i)];\n+ d0[H2(i)] = fcvt_fp8e4m3_to_b16(e, ctx.scale, &ctx.stat);\n+ }\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float8_e4m3 e = n[H1(i) + nelem];\n+ d1[H2(i)] = fcvt_fp8e4m3_to_b16(e, ctx.scale, &ctx.stat);\n+ }\n+ break;\n+ default:\n+ bfloat16_invalid_input(d0, nelem, &ctx.stat);\n+ memcpy(d1, d0, oprsz);\n+ break;\n+ }\n+\n+ fp8_finish(env, &ctx);\n+}\n+\n+void HELPER(sme2_bfcvtl_hb)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n+{\n+ FP8Context ctx = fp8_src_start(env, desc, 0x3f);\n+ uint8_t *n = vn;\n+ uint16_t *d0 = vd;\n+ uint16_t *d1 = vd + sizeof(ARMVectorReg);\n+ size_t oprsz = simd_oprsz(desc);\n+ size_t nelem = oprsz / 2;\n+\n+ switch (ctx.f8fmt) {\n+ case OFP8_E5M2:\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float8_e5m2 e0 = n[H1(2 * i + 0)];\n+ float8_e5m2 e1 = n[H1(2 * i + 1)];\n+ d0[H2(i)] = fcvt_fp8e5m2_to_b16(e0, ctx.scale, &ctx.stat);\n+ d1[H2(i)] = fcvt_fp8e5m2_to_b16(e1, ctx.scale, &ctx.stat);\n+ }\n+ break;\n+ case OFP8_E4M3:\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float8_e4m3 e0 = n[H1(2 * i + 0)];\n+ float8_e4m3 e1 = n[H1(2 * i + 1)];\n+ d0[H2(i)] = fcvt_fp8e4m3_to_b16(e0, ctx.scale, &ctx.stat);\n+ d1[H2(i)] = fcvt_fp8e4m3_to_b16(e1, ctx.scale, &ctx.stat);\n+ }\n+ break;\n+ default:\n+ bfloat16_invalid_input(d0, nelem, &ctx.stat);\n+ memcpy(d1, d0, oprsz);\n+ break;\n+ }\n+\n+ fp8_finish(env, &ctx);\n+}\ndiff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c\nindex 88c1d78c40..2841b2b8cb 100644\n--- a/target/arm/tcg/translate-sme.c\n+++ b/target/arm/tcg/translate-sme.c\n@@ -22,6 +22,7 @@\n #include \"helper-a64.h\"\n #include \"helper-sme.h\"\n #include \"helper-sve.h\"\n+#include \"helper-fp8.h\"\n #include \"translate.h\"\n #include \"translate-a64.h\"\n #include \"tcg/tcg-op.h\"\n@@ -1532,6 +1533,24 @@ TRANS_FEAT(UUNPK_4bh, aa64_sme2, do_zz, a, 0, gen_helper_sme2_uunpk4_bh)\n TRANS_FEAT(UUNPK_4hs, aa64_sme2, do_zz, a, 0, gen_helper_sme2_uunpk4_hs)\n TRANS_FEAT(UUNPK_4sd, aa64_sme2, do_zz, a, 0, gen_helper_sme2_uunpk4_sd)\n \n+static bool do_f8cvt(DisasContext *s, arg_zz_n *a,\n+ gen_helper_gvec_2_ptr *fn, bool issrc2)\n+{\n+ if (fpmr_access_check(s) && sme_sm_enabled_check(s)) {\n+ int svl = streaming_vec_reg_size(s);\n+ tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, a->zd),\n+ vec_full_reg_offset(s, a->zn),\n+ tcg_env, svl, svl,\n+ issrc2 | (FPST_ZA << 2), fn);\n+ }\n+ return true;\n+}\n+\n+TRANS_FEAT(BF1CVT, aa64_sme2_f8cvt, do_f8cvt, a, gen_helper_sme2_bfcvt_hb, 0)\n+TRANS_FEAT(BF2CVT, aa64_sme2_f8cvt, do_f8cvt, a, gen_helper_sme2_bfcvt_hb, 1)\n+TRANS_FEAT(BF1CVTL, aa64_sme2_f8cvt, do_f8cvt, a, gen_helper_sme2_bfcvtl_hb, 0)\n+TRANS_FEAT(BF2CVTL, aa64_sme2_f8cvt, do_f8cvt, a, gen_helper_sme2_bfcvtl_hb, 1)\n+\n static bool do_zipuzp_4(DisasContext *s, arg_zz_e *a,\n gen_helper_gvec_2 * const fn[5])\n {\ndiff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode\nindex 7a8e1abb59..df9586c1a5 100644\n--- a/target/arm/tcg/sme.decode\n+++ b/target/arm/tcg/sme.decode\n@@ -853,6 +853,11 @@ UUNPK_4bh 11000001 011 10101 111000 ....0 ...01 @zz_4x2_n1\n UUNPK_4hs 11000001 101 10101 111000 ....0 ...01 @zz_4x2_n1\n UUNPK_4sd 11000001 111 10101 111000 ....0 ...01 @zz_4x2_n1\n \n+BF1CVT 11000001 011 00110 111000 ..... ....0 @zz_2x1\n+BF2CVT 11000001 111 00110 111000 ..... ....0 @zz_2x1\n+BF1CVTL 11000001 011 00110 111000 ..... ....1 @zz_2x1\n+BF2CVTL 11000001 111 00110 111000 ..... ....1 @zz_2x1\n+\n ZIP_4 11000001 esz:2 1 10110 111000 ...00 ... 00 \\\n &zz_e zd=%zd_ax4 zn=%zn_ax4\n ZIP_4 11000001 001 10111 111000 ...00 ... 00 \\\n","prefixes":["v3","24/47"]}