{"id":2230725,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230725/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-32-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260430002046.59739-32-richard.henderson@linaro.org>","date":"2026-04-30T00:20:30","name":"[v3,31/47] target/arm: Implement FCVTN (16- to 8-bit fp) for SVE","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"87ea2d90cb27d6300cb456dcdc9592afe4963642","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.1/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-32-richard.henderson@linaro.org/mbox/","series":[{"id":502175,"url":"http://patchwork.ozlabs.org/api/1.1/series/502175/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502175","date":"2026-04-30T00:20:06","name":"target/arm: Implement FEAT_FP8","version":3,"mbox":"http://patchwork.ozlabs.org/series/502175/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230725/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230725/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=whe3Pftm;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5ZdB5zVSz1yHZ\n\tfor ; Thu, 30 Apr 2026 10:22:54 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wIFAQ-0007YQ-3V; Wed, 29 Apr 2026 20:22:10 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wIFAJ-0007Gc-Tx\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:22:03 -0400","from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wIFAH-0006V0-Qe\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:22:03 -0400","by mail-pg1-x52b.google.com with SMTP id\n 41be03b00d2f7-c648bc907ebso180032a12.3\n for ; Wed, 29 Apr 2026 17:22:01 -0700 (PDT)","from stoup.. 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helo=mail-pg1-x52b.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Richard Henderson \n---\n target/arm/tcg/helper-fp8-defs.h | 1 +\n target/arm/tcg/fp8_helper.c | 40 ++++++++++++++++++++++++++++++++\n target/arm/tcg/translate-sve.c | 2 ++\n target/arm/tcg/sve.decode | 1 +\n 4 files changed, 44 insertions(+)","diff":"diff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-defs.h\nindex 023a49e12f..e67fb191c2 100644\n--- a/target/arm/tcg/helper-fp8-defs.h\n+++ b/target/arm/tcg/helper-fp8-defs.h\n@@ -16,5 +16,6 @@ DEF_HELPER_FLAGS_4(sme2_fcvtl_hb, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_4(sve2_bfcvtn_bh, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n \n DEF_HELPER_FLAGS_5(gvec_fcvt_bh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\n+DEF_HELPER_FLAGS_4(sve2_fcvtn_bh, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n \n DEF_HELPER_FLAGS_5(advsimd_fcvt_bs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\ndiff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c\nindex facbf4f6c6..9c89964721 100644\n--- a/target/arm/tcg/fp8_helper.c\n+++ b/target/arm/tcg/fp8_helper.c\n@@ -587,6 +587,46 @@ void HELPER(gvec_fcvt_bh)(void *vd, void *vn, void *vm,\n clear_tail(vd, oprsz, simd_maxsz(desc));\n }\n \n+void HELPER(sve2_fcvtn_bh)(void *vd, void *vn, CPUARMState *env, uint32_t desc)\n+{\n+ FP8Context ctx = fp8_dst_start(env, desc);\n+ uint16_t *n0 = vn;\n+ uint16_t *n1 = vn + sizeof(ARMVectorReg);\n+ uint8_t *d = vd;\n+ bool osc = FIELD_EX64(env->vfp.fpmr, FPMR, OSC);\n+ size_t oprsz = simd_oprsz(desc);\n+ size_t nelem = oprsz / 2;\n+\n+ switch (ctx.f8fmt) {\n+ case OFP8_E5M2:\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float16 e0 = n0[H2(i)];\n+ float16 e1 = n1[H2(i)];\n+ d[H1(2 * i + 0)] =\n+ fcvt_f16_to_fp8e5m2(e0, ctx.scale, osc, &ctx.stat);\n+ d[H1(2 * i + 1)] =\n+ fcvt_f16_to_fp8e5m2(e1, ctx.scale, osc, &ctx.stat);\n+ }\n+ break;\n+ case OFP8_E4M3:\n+ for (size_t i = 0; i < nelem; ++i) {\n+ float16 e0 = n0[H2(i)];\n+ float16 e1 = n1[H2(i)];\n+ d[H1(2 * i + 0)] =\n+ fcvt_f16_to_fp8e4m3(e0, ctx.scale, osc, &ctx.stat);\n+ d[H1(2 * i + 1)] =\n+ fcvt_f16_to_fp8e4m3(e1, ctx.scale, osc, &ctx.stat);\n+ }\n+ break;\n+ default:\n+ float8_invalid_output(d, oprsz, &ctx.stat);\n+ break;\n+ }\n+\n+ fp8_finish(env, &ctx);\n+}\n+\n+\n void HELPER(advsimd_fcvt_bs)(void *vd, void *vn, void *vm,\n CPUARMState *env, uint32_t desc)\n {\ndiff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c\nindex 7276d9c44a..c7fcf27183 100644\n--- a/target/arm/tcg/translate-sve.c\n+++ b/target/arm/tcg/translate-sve.c\n@@ -4099,6 +4099,8 @@ TRANS_FEAT(BF1CVTLT, aa64_sme2_or_sve2_f8cvt, do_f8cvt, a,\n TRANS_FEAT(BF2CVTLT, aa64_sme2_or_sve2_f8cvt, do_f8cvt, a,\n gen_helper_sve2_bfcvt, true, true)\n \n+TRANS_FEAT(FCVTN, aa64_sme2_or_sve2_f8cvt, do_f8cvt,\n+ a, gen_helper_sve2_fcvtn_bh, false, false)\n TRANS_FEAT(BFCVTN, aa64_sme2_or_sve2_f8cvt, do_f8cvt,\n a, gen_helper_sve2_bfcvtn_bh, false, false)\n \ndiff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode\nindex b6ef8ed8de..806953bc35 100644\n--- a/target/arm/tcg/sve.decode\n+++ b/target/arm/tcg/sve.decode\n@@ -1101,6 +1101,7 @@ BF2CVT 01100101 00 001 000 001111 ..... ..... @rd_rn_e0\n BF1CVTLT 01100101 00 001 001 001110 ..... ..... @rd_rn_e0\n BF2CVTLT 01100101 00 001 001 001111 ..... ..... @rd_rn_e0\n \n+FCVTN 01100101 00 001 010 001100 ....0 ..... @rd_rnx2 esz=1\n BFCVTN 01100101 00 001 010 001110 ....0 ..... @rd_rnx2 esz=1\n \n ### SVE FP Compare with Zero Group\n","prefixes":["v3","31/47"]}