{"id":2230688,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230688/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430000524.56046-15-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260430000524.56046-15-richard.henderson@linaro.org>","date":"2026-04-30T00:04:57","name":"[v2,14/40] fpu: Return struct from parts{64,128}_return_nan","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e82b10d8be0323e8d6843ce2b896b86f8d94e6e1","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.1/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430000524.56046-15-richard.henderson@linaro.org/mbox/","series":[{"id":502170,"url":"http://patchwork.ozlabs.org/api/1.1/series/502170/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502170","date":"2026-04-30T00:04:48","name":"fpu: Export some internals for targets","version":2,"mbox":"http://patchwork.ozlabs.org/series/502170/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230688/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230688/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=lsVT37T6;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5ZKY6lD2z1yJr\n\tfor ; Thu, 30 Apr 2026 10:09:21 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wIEur-0006hT-9p; Wed, 29 Apr 2026 20:06:05 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wIEup-0006dt-Qn\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:06:03 -0400","from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wIEuo-0001mn-2L\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:06:03 -0400","by mail-pf1-x42d.google.com with SMTP id\n d2e1a72fcca58-82f4a53ae20so240947b3a.3\n for ; Wed, 29 Apr 2026 17:06:01 -0700 (PDT)","from stoup.. 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","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Richard Henderson \n---\n fpu/softfloat.c | 14 +++++++-------\n fpu/softfloat-parts.c.inc | 15 ++++++++-------\n 2 files changed, 15 insertions(+), 14 deletions(-)","diff":"diff --git a/fpu/softfloat.c b/fpu/softfloat.c\nindex 9c1e6fdce4..7d67e25c17 100644\n--- a/fpu/softfloat.c\n+++ b/fpu/softfloat.c\n@@ -2378,7 +2378,7 @@ static void parts_float_to_e5m2(FloatParts64 *a, float_status *s, bool saturate)\n switch (a->cls) {\n case float_class_snan:\n case float_class_qnan:\n- parts64_return_nan(a, s);\n+ *a = parts64_return_nan(a, s);\n break;\n \n case float_class_inf:\n@@ -2405,7 +2405,7 @@ static void parts_float_to_e5m2(FloatParts64 *a, float_status *s, bool saturate)\n static void parts64_float_to_float(FloatParts64 *a, float_status *s)\n {\n if (is_nan(a->cls)) {\n- parts64_return_nan(a, s);\n+ *a = parts64_return_nan(a, s);\n }\n if (a->cls == float_class_denormal) {\n float_raise(float_flag_input_denormal_used, s);\n@@ -2415,7 +2415,7 @@ static void parts64_float_to_float(FloatParts64 *a, float_status *s)\n static void parts128_float_to_float(FloatParts128 *a, float_status *s)\n {\n if (is_nan(a->cls)) {\n- parts128_return_nan(a, s);\n+ *a = parts128_return_nan(a, s);\n }\n if (a->cls == float_class_denormal) {\n float_raise(float_flag_input_denormal_used, s);\n@@ -2441,7 +2441,7 @@ static FloatParts64 parts128_to_parts64(FloatParts128 *b, float_status *s)\n case float_class_qnan:\n /* Discard the low bits of the NaN. */\n r.frac = b->frac_hi;\n- parts64_return_nan(&r, s);\n+ r = parts64_return_nan(&r, s);\n break;\n default:\n break;\n@@ -2461,7 +2461,7 @@ static FloatParts128 parts64_to_parts128(FloatParts64 *b, float_status *s)\n switch (r.cls) {\n case float_class_qnan:\n case float_class_snan:\n- parts128_return_nan(&r, s);\n+ r = parts128_return_nan(&r, s);\n break;\n case float_class_denormal:\n float_raise(float_flag_input_denormal_used, s);\n@@ -4458,7 +4458,7 @@ static void parts64_log2(FloatParts64 *a, float_status *s, const FloatFmt *fmt)\n break;\n case float_class_snan:\n case float_class_qnan:\n- parts64_return_nan(a, s);\n+ *a = parts64_return_nan(a, s);\n return;\n case float_class_zero:\n float_raise(float_flag_divbyzero, s);\n@@ -5067,7 +5067,7 @@ float32 float32_exp2(float32 a, float_status *status)\n break;\n case float_class_snan:\n case float_class_qnan:\n- parts64_return_nan(&xp, status);\n+ xp = parts64_return_nan(&xp, status);\n return float32_round_pack_canonical(&xp, status);\n case float_class_inf:\n return xp.sign ? float32_zero : a;\ndiff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc\nindex 4733755f35..ef46dd740c 100644\n--- a/fpu/softfloat-parts.c.inc\n+++ b/fpu/softfloat-parts.c.inc\n@@ -15,25 +15,26 @@\n * indicated otherwise.\n */\n \n-static void partsN(return_nan)(FloatPartsN *a, float_status *s)\n+static FloatPartsN partsN(return_nan)(const FloatPartsN *a, float_status *s)\n {\n switch (a->cls) {\n case float_class_snan:\n float_raise(float_flag_invalid | float_flag_invalid_snan, s);\n if (s->default_nan_mode) {\n- *a = partsN(default_nan)(s);\n+ return partsN(default_nan)(s);\n } else {\n- *a = partsN(silence_nan)(a, s);\n+ return partsN(silence_nan)(a, s);\n }\n break;\n case float_class_qnan:\n if (s->default_nan_mode) {\n- *a = partsN(default_nan)(s);\n+ return partsN(default_nan)(s);\n }\n break;\n default:\n g_assert_not_reached();\n }\n+ return *a;\n }\n \n static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,\n@@ -941,7 +942,7 @@ static void partsN(sqrt)(FloatPartsN *a, float_status *status,\n break;\n case float_class_snan:\n case float_class_qnan:\n- partsN(return_nan)(a, status);\n+ *a = partsN(return_nan)(a, status);\n return;\n case float_class_zero:\n return;\n@@ -1263,7 +1264,7 @@ static void partsN(round_to_int)(FloatPartsN *a, FloatRoundMode rmode,\n switch (a->cls) {\n case float_class_qnan:\n case float_class_snan:\n- partsN(return_nan)(a, s);\n+ *a = partsN(return_nan)(a, s);\n break;\n case float_class_zero:\n case float_class_inf:\n@@ -1656,7 +1657,7 @@ static void partsN(scalbn)(FloatPartsN *a, int n, float_status *s)\n switch (a->cls) {\n case float_class_snan:\n case float_class_qnan:\n- partsN(return_nan)(a, s);\n+ *a = partsN(return_nan)(a, s);\n break;\n case float_class_zero:\n case float_class_inf:\n","prefixes":["v2","14/40"]}