{"id":2230683,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230683/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430000524.56046-10-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260430000524.56046-10-richard.henderson@linaro.org>","date":"2026-04-30T00:04:52","name":"[v2,09/40] fpu: Split FloatParts{64,128} to softfloat-parts.h","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"3f280368ce3a571b2c2c38ba7e259450207e1bc4","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.1/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430000524.56046-10-richard.henderson@linaro.org/mbox/","series":[{"id":502170,"url":"http://patchwork.ozlabs.org/api/1.1/series/502170/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502170","date":"2026-04-30T00:04:48","name":"fpu: Export some internals for targets","version":2,"mbox":"http://patchwork.ozlabs.org/series/502170/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230683/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230683/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=EgCZU4FS;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5ZJY2gJhz1yHZ\n\tfor ; Thu, 30 Apr 2026 10:08:29 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wIEui-0006IQ-HY; Wed, 29 Apr 2026 20:05:56 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wIEue-0006Ao-Ng\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:05:52 -0400","from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wIEuc-0001ku-MR\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:05:52 -0400","by mail-pf1-x42a.google.com with SMTP id\n d2e1a72fcca58-82748257f5fso1056320b3a.1\n for ; Wed, 29 Apr 2026 17:05:50 -0700 (PDT)","from stoup.. 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Those parts of the code (and\n+ * some later contributions) are provided under that license, as detailed below.\n+ * It has subsequently been modified by contributors to the QEMU Project,\n+ * so some portions are provided under:\n+ * the SoftFloat-2a license\n+ * the BSD license\n+ * GPL-v2-or-later\n+ *\n+ * Any future contributions to this file after December 1st 2014 will be\n+ * taken to be licensed under the Softfloat-2a license unless specifically\n+ * indicated otherwise.\n+ */\n+\n+#ifndef SOFTFLOAT_PARTS_H\n+#define SOFTFLOAT_PARTS_H\n+\n+/*\n+ * Classify a floating point number. Everything above float_class_qnan\n+ * is a NaN so cls >= float_class_qnan is any NaN.\n+ *\n+ * Note that we canonicalize denormals, so most code should treat\n+ * class_normal and class_denormal identically.\n+ */\n+\n+typedef enum __attribute__ ((__packed__)) {\n+ float_class_unclassified,\n+ float_class_zero,\n+ float_class_normal,\n+ float_class_denormal, /* input was a non-squashed denormal */\n+ float_class_inf,\n+ float_class_qnan, /* all NaNs from here */\n+ float_class_snan,\n+} FloatClass;\n+\n+#define float_cmask(bit) (1u << (bit))\n+\n+enum {\n+ float_cmask_zero = float_cmask(float_class_zero),\n+ float_cmask_normal = float_cmask(float_class_normal),\n+ float_cmask_denormal = float_cmask(float_class_denormal),\n+ float_cmask_inf = float_cmask(float_class_inf),\n+ float_cmask_qnan = float_cmask(float_class_qnan),\n+ float_cmask_snan = float_cmask(float_class_snan),\n+\n+ float_cmask_infzero = float_cmask_zero | float_cmask_inf,\n+ float_cmask_anynan = float_cmask_qnan | float_cmask_snan,\n+ float_cmask_anynorm = float_cmask_normal | float_cmask_denormal,\n+};\n+\n+/*\n+ * Structure holding all of the decomposed parts of a float.\n+ * The exponent is unbiased and the fraction is normalized.\n+ *\n+ * The fraction words are stored in big-endian word ordering,\n+ * so that truncation from a larger format to a smaller format\n+ * can be done simply by ignoring subsequent elements.\n+ */\n+\n+typedef struct {\n+ FloatClass cls;\n+ bool sign;\n+ int32_t exp;\n+ union {\n+ /* Routines that know the structure may reference the singular name. */\n+ uint64_t frac;\n+ /*\n+ * Routines expanded with multiple structures reference \"hi\" and \"lo\"\n+ * depending on the operation. In FloatParts64, \"hi\" and \"lo\" are\n+ * both the same word and aliased here.\n+ */\n+ uint64_t frac_hi;\n+ uint64_t frac_lo;\n+ };\n+} FloatParts64;\n+\n+typedef struct {\n+ FloatClass cls;\n+ bool sign;\n+ int32_t exp;\n+ uint64_t frac_hi;\n+ uint64_t frac_lo;\n+} FloatParts128;\n+\n+#endif\ndiff --git a/fpu/softfloat.c b/fpu/softfloat.c\nindex 8c4263bfe6..cd75df3160 100644\n--- a/fpu/softfloat.c\n+++ b/fpu/softfloat.c\n@@ -83,6 +83,7 @@ this code that are retained.\n #include \n #include \"qemu/bitops.h\"\n #include \"fpu/softfloat.h\"\n+#include \"fpu/softfloat-parts.h\"\n \n /* We only need stdlib for abort() */\n \n@@ -396,39 +397,6 @@ float64_gen2(float64 xa, float64 xb, float_status *s,\n return soft(ua.s, ub.s, s);\n }\n \n-/*\n- * Classify a floating point number. Everything above float_class_qnan\n- * is a NaN so cls >= float_class_qnan is any NaN.\n- *\n- * Note that we canonicalize denormals, so most code should treat\n- * class_normal and class_denormal identically.\n- */\n-\n-typedef enum __attribute__ ((__packed__)) {\n- float_class_unclassified,\n- float_class_zero,\n- float_class_normal,\n- float_class_denormal, /* input was a non-squashed denormal */\n- float_class_inf,\n- float_class_qnan, /* all NaNs from here */\n- float_class_snan,\n-} FloatClass;\n-\n-#define float_cmask(bit) (1u << (bit))\n-\n-enum {\n- float_cmask_zero = float_cmask(float_class_zero),\n- float_cmask_normal = float_cmask(float_class_normal),\n- float_cmask_denormal = float_cmask(float_class_denormal),\n- float_cmask_inf = float_cmask(float_class_inf),\n- float_cmask_qnan = float_cmask(float_class_qnan),\n- float_cmask_snan = float_cmask(float_class_snan),\n-\n- float_cmask_infzero = float_cmask_zero | float_cmask_inf,\n- float_cmask_anynan = float_cmask_qnan | float_cmask_snan,\n- float_cmask_anynorm = float_cmask_normal | float_cmask_denormal,\n-};\n-\n /* Flags for parts_minmax. */\n enum {\n /* Set for minimum; clear for maximum. */\n@@ -474,40 +442,7 @@ static inline bool is_anynorm(FloatClass c)\n return float_cmask(c) & float_cmask_anynorm;\n }\n \n-/*\n- * Structure holding all of the decomposed parts of a float.\n- * The exponent is unbiased and the fraction is normalized.\n- *\n- * The fraction words are stored in big-endian word ordering,\n- * so that truncation from a larger format to a smaller format\n- * can be done simply by ignoring subsequent elements.\n- */\n-\n-typedef struct {\n- FloatClass cls;\n- bool sign;\n- int32_t exp;\n- union {\n- /* Routines that know the structure may reference the singular name. */\n- uint64_t frac;\n- /*\n- * Routines expanded with multiple structures reference \"hi\" and \"lo\"\n- * depending on the operation. In FloatParts64, \"hi\" and \"lo\" are\n- * both the same word and aliased here.\n- */\n- uint64_t frac_hi;\n- uint64_t frac_lo;\n- };\n-} FloatParts64;\n-\n-typedef struct {\n- FloatClass cls;\n- bool sign;\n- int32_t exp;\n- uint64_t frac_hi;\n- uint64_t frac_lo;\n-} FloatParts128;\n-\n+/* FloatParts256 is entirely internal, for parts128_mul* */\n typedef struct {\n FloatClass cls;\n bool sign;\n","prefixes":["v2","09/40"]}