{"id":2230681,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230681/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430000524.56046-26-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260430000524.56046-26-richard.henderson@linaro.org>","date":"2026-04-30T00:05:08","name":"[v2,25/40] fpu: Reorganize partsN(muladd)","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"b40f8973e3854ae649e6bec67db8194dc9f0d084","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.1/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430000524.56046-26-richard.henderson@linaro.org/mbox/","series":[{"id":502170,"url":"http://patchwork.ozlabs.org/api/1.1/series/502170/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502170","date":"2026-04-30T00:04:48","name":"fpu: Export some internals for targets","version":2,"mbox":"http://patchwork.ozlabs.org/series/502170/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230681/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230681/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=gRVLtQQO;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5ZHm2zQmz1yHZ\n\tfor ; Thu, 30 Apr 2026 10:07:48 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wIEwL-0001L4-Bn; Wed, 29 Apr 2026 20:07:37 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wIEvE-0007sW-PW\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:06:30 -0400","from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wIEvC-0001sm-Sz\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:06:28 -0400","by mail-pf1-x42a.google.com with SMTP id\n d2e1a72fcca58-82d0b68837aso184920b3a.2\n for ; Wed, 29 Apr 2026 17:06:26 -0700 (PDT)","from stoup.. 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","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Check the likely case of normal product and normal or\nzero addend first; shift NaN and infinity detection down;\nend with zero product + addend.\n\nSigned-off-by: Richard Henderson \n---\n fpu/softfloat-parts.c.inc | 155 +++++++++++++++++---------------------\n 1 file changed, 70 insertions(+), 85 deletions(-)","diff":"diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc\nindex b8baaf1e76..77465cce6e 100644\n--- a/fpu/softfloat-parts.c.inc\n+++ b/fpu/softfloat-parts.c.inc\n@@ -683,11 +683,47 @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b,\n FloatPartsN *c,\n int flags, float_status *s)\n {\n- int ab_mask, abc_mask;\n- FloatPartsW p_widen, c_widen;\n+ int ab_mask = float_cmask(a->cls) | float_cmask(b->cls);\n+ int c_mask = float_cmask(c->cls);\n+ int abc_mask = ab_mask | c_mask;\n+ bool c_sign = c->sign ^ !!(flags & float_muladd_negate_c);\n+ bool p_sign = a->sign ^ b->sign ^ !!(flags & float_muladd_negate_product);\n \n- ab_mask = float_cmask(a->cls) | float_cmask(b->cls);\n- abc_mask = float_cmask(c->cls) | ab_mask;\n+ /*\n+ * The \"likely\" case is A and B normal, so that the product is normal,\n+ * and C normal or zero so that the result is normal.\n+ */\n+ int likely_mask = ab_mask | (c_mask & ~float_cmask_zero);\n+ if (likely(cmask_is_only_normals(likely_mask))) {\n+ record_denormals_used(abc_mask, s);\n+\n+ /* Perform the multiplication step. */\n+ FloatPartsW p_widen = { .sign = p_sign, .exp = a->exp + b->exp + 1 };\n+ fracN(mulw)(&p_widen, a, b);\n+ if (!(p_widen.frac_hi & DECOMPOSED_IMPLICIT_BIT)) {\n+ fracW(add)(&p_widen, &p_widen, &p_widen);\n+ p_widen.exp -= 1;\n+ }\n+\n+ /* Perform the addition step. */\n+ if (!(c_mask & float_cmask_zero)) {\n+ /* Zero-extend C to less significant bits. */\n+ FloatPartsW c_widen = { .sign = c_sign, .exp = c->exp };\n+ fracN(widen)(&c_widen, c);\n+\n+ if (p_sign == c_sign) {\n+ partsW(add_normal)(&p_widen, &c_widen);\n+ } else if (!partsW(sub_normal)(&p_widen, &c_widen)) {\n+ goto return_sub_zero;\n+ }\n+ }\n+\n+ /* Narrow with sticky bit, for proper rounding later. */\n+ fracN(truncjam)(a, &p_widen);\n+ a->sign = p_widen.sign;\n+ a->exp = p_widen.exp;\n+ return a;\n+ }\n \n /*\n * It is implementation-defined whether the cases of (0,inf,qnan)\n@@ -700,97 +736,46 @@ static FloatPartsN *partsN(muladd)(FloatPartsN *a, FloatPartsN *b,\n return a;\n }\n \n- if (flags & float_muladd_negate_c) {\n- c->sign ^= 1;\n+ if (unlikely(ab_mask == float_cmask_infzero)) {\n+ /* Inf * Zero == NaN */\n+ float_raise(float_flag_invalid | float_flag_invalid_imz, s);\n+ goto d_nan;\n }\n \n- /* Compute the sign of the product into A. */\n- a->sign ^= b->sign;\n- if (flags & float_muladd_negate_product) {\n- a->sign ^= 1;\n- }\n-\n- if (unlikely(!cmask_is_only_normals(ab_mask))) {\n- if (unlikely(ab_mask == float_cmask_infzero)) {\n- float_raise(float_flag_invalid | float_flag_invalid_imz, s);\n+ if (unlikely(ab_mask & float_cmask_inf)) {\n+ if ((c_mask & float_cmask_inf) && p_sign != c_sign) {\n+ /* Inf - Inf == NaN */\n+ float_raise(float_flag_invalid | float_flag_invalid_isi, s);\n goto d_nan;\n }\n-\n- if (ab_mask & float_cmask_inf) {\n- if (c->cls == float_class_inf && a->sign != c->sign) {\n- float_raise(float_flag_invalid | float_flag_invalid_isi, s);\n- goto d_nan;\n- }\n- goto return_inf;\n- }\n-\n- g_assert(ab_mask & float_cmask_zero);\n- if (is_anynorm(c->cls)) {\n- *a = *c;\n- goto finish_sign;\n- }\n- if (c->cls == float_class_zero) {\n- if (flags & float_muladd_suppress_add_product_zero) {\n- a->sign = c->sign;\n- } else if (a->sign != c->sign) {\n- goto return_sub_zero;\n- }\n- goto return_zero;\n- }\n- g_assert(c->cls == float_class_inf);\n+ /* Inf + C == Inf */\n+ record_denormals_used(abc_mask, s);\n+ a->sign = p_sign;\n+ a->cls = float_class_inf;\n+ return a;\n }\n-\n- if (unlikely(c->cls == float_class_inf)) {\n- a->sign = c->sign;\n- goto return_inf;\n- }\n-\n- /* Perform the multiplication step. */\n- p_widen.sign = a->sign;\n- p_widen.exp = a->exp + b->exp + 1;\n- fracN(mulw)(&p_widen, a, b);\n- if (!(p_widen.frac_hi & DECOMPOSED_IMPLICIT_BIT)) {\n- fracW(add)(&p_widen, &p_widen, &p_widen);\n- p_widen.exp -= 1;\n- }\n-\n- /* Perform the addition step. */\n- if (c->cls != float_class_zero) {\n- /* Zero-extend C to less significant bits. */\n- fracN(widen)(&c_widen, c);\n- c_widen.exp = c->exp;\n-\n- if (a->sign == c->sign) {\n- partsW(add_normal)(&p_widen, &c_widen);\n- } else if (!partsW(sub_normal)(&p_widen, &c_widen)) {\n- goto return_sub_zero;\n- }\n- }\n-\n- /* Narrow with sticky bit, for proper rounding later. */\n- fracN(truncjam)(a, &p_widen);\n- a->sign = p_widen.sign;\n- a->exp = p_widen.exp;\n-\n- finish_sign:\n- /*\n- * All result types except for \"return the default NaN\n- * because this is an Invalid Operation\" go through here;\n- * this matches the set of cases where we consumed a\n- * denormal input.\n- */\n record_denormals_used(abc_mask, s);\n- return a;\n+\n+ /* Only remaining case is zero product. */\n+ assert(ab_mask & float_cmask_zero);\n+\n+ /*\n+ * 0 + C == C,\n+ * except for 0 - 0, which needs special rounding,\n+ * except for when we want to suppress this addition step.\n+ */\n+ if (!(c_mask & float_cmask_zero)\n+ || p_sign == c_sign\n+ || (flags & float_muladd_suppress_add_product_zero)) {\n+ c->sign = c_sign;\n+ return c;\n+ }\n \n return_sub_zero:\n+ /* 0 - 0 == -0 for round_down, +0 otherwise. */\n a->sign = s->float_rounding_mode == float_round_down;\n- return_zero:\n a->cls = float_class_zero;\n- goto finish_sign;\n-\n- return_inf:\n- a->cls = float_class_inf;\n- goto finish_sign;\n+ return a;\n \n d_nan:\n *a = partsN(default_nan)(s);\n","prefixes":["v2","25/40"]}