{"id":2230680,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230680/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430000524.56046-37-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260430000524.56046-37-richard.henderson@linaro.org>","date":"2026-04-30T00:05:19","name":"[v2,36/40] target/arm: Use FloatParts64 in f16_dotadd","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"74dc5716eb626aa68745ed2baa8844141c095988","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.1/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430000524.56046-37-richard.henderson@linaro.org/mbox/","series":[{"id":502170,"url":"http://patchwork.ozlabs.org/api/1.1/series/502170/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502170","date":"2026-04-30T00:04:48","name":"fpu: Export some internals for targets","version":2,"mbox":"http://patchwork.ozlabs.org/series/502170/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230680/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230680/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=EMAoDgMz;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5ZHl0HnMz1yJr\n\tfor ; Thu, 30 Apr 2026 10:07:47 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wIEwJ-00015U-Ma; Wed, 29 Apr 2026 20:07:35 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wIEvh-0008F8-FT\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:06:58 -0400","from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wIEvd-0001zp-5i\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:06:55 -0400","by mail-pf1-x435.google.com with SMTP id\n d2e1a72fcca58-82f351ca23cso157622b3a.2\n for ; Wed, 29 Apr 2026 17:06:52 -0700 (PDT)","from stoup.. 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helo=mail-pf1-x435.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Use softfloat-parts.h so that we can more naturally\nperform the required operations witha single rounding step.\nThis happens to also simplify the NaN detection step.\n\nSigned-off-by: Richard Henderson \n---\n target/arm/tcg/sme_helper.c | 96 ++++++++++++++++---------------------\n 1 file changed, 40 insertions(+), 56 deletions(-)","diff":"diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c\nindex 0702a1b129..16b96890cc 100644\n--- a/target/arm/tcg/sme_helper.c\n+++ b/target/arm/tcg/sme_helper.c\n@@ -27,6 +27,7 @@\n #include \"accel/tcg/helper-retaddr.h\"\n #include \"qemu/int128.h\"\n #include \"fpu/softfloat.h\"\n+#include \"fpu/softfloat-parts.h\"\n #include \"vec_internal.h\"\n #include \"sve_ldst_internal.h\"\n \n@@ -1227,18 +1228,15 @@ static inline uint32_t bf16mop_ah_neg_adj_pair(uint32_t pair, uint32_t pg)\n }\n \n static float32 f16_dotadd(float32 sum, uint32_t e1, uint32_t e2,\n- float_status *s_f16, float_status *s_std,\n- float_status *s_odd)\n+ float_status *s_f16, float_status *s_std)\n {\n /*\n- * We need three different float_status for different parts of this\n+ * We need two different float_status for different parts of this\n * operation:\n * - the input conversion of the float16 values must use the\n * f16-specific float_status, so that the FPCR.FZ16 control is applied\n * - operations on float32 including the final accumulation must use\n * the normal float_status, so that FPCR.FZ is applied\n- * - we have pre-set-up copy of s_std which is set to round-to-odd,\n- * for the multiply (see below)\n */\n float16 h1r = e1 & 0xffff;\n float16 h1c = e1 >> 16;\n@@ -1246,48 +1244,49 @@ static float32 f16_dotadd(float32 sum, uint32_t e1, uint32_t e2,\n float16 h2c = e2 >> 16;\n float32 t32;\n \n+ FloatParts64 p1r = float16_unpack_canonical(h1r, s_f16);\n+ FloatParts64 p1c = float16_unpack_canonical(h1c, s_f16);\n+ FloatParts64 p2r = float16_unpack_canonical(h2r, s_f16);\n+ FloatParts64 p2c = float16_unpack_canonical(h2c, s_f16);\n+\n+ int all_mask = (float_cmask(p1r.cls) | float_cmask(p1c.cls) |\n+ float_cmask(p1r.cls) | float_cmask(p1c.cls));\n+\n /* C.f. FPProcessNaNs4 */\n- if (float16_is_any_nan(h1r) || float16_is_any_nan(h1c) ||\n- float16_is_any_nan(h2r) || float16_is_any_nan(h2c)) {\n+ if (unlikely(all_mask & float_cmask_anynan)) {\n float16 t16;\n \n- if (float16_is_signaling_nan(h1r, s_f16)) {\n- t16 = h1r;\n- } else if (float16_is_signaling_nan(h1c, s_f16)) {\n- t16 = h1c;\n- } else if (float16_is_signaling_nan(h2r, s_f16)) {\n- t16 = h2r;\n- } else if (float16_is_signaling_nan(h2c, s_f16)) {\n- t16 = h2c;\n- } else if (float16_is_any_nan(h1r)) {\n- t16 = h1r;\n- } else if (float16_is_any_nan(h1c)) {\n- t16 = h1c;\n- } else if (float16_is_any_nan(h2r)) {\n- t16 = h2r;\n+ if (unlikely(all_mask & float_cmask_snan)) {\n+ if (p1r.cls == float_class_snan) {\n+ t16 = h1r;\n+ } else if (p1c.cls == float_class_snan) {\n+ t16 = h1c;\n+ } else if (p2r.cls == float_class_snan) {\n+ t16 = h2r;\n+ } else {\n+ t16 = h2c;\n+ }\n } else {\n- t16 = h2c;\n+ if (p1r.cls == float_class_qnan) {\n+ t16 = h1r;\n+ } else if (p1c.cls == float_class_qnan) {\n+ t16 = h1c;\n+ } else if (p2r.cls == float_class_qnan) {\n+ t16 = h2r;\n+ } else {\n+ t16 = h2c;\n+ }\n }\n t32 = float16_to_float32(t16, true, s_f16);\n } else {\n- float64 e1r = float16_to_float64(h1r, true, s_f16);\n- float64 e1c = float16_to_float64(h1c, true, s_f16);\n- float64 e2r = float16_to_float64(h2r, true, s_f16);\n- float64 e2c = float16_to_float64(h2c, true, s_f16);\n- float64 t64;\n-\n /*\n * The ARM pseudocode function FPDot performs both multiplies\n- * and the add with a single rounding operation. Emulate this\n- * by performing the first multiply in round-to-odd, then doing\n- * the second multiply as fused multiply-add, and rounding to\n- * float32 all in one step.\n+ * and the add with a single rounding operation.\n */\n- t64 = float64_mul(e1r, e2r, s_odd);\n- t64 = float64r32_muladd(e1c, e2c, t64, 0, s_std);\n+ FloatParts64 tmp = parts64_mul(&p1r, &p2r, s_std);\n+ tmp = parts64_muladd(&p1c, &p2c, &tmp, 0, s_std);\n \n- /* This conversion is exact, because we've already rounded. */\n- t32 = float64_to_float32(t64, s_std);\n+ t32 = float32_round_pack_canonical(&tmp, s_std);\n }\n \n /* The final accumulation step is not fused. */\n@@ -1299,9 +1298,6 @@ static void do_fmopa_w_h(void *vza, void *vzn, void *vzm, uint16_t *pn,\n uint32_t negx, bool ah_neg)\n {\n intptr_t row, col, oprsz = simd_maxsz(desc);\n- float_status fpst_odd = env->vfp.fp_status[FPST_ZA];\n-\n- set_float_rounding_mode(float_round_to_odd, &fpst_odd);\n \n for (row = 0; row < oprsz; ) {\n uint16_t prow = pn[H2(row >> 4)];\n@@ -1325,8 +1321,7 @@ static void do_fmopa_w_h(void *vza, void *vzn, void *vzm, uint16_t *pn,\n m = f16mop_adj_pair(m, pcol, 0);\n *a = f16_dotadd(*a, n, m,\n &env->vfp.fp_status[FPST_ZA_F16],\n- &env->vfp.fp_status[FPST_ZA],\n- &fpst_odd);\n+ &env->vfp.fp_status[FPST_ZA]);\n }\n col += 4;\n pcol >>= 4;\n@@ -1363,15 +1358,12 @@ void HELPER(sme2_fdot_h)(void *vd, void *vn, void *vm, void *va,\n bool za = extract32(desc, SIMD_DATA_SHIFT, 1);\n float_status *fpst_std = &env->vfp.fp_status[za ? FPST_ZA : FPST_A64];\n float_status *fpst_f16 = &env->vfp.fp_status[za ? FPST_ZA_F16 : FPST_A64_F16];\n- float_status fpst_odd = *fpst_std;\n float32 *d = vd, *a = va;\n uint32_t *n = vn, *m = vm;\n \n- set_float_rounding_mode(float_round_to_odd, &fpst_odd);\n-\n for (i = 0; i < oprsz / sizeof(float32); ++i) {\n d[H4(i)] = f16_dotadd(a[H4(i)], n[H4(i)], m[H4(i)],\n- fpst_f16, fpst_std, &fpst_odd);\n+ fpst_f16, fpst_std);\n }\n }\n \n@@ -1385,17 +1377,14 @@ void HELPER(sme2_fdot_idx_h)(void *vd, void *vn, void *vm, void *va,\n bool za = extract32(desc, SIMD_DATA_SHIFT + 2, 1);\n float_status *fpst_std = &env->vfp.fp_status[za ? FPST_ZA : FPST_A64];\n float_status *fpst_f16 = &env->vfp.fp_status[za ? FPST_ZA_F16 : FPST_A64_F16];\n- float_status fpst_odd = *fpst_std;\n float32 *d = vd, *a = va;\n uint32_t *n = vn, *m = (uint32_t *)vm + H4(idx);\n \n- set_float_rounding_mode(float_round_to_odd, &fpst_odd);\n-\n for (i = 0; i < elements; i += eltspersegment) {\n uint32_t mm = m[i];\n for (j = 0; j < eltspersegment; ++j) {\n d[H4(i + j)] = f16_dotadd(a[H4(i + j)], n[H4(i + j)], mm,\n- fpst_f16, fpst_std, &fpst_odd);\n+ fpst_f16, fpst_std);\n }\n }\n }\n@@ -1408,24 +1397,19 @@ void HELPER(sme2_fvdot_idx_h)(void *vd, void *vn, void *vm, void *va,\n intptr_t eltspersegment = MIN(4, elements);\n int idx = extract32(desc, SIMD_DATA_SHIFT, 2);\n int sel = extract32(desc, SIMD_DATA_SHIFT + 2, 1);\n- float_status fpst_odd, *fpst_std, *fpst_f16;\n float32 *d = vd, *a = va;\n uint16_t *n0 = vn;\n uint16_t *n1 = vn + sizeof(ARMVectorReg);\n uint32_t *m = (uint32_t *)vm + H4(idx);\n \n- fpst_std = &env->vfp.fp_status[FPST_ZA];\n- fpst_f16 = &env->vfp.fp_status[FPST_ZA_F16];\n- fpst_odd = *fpst_std;\n- set_float_rounding_mode(float_round_to_odd, &fpst_odd);\n-\n for (i = 0; i < elements; i += eltspersegment) {\n uint32_t mm = m[i];\n for (j = 0; j < eltspersegment; ++j) {\n uint32_t nn = (n0[H2(2 * (i + j) + sel)])\n | (n1[H2(2 * (i + j) + sel)] << 16);\n d[i + H4(j)] = f16_dotadd(a[i + H4(j)], nn, mm,\n- fpst_f16, fpst_std, &fpst_odd);\n+ &env->vfp.fp_status[FPST_ZA_F16],\n+ &env->vfp.fp_status[FPST_ZA]);\n }\n }\n }\n","prefixes":["v2","36/40"]}