{"id":2230591,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230591/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429220155.24546-2-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260429220155.24546-2-richard.henderson@linaro.org>","date":"2026-04-29T22:01:53","name":"[PULL,1/3] tcg/aarch64/tcg-target.c.inc: Replacement of I3XXX names","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"4883142cf9a8484f0caf75793dc4075e1703d5be","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.1/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429220155.24546-2-richard.henderson@linaro.org/mbox/","series":[{"id":502159,"url":"http://patchwork.ozlabs.org/api/1.1/series/502159/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502159","date":"2026-04-29T22:01:52","name":"[PULL,1/3] tcg/aarch64/tcg-target.c.inc: Replacement of I3XXX names","version":1,"mbox":"http://patchwork.ozlabs.org/series/502159/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230591/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230591/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=iyRH3Z2A;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5WWt0Hv3z1yGq\n\tfor ; Thu, 30 Apr 2026 08:03:04 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wICz0-0002Sx-B3; Wed, 29 Apr 2026 18:02:14 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wICyz-0002SP-3h\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 18:02:13 -0400","from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wICyt-0006YJ-Uj\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 18:02:12 -0400","by mail-pl1-x62c.google.com with SMTP id\n d9443c01a7336-2ad9f316d68so1017635ad.2\n for ; Wed, 29 Apr 2026 15:02:07 -0700 (PDT)","from stoup.. ([180.233.125.15]) by smtp.gmail.com with ESMTPSA id\n d9443c01a7336-2b98895ca58sm32162095ad.60.2026.04.29.15.02.01\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Wed, 29 Apr 2026 15:02:04 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1777500126; x=1778104926; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=Au0FBLPtKxqvVdNnvS2hkGyt2QlfF00euWXooPR/VnY=;\n b=iyRH3Z2AyoOO6bcqu+3y4AMpckihOpg8HMVP62KLcdOGZ7fEX7nWCDXlAZJ30VlAV3\n gFh/ssUX3r/1Ir5PeVNDRIixvct1S4Ezu8jKwLyd7g49TFYZcBMtuZGLCaAn8tha1vNH\n H6lmBagU6VLrVD0qg4/yhPpO39hlEpWDA/5ZfTPsN6QTLE+mdeUcUYhs/Jo/lTangBsJ\n 6l6Y/e4Qn2Mw5PN1Zu0ElYL8CBG8AlvilspCtI3OabMyttiIBWq4yaFjE/xE0SOYAb7s\n NUsoy+9vuruvHzWujyKrtgFHfKkg40EeOF1NXR2SGH+b1POyzw54Mw7hG9fFyj6WuQ35\n 5IaA==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1777500126; x=1778104926;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=Au0FBLPtKxqvVdNnvS2hkGyt2QlfF00euWXooPR/VnY=;\n b=KSy8qP0ujnT84iRQsu6LIf47+SV0SkwBFXLFhs3tadwpRvCMn4XwW1e94LbBCoA3/N\n BVVANDwM70M0ozg7yL9Ikvu0HDs+lu2lkZPkeTUZ+q34LVUeHL6vVexIUZB2jY9Ey9Ru\n So6aQKFrWU+CTj5GkNEy7VZeQHj2Qw9pGEyDps1ThMpBhpgT2ywjESwlMmvxXs3oYu1Q\n 8Y6A6oP2zAaELxS1GteiEV3+BQvPXzAiochkgqTe0yao1WdR6LKNkSkbZCrv2Dc/+m4O\n ieBGQ29sWSzSj9ae7opbEciTZ2PSjUTi7M08MkSzAPvuZoJgceBSCjGUl0UPgkdoonmo\n ulrg==","X-Gm-Message-State":"AOJu0YyLZpijWEm+oxKhZe0U2CMsq1rSLXUGWJk6g+6Zfz2AZUWKTVbD\n L5k4hMxTJ7s8+jt7tmbtjhNvOzx1BNT3AzND/SIVRod+3ruIx8+79XTze+pVNV7pD9TgapsiDr2\n 5mqD10S0=","X-Gm-Gg":"AeBDievKCk1z1fe8RpNqgy9Eyk/IqhAySGXtyhp8sNN1QRcpN0B6giqYCOU2t5xcX5f\n k32/HWr2SGUNYgywcoiwZpfngxsWf+fe3ULkywMm0nqmf3IVu2Tz0VjrPXAn5WLsRL/7ybCZVMJ\n 4fLe004rLcvknl50kMvBQS+Q/KzOa+rG1qKYpURZzB8gcCaF9N9C08KNJf5VbQM7550LTm6ZXzX\n /rLZ4FVxltMH+SMiyF6LCLTO9IXmAj6aziAhfGuofYSGrIiUpr8ztaw3jK4TWU7MLIj7Ns5jrAt\n 8a89TCjTK1LpFQLv8/stw1bvl7gAfHC5x7u9mkBUAwobbcepotSte/oG/smDXeTqa1W3JUoo+NV\n vozElXOvRhz8R+DlP9Cb2VLTmfCfJORo4pWmuoR4iX4Dx2oyKKlPtQSx68YP4Nv78M5Tq8xPenk\n NnCGI+X4hz9u3fMbQriqSj/3s6DLTGpCvQQxXBwfWI","X-Received":"by 2002:a17:902:9892:b0:2b0:ccad:de1a with SMTP id\n d9443c01a7336-2b9a2503c51mr1389905ad.30.1777500124868;\n Wed, 29 Apr 2026 15:02:04 -0700 (PDT)","From":"Richard Henderson ","To":"qemu-devel@nongnu.org","Cc":"stefanha@redhat.com,\n\tJim MacArthur ","Subject":"[PULL 1/3] tcg/aarch64/tcg-target.c.inc: Replacement of I3XXX names","Date":"Thu, 30 Apr 2026 08:01:53 +1000","Message-ID":"<20260429220155.24546-2-richard.henderson@linaro.org>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260429220155.24546-1-richard.henderson@linaro.org>","References":"<20260429220155.24546-1-richard.henderson@linaro.org>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::62c;\n envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Jim MacArthur \n\nMechanical replacement of instruction format names of the form 'I3206'\netc with more useful names. Where possible, names from a64.decode are\nused. Includes manual fixes to whitespace.\n\nSigned-off-by: Jim MacArthur \nReviewed-by: Richard Henderson \nSigned-off-by: Richard Henderson \nMessage-ID: <20260402-aarch64-tcg-instruction-format-rename2-v1-1-0998a08a515c@linaro.org>\n---\n tcg/aarch64/tcg-target.c.inc | 960 ++++++++++++++++++-----------------\n 1 file changed, 489 insertions(+), 471 deletions(-)","diff":"diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc\nindex caf79c742d..23d96a7960 100644\n--- a/tcg/aarch64/tcg-target.c.inc\n+++ b/tcg/aarch64/tcg-target.c.inc\n@@ -399,256 +399,256 @@ typedef enum {\n instruction group is described. */\n typedef enum {\n /* Compare and branch (immediate). */\n- I3201_CBZ = 0x34000000,\n- I3201_CBNZ = 0x35000000,\n+ Icbz_CBZ = 0x34000000,\n+ Icbz_CBNZ = 0x35000000,\n \n /* Conditional branch (immediate). */\n- I3202_B_C = 0x54000000,\n+ Ibcond_imm_B_C = 0x54000000,\n \n /* Test and branch (immediate). */\n- I3205_TBZ = 0x36000000,\n- I3205_TBNZ = 0x37000000,\n+ Itbz_TBZ = 0x36000000,\n+ Itbz_TBNZ = 0x37000000,\n \n /* Unconditional branch (immediate). */\n- I3206_B = 0x14000000,\n- I3206_BL = 0x94000000,\n+ Ibranch_B = 0x14000000,\n+ Ibranch_BL = 0x94000000,\n \n /* Unconditional branch (register). */\n- I3207_BR = 0xd61f0000,\n- I3207_BLR = 0xd63f0000,\n- I3207_RET = 0xd65f0000,\n+ Ibcond_reg_BR = 0xd61f0000,\n+ Ibcond_reg_BLR = 0xd63f0000,\n+ Ibcond_reg_RET = 0xd65f0000,\n \n /* AdvSIMD load/store single structure. */\n- I3303_LD1R = 0x0d40c000,\n+ Isimd_loadrep_LD1R = 0x0d40c000,\n \n /* Load literal for loading the address at pc-relative offset */\n- I3305_LDR = 0x58000000,\n- I3305_LDR_v64 = 0x5c000000,\n- I3305_LDR_v128 = 0x9c000000,\n+ Ildlit_LDR = 0x58000000,\n+ Ildlit_LDR_v64 = 0x5c000000,\n+ Ildlit_LDR_v128 = 0x9c000000,\n \n /* Load/store exclusive. */\n- I3306_LDXP = 0xc8600000,\n- I3306_STXP = 0xc8200000,\n+ Istxp_LDXP = 0xc8600000,\n+ Istxp_STXP = 0xc8200000,\n \n /* Load/store register. Described here as 3.3.12, but the helper\n that emits them can transform to 3.3.10 or 3.3.13. */\n- I3312_STRB = 0x38000000 | LDST_ST << 22 | MO_8 << 30,\n- I3312_STRH = 0x38000000 | LDST_ST << 22 | MO_16 << 30,\n- I3312_STRW = 0x38000000 | LDST_ST << 22 | MO_32 << 30,\n- I3312_STRX = 0x38000000 | LDST_ST << 22 | MO_64 << 30,\n+ Ildst_imm_STRB = 0x38000000 | LDST_ST << 22 | MO_8 << 30,\n+ Ildst_imm_STRH = 0x38000000 | LDST_ST << 22 | MO_16 << 30,\n+ Ildst_imm_STRW = 0x38000000 | LDST_ST << 22 | MO_32 << 30,\n+ Ildst_imm_STRX = 0x38000000 | LDST_ST << 22 | MO_64 << 30,\n \n- I3312_LDRB = 0x38000000 | LDST_LD << 22 | MO_8 << 30,\n- I3312_LDRH = 0x38000000 | LDST_LD << 22 | MO_16 << 30,\n- I3312_LDRW = 0x38000000 | LDST_LD << 22 | MO_32 << 30,\n- I3312_LDRX = 0x38000000 | LDST_LD << 22 | MO_64 << 30,\n+ Ildst_imm_LDRB = 0x38000000 | LDST_LD << 22 | MO_8 << 30,\n+ Ildst_imm_LDRH = 0x38000000 | LDST_LD << 22 | MO_16 << 30,\n+ Ildst_imm_LDRW = 0x38000000 | LDST_LD << 22 | MO_32 << 30,\n+ Ildst_imm_LDRX = 0x38000000 | LDST_LD << 22 | MO_64 << 30,\n \n- I3312_LDRSBW = 0x38000000 | LDST_LD_S_W << 22 | MO_8 << 30,\n- I3312_LDRSHW = 0x38000000 | LDST_LD_S_W << 22 | MO_16 << 30,\n+ Ildst_imm_LDRSBW = 0x38000000 | LDST_LD_S_W << 22 | MO_8 << 30,\n+ Ildst_imm_LDRSHW = 0x38000000 | LDST_LD_S_W << 22 | MO_16 << 30,\n \n- I3312_LDRSBX = 0x38000000 | LDST_LD_S_X << 22 | MO_8 << 30,\n- I3312_LDRSHX = 0x38000000 | LDST_LD_S_X << 22 | MO_16 << 30,\n- I3312_LDRSWX = 0x38000000 | LDST_LD_S_X << 22 | MO_32 << 30,\n+ Ildst_imm_LDRSBX = 0x38000000 | LDST_LD_S_X << 22 | MO_8 << 30,\n+ Ildst_imm_LDRSHX = 0x38000000 | LDST_LD_S_X << 22 | MO_16 << 30,\n+ Ildst_imm_LDRSWX = 0x38000000 | LDST_LD_S_X << 22 | MO_32 << 30,\n \n- I3312_LDRVS = 0x3c000000 | LDST_LD << 22 | MO_32 << 30,\n- I3312_STRVS = 0x3c000000 | LDST_ST << 22 | MO_32 << 30,\n+ Ildst_imm_LDRVS = 0x3c000000 | LDST_LD << 22 | MO_32 << 30,\n+ Ildst_imm_STRVS = 0x3c000000 | LDST_ST << 22 | MO_32 << 30,\n \n- I3312_LDRVD = 0x3c000000 | LDST_LD << 22 | MO_64 << 30,\n- I3312_STRVD = 0x3c000000 | LDST_ST << 22 | MO_64 << 30,\n+ Ildst_imm_LDRVD = 0x3c000000 | LDST_LD << 22 | MO_64 << 30,\n+ Ildst_imm_STRVD = 0x3c000000 | LDST_ST << 22 | MO_64 << 30,\n \n- I3312_LDRVQ = 0x3c000000 | 3 << 22 | 0 << 30,\n- I3312_STRVQ = 0x3c000000 | 2 << 22 | 0 << 30,\n+ Ildst_imm_LDRVQ = 0x3c000000 | 3 << 22 | 0 << 30,\n+ Ildst_imm_STRVQ = 0x3c000000 | 2 << 22 | 0 << 30,\n \n- I3312_TO_I3310 = 0x00200800,\n- I3312_TO_I3313 = 0x01000000,\n+ Ildst_imm_TO_I3310 = 0x00200800,\n+ Ildst_imm_TO_I3313 = 0x01000000,\n \n /* Load/store register pair instructions. */\n- I3314_LDP = 0x28400000,\n- I3314_STP = 0x28000000,\n+ Ildstpair_LDP = 0x28400000,\n+ Ildstpair_STP = 0x28000000,\n \n /* Add/subtract immediate instructions. */\n- I3401_ADDI = 0x11000000,\n- I3401_ADDSI = 0x31000000,\n- I3401_SUBI = 0x51000000,\n- I3401_SUBSI = 0x71000000,\n+ Iaddsub_imm_ADDI = 0x11000000,\n+ Iaddsub_imm_ADDSI = 0x31000000,\n+ Iaddsub_imm_SUBI = 0x51000000,\n+ Iaddsub_imm_SUBSI = 0x71000000,\n \n /* Bitfield instructions. */\n- I3402_BFM = 0x33000000,\n- I3402_SBFM = 0x13000000,\n- I3402_UBFM = 0x53000000,\n+ Ibitfield_BFM = 0x33000000,\n+ Ibitfield_SBFM = 0x13000000,\n+ Ibitfield_UBFM = 0x53000000,\n \n /* Extract instruction. */\n- I3403_EXTR = 0x13800000,\n+ Iextract_EXTR = 0x13800000,\n \n /* Logical immediate instructions. */\n- I3404_ANDI = 0x12000000,\n- I3404_ORRI = 0x32000000,\n- I3404_EORI = 0x52000000,\n- I3404_ANDSI = 0x72000000,\n+ Ilogic_imm_ANDI = 0x12000000,\n+ Ilogic_imm_ORRI = 0x32000000,\n+ Ilogic_imm_EORI = 0x52000000,\n+ Ilogic_imm_ANDSI = 0x72000000,\n \n /* Move wide immediate instructions. */\n- I3405_MOVN = 0x12800000,\n- I3405_MOVZ = 0x52800000,\n- I3405_MOVK = 0x72800000,\n+ Imovw_MOVN = 0x12800000,\n+ Imovw_MOVZ = 0x52800000,\n+ Imovw_MOVK = 0x72800000,\n \n /* PC relative addressing instructions. */\n- I3406_ADR = 0x10000000,\n- I3406_ADRP = 0x90000000,\n+ Ipcrel_ADR = 0x10000000,\n+ Ipcrel_ADRP = 0x90000000,\n \n /* Add/subtract extended register instructions. */\n- I3501_ADD = 0x0b200000,\n+ Iaddsub_ext_ADD = 0x0b200000,\n \n /* Add/subtract shifted register instructions (without a shift). */\n- I3502_ADD = 0x0b000000,\n- I3502_ADDS = 0x2b000000,\n- I3502_SUB = 0x4b000000,\n- I3502_SUBS = 0x6b000000,\n+ Iaddsub_shift_ADD = 0x0b000000,\n+ Iaddsub_shift_ADDS = 0x2b000000,\n+ Iaddsub_shift_SUB = 0x4b000000,\n+ Iaddsub_shift_SUBS = 0x6b000000,\n \n /* Add/subtract shifted register instructions (with a shift). */\n- I3502S_ADD_LSL = I3502_ADD,\n+ Iaddsub_realshift_ADD_LSL = Iaddsub_shift_ADD,\n \n /* Add/subtract with carry instructions. */\n- I3503_ADC = 0x1a000000,\n- I3503_ADCS = 0x3a000000,\n- I3503_SBC = 0x5a000000,\n- I3503_SBCS = 0x7a000000,\n+ Irrr_sf_ADC = 0x1a000000,\n+ Irrr_sf_ADCS = 0x3a000000,\n+ Irrr_sf_SBC = 0x5a000000,\n+ Irrr_sf_SBCS = 0x7a000000,\n \n /* Conditional select instructions. */\n- I3506_CSEL = 0x1a800000,\n- I3506_CSINC = 0x1a800400,\n- I3506_CSINV = 0x5a800000,\n- I3506_CSNEG = 0x5a800400,\n+ Icsel_CSEL = 0x1a800000,\n+ Icsel_CSINC = 0x1a800400,\n+ Icsel_CSINV = 0x5a800000,\n+ Icsel_CSNEG = 0x5a800400,\n \n /* Data-processing (1 source) instructions. */\n- I3507_CLZ = 0x5ac01000,\n- I3507_RBIT = 0x5ac00000,\n- I3507_REV = 0x5ac00000, /* + size << 10 */\n+ Irr_sf_CLZ = 0x5ac01000,\n+ Irr_sf_RBIT = 0x5ac00000,\n+ Irr_sf_REV = 0x5ac00000, /* + size << 10 */\n \n /* Data-processing (2 source) instructions. */\n- I3508_LSLV = 0x1ac02000,\n- I3508_LSRV = 0x1ac02400,\n- I3508_ASRV = 0x1ac02800,\n- I3508_RORV = 0x1ac02c00,\n- I3508_SMULH = 0x9b407c00,\n- I3508_UMULH = 0x9bc07c00,\n- I3508_UDIV = 0x1ac00800,\n- I3508_SDIV = 0x1ac00c00,\n+ Irrr_LSLV = 0x1ac02000,\n+ Irrr_LSRV = 0x1ac02400,\n+ Irrr_ASRV = 0x1ac02800,\n+ Irrr_RORV = 0x1ac02c00,\n+ Irrr_SMULH = 0x9b407c00,\n+ Irrr_UMULH = 0x9bc07c00,\n+ Irrr_UDIV = 0x1ac00800,\n+ Irrr_SDIV = 0x1ac00c00,\n \n /* Data-processing (3 source) instructions. */\n- I3509_MADD = 0x1b000000,\n- I3509_MSUB = 0x1b008000,\n+ Irrrr_MADD = 0x1b000000,\n+ Irrrr_MSUB = 0x1b008000,\n \n /* Logical shifted register instructions (without a shift). */\n- I3510_AND = 0x0a000000,\n- I3510_BIC = 0x0a200000,\n- I3510_ORR = 0x2a000000,\n- I3510_ORN = 0x2a200000,\n- I3510_EOR = 0x4a000000,\n- I3510_EON = 0x4a200000,\n- I3510_ANDS = 0x6a000000,\n+ Ilogic_shift_AND = 0x0a000000,\n+ Ilogic_shift_BIC = 0x0a200000,\n+ Ilogic_shift_ORR = 0x2a000000,\n+ Ilogic_shift_ORN = 0x2a200000,\n+ Ilogic_shift_EOR = 0x4a000000,\n+ Ilogic_shift_EON = 0x4a200000,\n+ Ilogic_shift_ANDS = 0x6a000000,\n \n /* Logical shifted register instructions (with a shift). */\n- I3502S_AND_LSR = I3510_AND | (1 << 22),\n+ Iaddsub_realshift_AND_LSR = Ilogic_shift_AND | (1 << 22),\n \n /* AdvSIMD copy */\n- I3605_DUP = 0x0e000400,\n- I3605_INS = 0x4e001c00,\n- I3605_UMOV = 0x0e003c00,\n+ Isimd_copy_DUP = 0x0e000400,\n+ Isimd_copy_INS = 0x4e001c00,\n+ Isimd_copy_UMOV = 0x0e003c00,\n \n /* AdvSIMD modified immediate */\n- I3606_MOVI = 0x0f000400,\n- I3606_MVNI = 0x2f000400,\n- I3606_BIC = 0x2f001400,\n- I3606_ORR = 0x0f001400,\n+ Isimd_imm_MOVI = 0x0f000400,\n+ Isimd_imm_MVNI = 0x2f000400,\n+ Isimd_imm_BIC = 0x2f001400,\n+ Isimd_imm_ORR = 0x0f001400,\n \n /* AdvSIMD scalar shift by immediate */\n- I3609_SSHR = 0x5f000400,\n- I3609_SSRA = 0x5f001400,\n- I3609_SHL = 0x5f005400,\n- I3609_USHR = 0x7f000400,\n- I3609_USRA = 0x7f001400,\n- I3609_SLI = 0x7f005400,\n+ Iq_shift_SSHR = 0x5f000400,\n+ Iq_shift_SSRA = 0x5f001400,\n+ Iq_shift_SHL = 0x5f005400,\n+ Iq_shift_USHR = 0x7f000400,\n+ Iq_shift_USRA = 0x7f001400,\n+ Iq_shift_SLI = 0x7f005400,\n \n /* AdvSIMD scalar three same */\n- I3611_SQADD = 0x5e200c00,\n- I3611_SQSUB = 0x5e202c00,\n- I3611_CMGT = 0x5e203400,\n- I3611_CMGE = 0x5e203c00,\n- I3611_SSHL = 0x5e204400,\n- I3611_ADD = 0x5e208400,\n- I3611_CMTST = 0x5e208c00,\n- I3611_UQADD = 0x7e200c00,\n- I3611_UQSUB = 0x7e202c00,\n- I3611_CMHI = 0x7e203400,\n- I3611_CMHS = 0x7e203c00,\n- I3611_USHL = 0x7e204400,\n- I3611_SUB = 0x7e208400,\n- I3611_CMEQ = 0x7e208c00,\n+ Irrr_e_SQADD = 0x5e200c00,\n+ Irrr_e_SQSUB = 0x5e202c00,\n+ Irrr_e_CMGT = 0x5e203400,\n+ Irrr_e_CMGE = 0x5e203c00,\n+ Irrr_e_SSHL = 0x5e204400,\n+ Irrr_e_ADD = 0x5e208400,\n+ Irrr_e_CMTST = 0x5e208c00,\n+ Irrr_e_UQADD = 0x7e200c00,\n+ Irrr_e_UQSUB = 0x7e202c00,\n+ Irrr_e_CMHI = 0x7e203400,\n+ Irrr_e_CMHS = 0x7e203c00,\n+ Irrr_e_USHL = 0x7e204400,\n+ Irrr_e_SUB = 0x7e208400,\n+ Irrr_e_CMEQ = 0x7e208c00,\n \n /* AdvSIMD scalar two-reg misc */\n- I3612_CMGT0 = 0x5e208800,\n- I3612_CMEQ0 = 0x5e209800,\n- I3612_CMLT0 = 0x5e20a800,\n- I3612_ABS = 0x5e20b800,\n- I3612_CMGE0 = 0x7e208800,\n- I3612_CMLE0 = 0x7e209800,\n- I3612_NEG = 0x7e20b800,\n+ Isimd_rr_CMGT0 = 0x5e208800,\n+ Isimd_rr_CMEQ0 = 0x5e209800,\n+ Isimd_rr_CMLT0 = 0x5e20a800,\n+ Isimd_rr_ABS = 0x5e20b800,\n+ Isimd_rr_CMGE0 = 0x7e208800,\n+ Isimd_rr_CMLE0 = 0x7e209800,\n+ Isimd_rr_NEG = 0x7e20b800,\n \n /* AdvSIMD shift by immediate */\n- I3614_SSHR = 0x0f000400,\n- I3614_SSRA = 0x0f001400,\n- I3614_SHL = 0x0f005400,\n- I3614_SLI = 0x2f005400,\n- I3614_USHR = 0x2f000400,\n- I3614_USRA = 0x2f001400,\n+ Isimd_shift_imm_SSHR = 0x0f000400,\n+ Isimd_shift_imm_SSRA = 0x0f001400,\n+ Isimd_shift_imm_SHL = 0x0f005400,\n+ Isimd_shift_imm_SLI = 0x2f005400,\n+ Isimd_shift_imm_USHR = 0x2f000400,\n+ Isimd_shift_imm_USRA = 0x2f001400,\n \n /* AdvSIMD three same. */\n- I3616_ADD = 0x0e208400,\n- I3616_AND = 0x0e201c00,\n- I3616_BIC = 0x0e601c00,\n- I3616_BIF = 0x2ee01c00,\n- I3616_BIT = 0x2ea01c00,\n- I3616_BSL = 0x2e601c00,\n- I3616_EOR = 0x2e201c00,\n- I3616_MUL = 0x0e209c00,\n- I3616_ORR = 0x0ea01c00,\n- I3616_ORN = 0x0ee01c00,\n- I3616_SUB = 0x2e208400,\n- I3616_CMGT = 0x0e203400,\n- I3616_CMGE = 0x0e203c00,\n- I3616_CMTST = 0x0e208c00,\n- I3616_CMHI = 0x2e203400,\n- I3616_CMHS = 0x2e203c00,\n- I3616_CMEQ = 0x2e208c00,\n- I3616_SMAX = 0x0e206400,\n- I3616_SMIN = 0x0e206c00,\n- I3616_SSHL = 0x0e204400,\n- I3616_SQADD = 0x0e200c00,\n- I3616_SQSUB = 0x0e202c00,\n- I3616_UMAX = 0x2e206400,\n- I3616_UMIN = 0x2e206c00,\n- I3616_UQADD = 0x2e200c00,\n- I3616_UQSUB = 0x2e202c00,\n- I3616_USHL = 0x2e204400,\n+ Iqrrr_e_ADD = 0x0e208400,\n+ Iqrrr_e_AND = 0x0e201c00,\n+ Iqrrr_e_BIC = 0x0e601c00,\n+ Iqrrr_e_BIF = 0x2ee01c00,\n+ Iqrrr_e_BIT = 0x2ea01c00,\n+ Iqrrr_e_BSL = 0x2e601c00,\n+ Iqrrr_e_EOR = 0x2e201c00,\n+ Iqrrr_e_MUL = 0x0e209c00,\n+ Iqrrr_e_ORR = 0x0ea01c00,\n+ Iqrrr_e_ORN = 0x0ee01c00,\n+ Iqrrr_e_SUB = 0x2e208400,\n+ Iqrrr_e_CMGT = 0x0e203400,\n+ Iqrrr_e_CMGE = 0x0e203c00,\n+ Iqrrr_e_CMTST = 0x0e208c00,\n+ Iqrrr_e_CMHI = 0x2e203400,\n+ Iqrrr_e_CMHS = 0x2e203c00,\n+ Iqrrr_e_CMEQ = 0x2e208c00,\n+ Iqrrr_e_SMAX = 0x0e206400,\n+ Iqrrr_e_SMIN = 0x0e206c00,\n+ Iqrrr_e_SSHL = 0x0e204400,\n+ Iqrrr_e_SQADD = 0x0e200c00,\n+ Iqrrr_e_SQSUB = 0x0e202c00,\n+ Iqrrr_e_UMAX = 0x2e206400,\n+ Iqrrr_e_UMIN = 0x2e206c00,\n+ Iqrrr_e_UQADD = 0x2e200c00,\n+ Iqrrr_e_UQSUB = 0x2e202c00,\n+ Iqrrr_e_USHL = 0x2e204400,\n \n /* AdvSIMD two-reg misc. */\n- I3617_CMGT0 = 0x0e208800,\n- I3617_CMEQ0 = 0x0e209800,\n- I3617_CMLT0 = 0x0e20a800,\n- I3617_CMGE0 = 0x2e208800,\n- I3617_CMLE0 = 0x2e209800,\n- I3617_NOT = 0x2e205800,\n- I3617_ABS = 0x0e20b800,\n- I3617_NEG = 0x2e20b800,\n+ Iqrr_e_CMGT0 = 0x0e208800,\n+ Iqrr_e_CMEQ0 = 0x0e209800,\n+ Iqrr_e_CMLT0 = 0x0e20a800,\n+ Iqrr_e_CMGE0 = 0x2e208800,\n+ Iqrr_e_CMLE0 = 0x2e209800,\n+ Iqrr_e_NOT = 0x2e205800,\n+ Iqrr_e_ABS = 0x0e20b800,\n+ Iqrr_e_NEG = 0x2e20b800,\n \n /* System instructions. */\n- NOP = 0xd503201f,\n- DMB_ISH = 0xd50338bf,\n- DMB_LD = 0x00000100,\n- DMB_ST = 0x00000200,\n+ NOP = 0xd503201f,\n+ DMB_ISH = 0xd50338bf,\n+ DMB_LD = 0x00000100,\n+ DMB_ST = 0x00000200,\n \n- BTI_C = 0xd503245f,\n- BTI_J = 0xd503249f,\n- BTI_JC = 0xd50324df,\n+ BTI_C = 0xd503245f,\n+ BTI_J = 0xd503249f,\n+ BTI_JC = 0xd50324df,\n } AArch64Insn;\n \n static inline uint32_t tcg_in32(TCGContext *s)\n@@ -661,37 +661,37 @@ static inline uint32_t tcg_in32(TCGContext *s)\n #define tcg_out_insn(S, FMT, OP, ...) \\\n glue(tcg_out_insn_,FMT)(S, glue(glue(glue(I,FMT),_),OP), ## __VA_ARGS__)\n \n-static void tcg_out_insn_3303(TCGContext *s, AArch64Insn insn, bool q,\n+static void tcg_out_insn_simd_loadrep(TCGContext *s, AArch64Insn insn, bool q,\n TCGReg rt, TCGReg rn, unsigned size)\n {\n tcg_out32(s, insn | (rt & 0x1f) | (rn << 5) | (size << 10) | (q << 30));\n }\n \n-static void tcg_out_insn_3305(TCGContext *s, AArch64Insn insn,\n+static void tcg_out_insn_ldlit(TCGContext *s, AArch64Insn insn,\n int imm19, TCGReg rt)\n {\n tcg_out32(s, insn | (imm19 & 0x7ffff) << 5 | rt);\n }\n \n-static void tcg_out_insn_3306(TCGContext *s, AArch64Insn insn, TCGReg rs,\n+static void tcg_out_insn_stxp(TCGContext *s, AArch64Insn insn, TCGReg rs,\n TCGReg rt, TCGReg rt2, TCGReg rn)\n {\n tcg_out32(s, insn | rs << 16 | rt2 << 10 | rn << 5 | rt);\n }\n \n-static void tcg_out_insn_3201(TCGContext *s, AArch64Insn insn, TCGType ext,\n+static void tcg_out_insn_cbz(TCGContext *s, AArch64Insn insn, TCGType ext,\n TCGReg rt, int imm19)\n {\n tcg_out32(s, insn | ext << 31 | (imm19 & 0x7ffff) << 5 | rt);\n }\n \n-static void tcg_out_insn_3202(TCGContext *s, AArch64Insn insn,\n+static void tcg_out_insn_bcond_imm(TCGContext *s, AArch64Insn insn,\n TCGCond c, int imm19)\n {\n tcg_out32(s, insn | tcg_cond_to_aarch64[c] | (imm19 & 0x7ffff) << 5);\n }\n \n-static void tcg_out_insn_3205(TCGContext *s, AArch64Insn insn,\n+static void tcg_out_insn_tbz(TCGContext *s, AArch64Insn insn,\n TCGReg rt, int imm6, int imm14)\n {\n insn |= (imm6 & 0x20) << (31 - 5);\n@@ -699,17 +699,17 @@ static void tcg_out_insn_3205(TCGContext *s, AArch64Insn insn,\n tcg_out32(s, insn | (imm14 & 0x3fff) << 5 | rt);\n }\n \n-static void tcg_out_insn_3206(TCGContext *s, AArch64Insn insn, int imm26)\n+static void tcg_out_insn_branch(TCGContext *s, AArch64Insn insn, int imm26)\n {\n tcg_out32(s, insn | (imm26 & 0x03ffffff));\n }\n \n-static void tcg_out_insn_3207(TCGContext *s, AArch64Insn insn, TCGReg rn)\n+static void tcg_out_insn_bcond_reg(TCGContext *s, AArch64Insn insn, TCGReg rn)\n {\n tcg_out32(s, insn | rn << 5);\n }\n \n-static void tcg_out_insn_3314(TCGContext *s, AArch64Insn insn,\n+static void tcg_out_insn_ldstpair(TCGContext *s, AArch64Insn insn,\n TCGReg r1, TCGReg r2, TCGReg rn,\n tcg_target_long ofs, bool pre, bool w)\n {\n@@ -723,8 +723,9 @@ static void tcg_out_insn_3314(TCGContext *s, AArch64Insn insn,\n tcg_out32(s, insn | r2 << 10 | rn << 5 | r1);\n }\n \n-static void tcg_out_insn_3401(TCGContext *s, AArch64Insn insn, TCGType ext,\n- TCGReg rd, TCGReg rn, uint64_t aimm)\n+static void tcg_out_insn_addsub_imm(TCGContext *s, AArch64Insn insn,\n+ TCGType ext, TCGReg rd, TCGReg rn,\n+ uint64_t aimm)\n {\n if (aimm > 0xfff) {\n tcg_debug_assert((aimm & 0xfff) == 0);\n@@ -738,16 +739,17 @@ static void tcg_out_insn_3401(TCGContext *s, AArch64Insn insn, TCGType ext,\n /* This function can be used for both 3.4.2 (Bitfield) and 3.4.4\n (Logical immediate). Both insn groups have N, IMMR and IMMS fields\n that feed the DecodeBitMasks pseudo function. */\n-static void tcg_out_insn_3402(TCGContext *s, AArch64Insn insn, TCGType ext,\n- TCGReg rd, TCGReg rn, int n, int immr, int imms)\n+static void tcg_out_insn_bitfield(TCGContext *s, AArch64Insn insn, TCGType ext,\n+ TCGReg rd, TCGReg rn, int n, int immr,\n+ int imms)\n {\n tcg_out32(s, insn | ext << 31 | n << 22 | immr << 16 | imms << 10\n | rn << 5 | rd);\n }\n \n-#define tcg_out_insn_3404 tcg_out_insn_3402\n+#define tcg_out_insn_logic_imm tcg_out_insn_bitfield\n \n-static void tcg_out_insn_3403(TCGContext *s, AArch64Insn insn, TCGType ext,\n+static void tcg_out_insn_extract(TCGContext *s, AArch64Insn insn, TCGType ext,\n TCGReg rd, TCGReg rn, TCGReg rm, int imms)\n {\n tcg_out32(s, insn | ext << 31 | ext << 22 | rm << 16 | imms << 10\n@@ -756,20 +758,20 @@ static void tcg_out_insn_3403(TCGContext *s, AArch64Insn insn, TCGType ext,\n \n /* This function is used for the Move (wide immediate) instruction group.\n Note that SHIFT is a full shift count, not the 2 bit HW field. */\n-static void tcg_out_insn_3405(TCGContext *s, AArch64Insn insn, TCGType ext,\n+static void tcg_out_insn_movw(TCGContext *s, AArch64Insn insn, TCGType ext,\n TCGReg rd, uint16_t half, unsigned shift)\n {\n tcg_debug_assert((shift & ~0x30) == 0);\n tcg_out32(s, insn | ext << 31 | shift << (21 - 4) | half << 5 | rd);\n }\n \n-static void tcg_out_insn_3406(TCGContext *s, AArch64Insn insn,\n+static void tcg_out_insn_pcrel(TCGContext *s, AArch64Insn insn,\n TCGReg rd, int64_t disp)\n {\n tcg_out32(s, insn | (disp & 3) << 29 | (disp & 0x1ffffc) << (5 - 2) | rd);\n }\n \n-static inline void tcg_out_insn_3501(TCGContext *s, AArch64Insn insn,\n+static inline void tcg_out_insn_addsub_ext(TCGContext *s, AArch64Insn insn,\n TCGType sf, TCGReg rd, TCGReg rn,\n TCGReg rm, int opt, int imm3)\n {\n@@ -779,9 +781,11 @@ static inline void tcg_out_insn_3501(TCGContext *s, AArch64Insn insn,\n \n /* This function is for both 3.5.2 (Add/Subtract shifted register), for\n the rare occasion when we actually want to supply a shift amount. */\n-static inline void tcg_out_insn_3502S(TCGContext *s, AArch64Insn insn,\n- TCGType ext, TCGReg rd, TCGReg rn,\n- TCGReg rm, int imm6)\n+static inline void tcg_out_insn_addsub_realshift(TCGContext *s,\n+ AArch64Insn insn,\n+ TCGType ext, TCGReg rd,\n+ TCGReg rn, TCGReg rm,\n+ int imm6)\n {\n tcg_out32(s, insn | ext << 31 | rm << 16 | imm6 << 10 | rn << 5 | rd);\n }\n@@ -790,36 +794,37 @@ static inline void tcg_out_insn_3502S(TCGContext *s, AArch64Insn insn,\n and 3.5.10 (Logical shifted register), for the vast majorty of cases\n when we don't want to apply a shift. Thus it can also be used for\n 3.5.3 (Add/subtract with carry) and 3.5.8 (Data processing 2 source). */\n-static void tcg_out_insn_3502(TCGContext *s, AArch64Insn insn, TCGType ext,\n- TCGReg rd, TCGReg rn, TCGReg rm)\n+static void tcg_out_insn_addsub_shift(TCGContext *s, AArch64Insn insn,\n+ TCGType ext, TCGReg rd, TCGReg rn,\n+ TCGReg rm)\n {\n tcg_out32(s, insn | ext << 31 | rm << 16 | rn << 5 | rd);\n }\n \n-#define tcg_out_insn_3503 tcg_out_insn_3502\n-#define tcg_out_insn_3508 tcg_out_insn_3502\n-#define tcg_out_insn_3510 tcg_out_insn_3502\n+#define tcg_out_insn_rrr_sf tcg_out_insn_addsub_shift\n+#define tcg_out_insn_rrr tcg_out_insn_addsub_shift\n+#define tcg_out_insn_logic_shift tcg_out_insn_addsub_shift\n \n-static void tcg_out_insn_3506(TCGContext *s, AArch64Insn insn, TCGType ext,\n+static void tcg_out_insn_csel(TCGContext *s, AArch64Insn insn, TCGType ext,\n TCGReg rd, TCGReg rn, TCGReg rm, TCGCond c)\n {\n tcg_out32(s, insn | ext << 31 | rm << 16 | rn << 5 | rd\n | tcg_cond_to_aarch64[c] << 12);\n }\n \n-static void tcg_out_insn_3507(TCGContext *s, AArch64Insn insn, TCGType ext,\n+static void tcg_out_insn_rr_sf(TCGContext *s, AArch64Insn insn, TCGType ext,\n TCGReg rd, TCGReg rn)\n {\n tcg_out32(s, insn | ext << 31 | rn << 5 | rd);\n }\n \n-static void tcg_out_insn_3509(TCGContext *s, AArch64Insn insn, TCGType ext,\n+static void tcg_out_insn_rrrr(TCGContext *s, AArch64Insn insn, TCGType ext,\n TCGReg rd, TCGReg rn, TCGReg rm, TCGReg ra)\n {\n tcg_out32(s, insn | ext << 31 | rm << 16 | ra << 10 | rn << 5 | rd);\n }\n \n-static void tcg_out_insn_3605(TCGContext *s, AArch64Insn insn, bool q,\n+static void tcg_out_insn_simd_copy(TCGContext *s, AArch64Insn insn, bool q,\n TCGReg rd, TCGReg rn, int dst_idx, int src_idx)\n {\n /* Note that bit 11 set means general register input. Therefore\n@@ -828,47 +833,47 @@ static void tcg_out_insn_3605(TCGContext *s, AArch64Insn insn, bool q,\n | (rd & 0x1f) | (~rn & 0x20) << 6 | (rn & 0x1f) << 5);\n }\n \n-static void tcg_out_insn_3606(TCGContext *s, AArch64Insn insn, bool q,\n+static void tcg_out_insn_simd_imm(TCGContext *s, AArch64Insn insn, bool q,\n TCGReg rd, bool op, int cmode, uint8_t imm8)\n {\n tcg_out32(s, insn | q << 30 | op << 29 | cmode << 12 | (rd & 0x1f)\n | (imm8 & 0xe0) << (16 - 5) | (imm8 & 0x1f) << 5);\n }\n \n-static void tcg_out_insn_3609(TCGContext *s, AArch64Insn insn,\n+static void tcg_out_insn_q_shift(TCGContext *s, AArch64Insn insn,\n TCGReg rd, TCGReg rn, unsigned immhb)\n {\n tcg_out32(s, insn | immhb << 16 | (rn & 0x1f) << 5 | (rd & 0x1f));\n }\n \n-static void tcg_out_insn_3611(TCGContext *s, AArch64Insn insn,\n+static void tcg_out_insn_rrr_e(TCGContext *s, AArch64Insn insn,\n unsigned size, TCGReg rd, TCGReg rn, TCGReg rm)\n {\n tcg_out32(s, insn | (size << 22) | (rm & 0x1f) << 16\n | (rn & 0x1f) << 5 | (rd & 0x1f));\n }\n \n-static void tcg_out_insn_3612(TCGContext *s, AArch64Insn insn,\n+static void tcg_out_insn_simd_rr(TCGContext *s, AArch64Insn insn,\n unsigned size, TCGReg rd, TCGReg rn)\n {\n tcg_out32(s, insn | (size << 22) | (rn & 0x1f) << 5 | (rd & 0x1f));\n }\n \n-static void tcg_out_insn_3614(TCGContext *s, AArch64Insn insn, bool q,\n+static void tcg_out_insn_simd_shift_imm(TCGContext *s, AArch64Insn insn, bool q,\n TCGReg rd, TCGReg rn, unsigned immhb)\n {\n tcg_out32(s, insn | q << 30 | immhb << 16\n | (rn & 0x1f) << 5 | (rd & 0x1f));\n }\n \n-static void tcg_out_insn_3616(TCGContext *s, AArch64Insn insn, bool q,\n+static void tcg_out_insn_qrrr_e(TCGContext *s, AArch64Insn insn, bool q,\n unsigned size, TCGReg rd, TCGReg rn, TCGReg rm)\n {\n tcg_out32(s, insn | q << 30 | (size << 22) | (rm & 0x1f) << 16\n | (rn & 0x1f) << 5 | (rd & 0x1f));\n }\n \n-static void tcg_out_insn_3617(TCGContext *s, AArch64Insn insn, bool q,\n+static void tcg_out_insn_qrr_e(TCGContext *s, AArch64Insn insn, bool q,\n unsigned size, TCGReg rd, TCGReg rn)\n {\n tcg_out32(s, insn | q << 30 | (size << 22)\n@@ -880,11 +885,11 @@ static void tcg_out_insn_3310(TCGContext *s, AArch64Insn insn,\n TCGReg regoff)\n {\n /* Note the AArch64Insn constants above are for C3.3.12. Adjust. */\n- tcg_out32(s, insn | I3312_TO_I3310 | regoff << 16 |\n+ tcg_out32(s, insn | Ildst_imm_TO_I3310 | regoff << 16 |\n 0x4000 | ext << 13 | base << 5 | (rd & 0x1f));\n }\n \n-static void tcg_out_insn_3312(TCGContext *s, AArch64Insn insn,\n+static void tcg_out_insn_ldst_imm(TCGContext *s, AArch64Insn insn,\n TCGReg rd, TCGReg rn, intptr_t offset)\n {\n tcg_out32(s, insn | (offset & 0x1ff) << 12 | rn << 5 | (rd & 0x1f));\n@@ -894,7 +899,7 @@ static void tcg_out_insn_3313(TCGContext *s, AArch64Insn insn,\n TCGReg rd, TCGReg rn, uintptr_t scaled_uimm)\n {\n /* Note the AArch64Insn constants above are for C3.3.12. Adjust. */\n- tcg_out32(s, insn | I3312_TO_I3313 | scaled_uimm << 10\n+ tcg_out32(s, insn | Ildst_imm_TO_I3313 | scaled_uimm << 10\n | rn << 5 | (rd & 0x1f));\n }\n \n@@ -912,13 +917,13 @@ static void tcg_out_bti(TCGContext *s, AArch64Insn insn)\n /* Register to register move using ORR (shifted register with no shift). */\n static void tcg_out_movr(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rm)\n {\n- tcg_out_insn(s, 3510, ORR, ext, rd, TCG_REG_XZR, rm);\n+ tcg_out_insn(s, logic_shift, ORR, ext, rd, TCG_REG_XZR, rm);\n }\n \n /* Register to register move using ADDI (move to/from SP). */\n static void tcg_out_movr_sp(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rn)\n {\n- tcg_out_insn(s, 3401, ADDI, ext, rd, rn, 0);\n+ tcg_out_insn(s, addsub_imm, ADDI, ext, rd, rn, 0);\n }\n \n /* This function is used for the Logical (immediate) instruction group.\n@@ -949,7 +954,7 @@ static void tcg_out_logicali(TCGContext *s, AArch64Insn insn, TCGType ext,\n c &= 31;\n }\n \n- tcg_out_insn_3404(s, insn, ext, rd, rn, ext, r, c);\n+ tcg_out_insn_logic_imm(s, insn, ext, rd, rn, ext, r, c);\n }\n \n static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,\n@@ -961,7 +966,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,\n /* Test all bytes equal first. */\n if (vece == MO_8) {\n imm8 = (uint8_t)v64;\n- tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0xe, imm8);\n+ tcg_out_insn(s, simd_imm, MOVI, q, rd, 0, 0xe, imm8);\n return;\n }\n \n@@ -977,7 +982,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,\n goto fail_bytes;\n }\n }\n- tcg_out_insn(s, 3606, MOVI, q, rd, 1, 0xe, imm8);\n+ tcg_out_insn(s, simd_imm, MOVI, q, rd, 1, 0xe, imm8);\n return;\n fail_bytes:\n \n@@ -990,11 +995,11 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,\n uint16_t v16 = v64;\n \n if (is_shimm16(v16, &cmode, &imm8)) {\n- tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8);\n+ tcg_out_insn(s, simd_imm, MOVI, q, rd, 0, cmode, imm8);\n return;\n }\n if (is_shimm16(~v16, &cmode, &imm8)) {\n- tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8);\n+ tcg_out_insn(s, simd_imm, MVNI, q, rd, 0, cmode, imm8);\n return;\n }\n \n@@ -1002,8 +1007,8 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,\n * Otherwise, all remaining constants can be loaded in two insns:\n * rd = v16 & 0xff, rd |= v16 & 0xff00.\n */\n- tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0x8, v16 & 0xff);\n- tcg_out_insn(s, 3606, ORR, q, rd, 0, 0xa, v16 >> 8);\n+ tcg_out_insn(s, simd_imm, MOVI, q, rd, 0, 0x8, v16 & 0xff);\n+ tcg_out_insn(s, simd_imm, ORR, q, rd, 0, 0xa, v16 >> 8);\n return;\n } else if (vece == MO_32) {\n uint32_t v32 = v64;\n@@ -1012,12 +1017,12 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,\n if (is_shimm32(v32, &cmode, &imm8) ||\n is_soimm32(v32, &cmode, &imm8) ||\n is_fimm32(v32, &cmode, &imm8)) {\n- tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8);\n+ tcg_out_insn(s, simd_imm, MOVI, q, rd, 0, cmode, imm8);\n return;\n }\n if (is_shimm32(n32, &cmode, &imm8) ||\n is_soimm32(n32, &cmode, &imm8)) {\n- tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8);\n+ tcg_out_insn(s, simd_imm, MVNI, q, rd, 0, cmode, imm8);\n return;\n }\n \n@@ -1027,18 +1032,20 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,\n */\n i = is_shimm32_pair(v32, &cmode, &imm8);\n if (i) {\n- tcg_out_insn(s, 3606, MOVI, q, rd, 0, cmode, imm8);\n- tcg_out_insn(s, 3606, ORR, q, rd, 0, i, extract32(v32, i * 4, 8));\n+ tcg_out_insn(s, simd_imm, MOVI, q, rd, 0, cmode, imm8);\n+ tcg_out_insn(s, simd_imm, ORR, q, rd, 0, i,\n+ extract32(v32, i * 4, 8));\n return;\n }\n i = is_shimm32_pair(n32, &cmode, &imm8);\n if (i) {\n- tcg_out_insn(s, 3606, MVNI, q, rd, 0, cmode, imm8);\n- tcg_out_insn(s, 3606, BIC, q, rd, 0, i, extract32(n32, i * 4, 8));\n+ tcg_out_insn(s, simd_imm, MVNI, q, rd, 0, cmode, imm8);\n+ tcg_out_insn(s, simd_imm, BIC, q, rd, 0, i,\n+ extract32(n32, i * 4, 8));\n return;\n }\n } else if (is_fimm64(v64, &cmode, &imm8)) {\n- tcg_out_insn(s, 3606, MOVI, q, rd, 1, cmode, imm8);\n+ tcg_out_insn(s, simd_imm, MOVI, q, rd, 1, cmode, imm8);\n return;\n }\n \n@@ -1048,10 +1055,10 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,\n */\n if (type == TCG_TYPE_V128) {\n new_pool_l2(s, R_AARCH64_CONDBR19, s->code_ptr, 0, v64, v64);\n- tcg_out_insn(s, 3305, LDR_v128, 0, rd);\n+ tcg_out_insn(s, ldlit, LDR_v128, 0, rd);\n } else {\n new_pool_label(s, v64, R_AARCH64_CONDBR19, s->code_ptr, 0);\n- tcg_out_insn(s, 3305, LDR_v64, 0, rd);\n+ tcg_out_insn(s, ldlit, LDR_v64, 0, rd);\n }\n }\n \n@@ -1059,7 +1066,7 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,\n TCGReg rd, TCGReg rs)\n {\n int is_q = type - TCG_TYPE_V64;\n- tcg_out_insn(s, 3605, DUP, is_q, rd, rs, 1 << vece, 0);\n+ tcg_out_insn(s, simd_copy, DUP, is_q, rd, rs, 1 << vece, 0);\n return true;\n }\n \n@@ -1070,25 +1077,26 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,\n \n if (offset < -0xffffff || offset > 0xffffff) {\n tcg_out_movi(s, TCG_TYPE_PTR, temp, offset);\n- tcg_out_insn(s, 3502, ADD, 1, temp, temp, base);\n+ tcg_out_insn(s, addsub_shift, ADD, 1, temp, temp, base);\n base = temp;\n } else {\n- AArch64Insn add_insn = I3401_ADDI;\n+ AArch64Insn add_insn = Iaddsub_imm_ADDI;\n \n if (offset < 0) {\n- add_insn = I3401_SUBI;\n+ add_insn = Iaddsub_imm_SUBI;\n offset = -offset;\n }\n if (offset & 0xfff000) {\n- tcg_out_insn_3401(s, add_insn, 1, temp, base, offset & 0xfff000);\n+ tcg_out_insn_addsub_imm(s, add_insn, 1, temp, base,\n+ offset & 0xfff000);\n base = temp;\n }\n if (offset & 0xfff) {\n- tcg_out_insn_3401(s, add_insn, 1, temp, base, offset & 0xfff);\n+ tcg_out_insn_addsub_imm(s, add_insn, 1, temp, base, offset & 0xfff);\n base = temp;\n }\n }\n- tcg_out_insn(s, 3303, LD1R, type == TCG_TYPE_V128, r, base, vece);\n+ tcg_out_insn(s, simd_loadrep, LD1R, type == TCG_TYPE_V128, r, base, vece);\n return true;\n }\n \n@@ -1124,10 +1132,10 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,\n /* Speed things up by handling the common case of small positive\n and negative values specially. */\n if ((value & ~0xffffull) == 0) {\n- tcg_out_insn(s, 3405, MOVZ, type, rd, value, 0);\n+ tcg_out_insn(s, movw, MOVZ, type, rd, value, 0);\n return;\n } else if ((ivalue & ~0xffffull) == 0) {\n- tcg_out_insn(s, 3405, MOVN, type, rd, ivalue, 0);\n+ tcg_out_insn(s, movw, MOVN, type, rd, ivalue, 0);\n return;\n }\n \n@@ -1135,7 +1143,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,\n use the sign-extended value. That lets us match rotated values such\n as 0xff0000ff with the same 64-bit logic matching 0xffffffffff0000ff. */\n if (is_limm(svalue)) {\n- tcg_out_logicali(s, I3404_ORRI, type, rd, TCG_REG_XZR, svalue);\n+ tcg_out_logicali(s, Ilogic_imm_ORRI, type, rd, TCG_REG_XZR, svalue);\n return;\n }\n \n@@ -1145,14 +1153,14 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,\n intptr_t src_rx = (intptr_t)tcg_splitwx_to_rx(s->code_ptr);\n tcg_target_long disp = value - src_rx;\n if (disp == sextract64(disp, 0, 21)) {\n- tcg_out_insn(s, 3406, ADR, rd, disp);\n+ tcg_out_insn(s, pcrel, ADR, rd, disp);\n return;\n }\n disp = (value >> 12) - (src_rx >> 12);\n if (disp == sextract64(disp, 0, 21)) {\n- tcg_out_insn(s, 3406, ADRP, rd, disp);\n+ tcg_out_insn(s, pcrel, ADRP, rd, disp);\n if (value & 0xfff) {\n- tcg_out_insn(s, 3401, ADDI, type, rd, rd, value & 0xfff);\n+ tcg_out_insn(s, addsub_imm, ADDI, type, rd, rd, value & 0xfff);\n }\n return;\n }\n@@ -1161,26 +1169,26 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,\n /* Would it take fewer insns to begin with MOVN? */\n if (ctpop64(value) >= 32) {\n t0 = ivalue;\n- opc = I3405_MOVN;\n+ opc = Imovw_MOVN;\n } else {\n t0 = value;\n- opc = I3405_MOVZ;\n+ opc = Imovw_MOVZ;\n }\n s0 = ctz64(t0) & (63 & -16);\n t1 = t0 & ~(0xffffull << s0);\n s1 = ctz64(t1) & (63 & -16);\n t2 = t1 & ~(0xffffull << s1);\n if (t2 == 0) {\n- tcg_out_insn_3405(s, opc, type, rd, t0 >> s0, s0);\n+ tcg_out_insn_movw(s, opc, type, rd, t0 >> s0, s0);\n if (t1 != 0) {\n- tcg_out_insn(s, 3405, MOVK, type, rd, value >> s1, s1);\n+ tcg_out_insn(s, movw, MOVK, type, rd, value >> s1, s1);\n }\n return;\n }\n \n /* For more than 2 insns, dump it into the constant pool. */\n new_pool_label(s, value, R_AARCH64_CONDBR19, s->code_ptr, 0);\n- tcg_out_insn(s, 3305, LDR, 0, rd);\n+ tcg_out_insn(s, ldlit, LDR, 0, rd);\n }\n \n static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2)\n@@ -1213,7 +1221,7 @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn insn, TCGReg rd,\n \n /* Small signed offsets can use the unscaled encoding. */\n if (offset >= -256 && offset < 256) {\n- tcg_out_insn_3312(s, insn, rd, rn, offset);\n+ tcg_out_insn_ldst_imm(s, insn, rd, rn, offset);\n return;\n }\n \n@@ -1234,21 +1242,21 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)\n tcg_out_movr(s, type, ret, arg);\n break;\n } else if (ret < 32) {\n- tcg_out_insn(s, 3605, UMOV, type, ret, arg, 0, 0);\n+ tcg_out_insn(s, simd_copy, UMOV, type, ret, arg, 0, 0);\n break;\n } else if (arg < 32) {\n- tcg_out_insn(s, 3605, INS, 0, ret, arg, 4 << type, 0);\n+ tcg_out_insn(s, simd_copy, INS, 0, ret, arg, 4 << type, 0);\n break;\n }\n /* FALLTHRU */\n \n case TCG_TYPE_V64:\n tcg_debug_assert(ret >= 32 && arg >= 32);\n- tcg_out_insn(s, 3616, ORR, 0, 0, ret, arg, arg);\n+ tcg_out_insn(s, qrrr_e, ORR, 0, 0, ret, arg, arg);\n break;\n case TCG_TYPE_V128:\n tcg_debug_assert(ret >= 32 && arg >= 32);\n- tcg_out_insn(s, 3616, ORR, 1, 0, ret, arg, arg);\n+ tcg_out_insn(s, qrrr_e, ORR, 1, 0, ret, arg, arg);\n break;\n \n default:\n@@ -1265,19 +1273,19 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,\n \n switch (type) {\n case TCG_TYPE_I32:\n- insn = (ret < 32 ? I3312_LDRW : I3312_LDRVS);\n+ insn = (ret < 32 ? Ildst_imm_LDRW : Ildst_imm_LDRVS);\n lgsz = 2;\n break;\n case TCG_TYPE_I64:\n- insn = (ret < 32 ? I3312_LDRX : I3312_LDRVD);\n+ insn = (ret < 32 ? Ildst_imm_LDRX : Ildst_imm_LDRVD);\n lgsz = 3;\n break;\n case TCG_TYPE_V64:\n- insn = I3312_LDRVD;\n+ insn = Ildst_imm_LDRVD;\n lgsz = 3;\n break;\n case TCG_TYPE_V128:\n- insn = I3312_LDRVQ;\n+ insn = Ildst_imm_LDRVQ;\n lgsz = 4;\n break;\n default:\n@@ -1294,19 +1302,19 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg src,\n \n switch (type) {\n case TCG_TYPE_I32:\n- insn = (src < 32 ? I3312_STRW : I3312_STRVS);\n+ insn = (src < 32 ? Ildst_imm_STRW : Ildst_imm_STRVS);\n lgsz = 2;\n break;\n case TCG_TYPE_I64:\n- insn = (src < 32 ? I3312_STRX : I3312_STRVD);\n+ insn = (src < 32 ? Ildst_imm_STRX : Ildst_imm_STRVD);\n lgsz = 3;\n break;\n case TCG_TYPE_V64:\n- insn = I3312_STRVD;\n+ insn = Ildst_imm_STRVD;\n lgsz = 3;\n break;\n case TCG_TYPE_V128:\n- insn = I3312_STRVQ;\n+ insn = Ildst_imm_STRVQ;\n lgsz = 4;\n break;\n default:\n@@ -1328,34 +1336,34 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,\n static inline void tcg_out_bfm(TCGContext *s, TCGType ext, TCGReg rd,\n TCGReg rn, unsigned int a, unsigned int b)\n {\n- tcg_out_insn(s, 3402, BFM, ext, rd, rn, ext, a, b);\n+ tcg_out_insn(s, bitfield, BFM, ext, rd, rn, ext, a, b);\n }\n \n static inline void tcg_out_ubfm(TCGContext *s, TCGType ext, TCGReg rd,\n TCGReg rn, unsigned int a, unsigned int b)\n {\n- tcg_out_insn(s, 3402, UBFM, ext, rd, rn, ext, a, b);\n+ tcg_out_insn(s, bitfield, UBFM, ext, rd, rn, ext, a, b);\n }\n \n static inline void tcg_out_sbfm(TCGContext *s, TCGType ext, TCGReg rd,\n TCGReg rn, unsigned int a, unsigned int b)\n {\n- tcg_out_insn(s, 3402, SBFM, ext, rd, rn, ext, a, b);\n+ tcg_out_insn(s, bitfield, SBFM, ext, rd, rn, ext, a, b);\n }\n \n static inline void tcg_out_extr(TCGContext *s, TCGType ext, TCGReg rd,\n TCGReg rn, TCGReg rm, unsigned int a)\n {\n- tcg_out_insn(s, 3403, EXTR, ext, rd, rn, rm, a);\n+ tcg_out_insn(s, extract, EXTR, ext, rd, rn, rm, a);\n }\n \n static void tgen_cmp(TCGContext *s, TCGType ext, TCGCond cond,\n TCGReg a, TCGReg b)\n {\n if (is_tst_cond(cond)) {\n- tcg_out_insn(s, 3510, ANDS, ext, TCG_REG_XZR, a, b);\n+ tcg_out_insn(s, logic_shift, ANDS, ext, TCG_REG_XZR, a, b);\n } else {\n- tcg_out_insn(s, 3502, SUBS, ext, TCG_REG_XZR, a, b);\n+ tcg_out_insn(s, addsub_shift, SUBS, ext, TCG_REG_XZR, a, b);\n }\n }\n \n@@ -1363,13 +1371,13 @@ static void tgen_cmpi(TCGContext *s, TCGType ext, TCGCond cond,\n TCGReg a, tcg_target_long b)\n {\n if (is_tst_cond(cond)) {\n- tcg_out_logicali(s, I3404_ANDSI, ext, TCG_REG_XZR, a, b);\n+ tcg_out_logicali(s, Ilogic_imm_ANDSI, ext, TCG_REG_XZR, a, b);\n } else if (b >= 0) {\n tcg_debug_assert(is_aimm(b));\n- tcg_out_insn(s, 3401, SUBSI, ext, TCG_REG_XZR, a, b);\n+ tcg_out_insn(s, addsub_imm, SUBSI, ext, TCG_REG_XZR, a, b);\n } else {\n tcg_debug_assert(is_aimm(-b));\n- tcg_out_insn(s, 3401, ADDSI, ext, TCG_REG_XZR, a, -b);\n+ tcg_out_insn(s, addsub_imm, ADDSI, ext, TCG_REG_XZR, a, -b);\n }\n }\n \n@@ -1387,17 +1395,17 @@ static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target)\n {\n ptrdiff_t offset = tcg_pcrel_diff(s, target) >> 2;\n tcg_debug_assert(offset == sextract64(offset, 0, 26));\n- tcg_out_insn(s, 3206, B, offset);\n+ tcg_out_insn(s, branch, B, offset);\n }\n \n static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *target)\n {\n ptrdiff_t offset = tcg_pcrel_diff(s, target) >> 2;\n if (offset == sextract64(offset, 0, 26)) {\n- tcg_out_insn(s, 3206, BL, offset);\n+ tcg_out_insn(s, branch, BL, offset);\n } else {\n tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, (intptr_t)target);\n- tcg_out_insn(s, 3207, BLR, TCG_REG_TMP0);\n+ tcg_out_insn(s, bcond_reg, BLR, TCG_REG_TMP0);\n }\n }\n \n@@ -1411,7 +1419,7 @@ static void tcg_out_br(TCGContext *s, TCGLabel *l)\n {\n if (!l->has_value) {\n tcg_out_reloc(s, s->code_ptr, R_AARCH64_JUMP26, l, 0);\n- tcg_out_insn(s, 3206, B, 0);\n+ tcg_out_insn(s, branch, B, 0);\n } else {\n tcg_out_goto(s, l->u.value_ptr);\n }\n@@ -1422,7 +1430,7 @@ static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c,\n {\n tgen_cmp(s, type, c, a, b);\n tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, l, 0);\n- tcg_out_insn(s, 3202, B_C, c, 0);\n+ tcg_out_insn(s, bcond_imm, B_C, c, 0);\n }\n \n static void tgen_brcondi(TCGContext *s, TCGType ext, TCGCond c,\n@@ -1470,7 +1478,7 @@ static void tgen_brcondi(TCGContext *s, TCGType ext, TCGCond c,\n if (need_cmp) {\n tgen_cmpi(s, ext, c, a, b);\n tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, l, 0);\n- tcg_out_insn(s, 3202, B_C, c, 0);\n+ tcg_out_insn(s, bcond_imm, B_C, c, 0);\n return;\n }\n \n@@ -1478,10 +1486,10 @@ static void tgen_brcondi(TCGContext *s, TCGType ext, TCGCond c,\n tcg_out_reloc(s, s->code_ptr, R_AARCH64_TSTBR14, l, 0);\n switch (c) {\n case TCG_COND_TSTEQ:\n- tcg_out_insn(s, 3205, TBZ, a, tbit, 0);\n+ tcg_out_insn(s, tbz, TBZ, a, tbit, 0);\n break;\n case TCG_COND_TSTNE:\n- tcg_out_insn(s, 3205, TBNZ, a, tbit, 0);\n+ tcg_out_insn(s, tbz, TBNZ, a, tbit, 0);\n break;\n default:\n g_assert_not_reached();\n@@ -1490,10 +1498,10 @@ static void tgen_brcondi(TCGContext *s, TCGType ext, TCGCond c,\n tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, l, 0);\n switch (c) {\n case TCG_COND_EQ:\n- tcg_out_insn(s, 3201, CBZ, ext, a, 0);\n+ tcg_out_insn(s, cbz, CBZ, ext, a, 0);\n break;\n case TCG_COND_NE:\n- tcg_out_insn(s, 3201, CBNZ, ext, a, 0);\n+ tcg_out_insn(s, cbz, CBNZ, ext, a, 0);\n break;\n default:\n g_assert_not_reached();\n@@ -1511,7 +1519,7 @@ static inline void tcg_out_rev(TCGContext *s, int ext, MemOp s_bits,\n TCGReg rd, TCGReg rn)\n {\n /* REV, REV16, REV32 */\n- tcg_out_insn_3507(s, I3507_REV | (s_bits << 10), ext, rd, rn);\n+ tcg_out_insn_rr_sf(s, Irr_sf_REV | (s_bits << 10), ext, rd, rn);\n }\n \n static inline void tcg_out_sxt(TCGContext *s, TCGType ext, MemOp s_bits,\n@@ -1671,16 +1679,17 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,\n /* Load CPUTLBDescFast.{mask,table} into {tmp0,tmp1}. */\n QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0);\n QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 8);\n- tcg_out_insn(s, 3314, LDP, TCG_REG_TMP0, TCG_REG_TMP1, TCG_AREG0,\n+ tcg_out_insn(s, ldstpair, LDP, TCG_REG_TMP0, TCG_REG_TMP1, TCG_AREG0,\n tlb_mask_table_ofs(s, mem_index), 1, 0);\n \n /* Extract the TLB index from the address into X0. */\n- tcg_out_insn(s, 3502S, AND_LSR, TCG_TYPE_I64,\n+ tcg_out_insn(s, addsub_realshift, AND_LSR, TCG_TYPE_I64,\n TCG_REG_TMP0, TCG_REG_TMP0, addr_reg,\n TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);\n \n /* Add the tlb_table pointer, forming the CPUTLBEntry address. */\n- tcg_out_insn(s, 3502, ADD, 1, TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP0);\n+ tcg_out_insn(s, addsub_shift, ADD, 1, TCG_REG_TMP1, TCG_REG_TMP1,\n+ TCG_REG_TMP0);\n \n /* Load the tlb comparator into TMP0, and the fast path addend. */\n QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN);\n@@ -1700,13 +1709,13 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,\n addr_adj = addr_reg;\n } else {\n addr_adj = TCG_REG_TMP2;\n- tcg_out_insn(s, 3401, ADDI, addr_type,\n+ tcg_out_insn(s, addsub_imm, ADDI, addr_type,\n addr_adj, addr_reg, s_mask - a_mask);\n }\n compare_mask = (uint64_t)TARGET_PAGE_MASK | a_mask;\n \n /* Store the page mask part of the address into TMP2. */\n- tcg_out_logicali(s, I3404_ANDI, addr_type, TCG_REG_TMP2,\n+ tcg_out_logicali(s, Ilogic_imm_ANDI, addr_type, TCG_REG_TMP2,\n addr_adj, compare_mask);\n \n /* Perform the address comparison. */\n@@ -1714,7 +1723,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,\n \n /* If not equal, we jump to the slow path. */\n ldst->label_ptr[0] = s->code_ptr;\n- tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0);\n+ tcg_out_insn(s, bcond_imm, B_C, TCG_COND_NE, 0);\n \n h->base = TCG_REG_TMP1;\n h->index = addr_reg;\n@@ -1728,11 +1737,12 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,\n ldst->addr_reg = addr_reg;\n \n /* tst addr, #mask */\n- tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, a_mask);\n+ tcg_out_logicali(s, Ilogic_imm_ANDSI, 0, TCG_REG_XZR, addr_reg,\n+ a_mask);\n \n /* b.ne slow_path */\n ldst->label_ptr[0] = s->code_ptr;\n- tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0);\n+ tcg_out_insn(s, bcond_imm, B_C, TCG_COND_NE, 0);\n }\n \n if (guest_base || addr_type == TCG_TYPE_I32) {\n@@ -1754,27 +1764,28 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext,\n {\n switch (memop & MO_SSIZE) {\n case MO_UB:\n- tcg_out_ldst_r(s, I3312_LDRB, data_r, h.base, h.index_ext, h.index);\n+ tcg_out_ldst_r(s, Ildst_imm_LDRB, data_r, h.base, h.index_ext, h.index);\n break;\n case MO_SB:\n- tcg_out_ldst_r(s, ext ? I3312_LDRSBX : I3312_LDRSBW,\n+ tcg_out_ldst_r(s, ext ? Ildst_imm_LDRSBX : Ildst_imm_LDRSBW,\n data_r, h.base, h.index_ext, h.index);\n break;\n case MO_UW:\n- tcg_out_ldst_r(s, I3312_LDRH, data_r, h.base, h.index_ext, h.index);\n+ tcg_out_ldst_r(s, Ildst_imm_LDRH, data_r, h.base, h.index_ext, h.index);\n break;\n case MO_SW:\n- tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW),\n+ tcg_out_ldst_r(s, (ext ? Ildst_imm_LDRSHX : Ildst_imm_LDRSHW),\n data_r, h.base, h.index_ext, h.index);\n break;\n case MO_UL:\n- tcg_out_ldst_r(s, I3312_LDRW, data_r, h.base, h.index_ext, h.index);\n+ tcg_out_ldst_r(s, Ildst_imm_LDRW, data_r, h.base, h.index_ext, h.index);\n break;\n case MO_SL:\n- tcg_out_ldst_r(s, I3312_LDRSWX, data_r, h.base, h.index_ext, h.index);\n+ tcg_out_ldst_r(s, Ildst_imm_LDRSWX, data_r, h.base, h.index_ext,\n+ h.index);\n break;\n case MO_UQ:\n- tcg_out_ldst_r(s, I3312_LDRX, data_r, h.base, h.index_ext, h.index);\n+ tcg_out_ldst_r(s, Ildst_imm_LDRX, data_r, h.base, h.index_ext, h.index);\n break;\n default:\n g_assert_not_reached();\n@@ -1786,16 +1797,16 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop,\n {\n switch (memop & MO_SIZE) {\n case MO_8:\n- tcg_out_ldst_r(s, I3312_STRB, data_r, h.base, h.index_ext, h.index);\n+ tcg_out_ldst_r(s, Ildst_imm_STRB, data_r, h.base, h.index_ext, h.index);\n break;\n case MO_16:\n- tcg_out_ldst_r(s, I3312_STRH, data_r, h.base, h.index_ext, h.index);\n+ tcg_out_ldst_r(s, Ildst_imm_STRH, data_r, h.base, h.index_ext, h.index);\n break;\n case MO_32:\n- tcg_out_ldst_r(s, I3312_STRW, data_r, h.base, h.index_ext, h.index);\n+ tcg_out_ldst_r(s, Ildst_imm_STRW, data_r, h.base, h.index_ext, h.index);\n break;\n case MO_64:\n- tcg_out_ldst_r(s, I3312_STRX, data_r, h.base, h.index_ext, h.index);\n+ tcg_out_ldst_r(s, Ildst_imm_STRX, data_r, h.base, h.index_ext, h.index);\n break;\n default:\n g_assert_not_reached();\n@@ -1861,11 +1872,11 @@ static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi,\n base = TCG_REG_TMP2;\n if (h.index_ext == TCG_TYPE_I32) {\n /* add base, base, index, uxtw */\n- tcg_out_insn(s, 3501, ADD, TCG_TYPE_I64, base,\n+ tcg_out_insn(s, addsub_ext, ADD, TCG_TYPE_I64, base,\n h.base, h.index, MO_32, 0);\n } else {\n /* add base, base, index */\n- tcg_out_insn(s, 3502, ADD, 1, base, h.base, h.index);\n+ tcg_out_insn(s, addsub_shift, ADD, 1, base, h.base, h.index);\n }\n }\n \n@@ -1885,9 +1896,10 @@ static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi,\n * TODO: align should be MO_64, so we only need test bit 3,\n * which means we could use TBNZ instead of ANDS+B_C.\n */\n- tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, 15);\n+ tcg_out_logicali(s, Ilogic_imm_ANDSI, 0, TCG_REG_XZR, addr_reg,\n+ 15);\n branch = s->code_ptr;\n- tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0);\n+ tcg_out_insn(s, bcond_imm, B_C, TCG_COND_NE, 0);\n use_pair = true;\n }\n \n@@ -1919,22 +1931,22 @@ static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi,\n sh = datahi;\n }\n \n- tcg_out_insn(s, 3306, LDXP, TCG_REG_XZR, ll, lh, base);\n- tcg_out_insn(s, 3306, STXP, TCG_REG_TMP0, sl, sh, base);\n- tcg_out_insn(s, 3201, CBNZ, 0, TCG_REG_TMP0, -2);\n+ tcg_out_insn(s, stxp, LDXP, TCG_REG_XZR, ll, lh, base);\n+ tcg_out_insn(s, stxp, STXP, TCG_REG_TMP0, sl, sh, base);\n+ tcg_out_insn(s, cbz, CBNZ, 0, TCG_REG_TMP0, -2);\n \n if (use_pair) {\n /* \"b .+8\", branching across the one insn of use_pair. */\n- tcg_out_insn(s, 3206, B, 2);\n+ tcg_out_insn(s, branch, B, 2);\n reloc_pc19(branch, tcg_splitwx_to_rx(s->code_ptr));\n }\n }\n \n if (use_pair) {\n if (is_ld) {\n- tcg_out_insn(s, 3314, LDP, datalo, datahi, base, 0, 1, 0);\n+ tcg_out_insn(s, ldstpair, LDP, datalo, datahi, base, 0, 1, 0);\n } else {\n- tcg_out_insn(s, 3314, STP, datalo, datahi, base, 0, 1, 0);\n+ tcg_out_insn(s, ldstpair, STP, datalo, datahi, base, 0, 1, 0);\n }\n }\n \n@@ -1985,7 +1997,7 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0)\n \n offset = tcg_pcrel_diff(s, target) >> 2;\n if (offset == sextract64(offset, 0, 26)) {\n- tcg_out_insn(s, 3206, B, offset);\n+ tcg_out_insn(s, branch, B, offset);\n } else {\n /*\n * Only x16/x17 generate BTI type Jump (2),\n@@ -1993,7 +2005,7 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0)\n */\n QEMU_BUILD_BUG_ON(TCG_REG_TMP0 != TCG_REG_X16);\n tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, (intptr_t)target);\n- tcg_out_insn(s, 3207, BR, TCG_REG_TMP0);\n+ tcg_out_insn(s, bcond_reg, BR, TCG_REG_TMP0);\n }\n }\n \n@@ -2008,15 +2020,15 @@ static void tcg_out_goto_tb(TCGContext *s, int which)\n tcg_debug_assert(i_off == sextract64(i_off, 0, 21));\n \n set_jmp_insn_offset(s, which);\n- tcg_out32(s, I3206_B);\n- tcg_out_insn(s, 3207, BR, TCG_REG_TMP0);\n+ tcg_out32(s, Ibranch_B);\n+ tcg_out_insn(s, bcond_reg, BR, TCG_REG_TMP0);\n set_jmp_reset_offset(s, which);\n tcg_out_bti(s, BTI_J);\n }\n \n static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0)\n {\n- tcg_out_insn(s, 3207, BR, a0);\n+ tcg_out_insn(s, bcond_reg, BR, a0);\n }\n \n void tb_target_set_jmp_target(const TranslationBlock *tb, int n,\n@@ -2028,13 +2040,13 @@ void tb_target_set_jmp_target(const TranslationBlock *tb, int n,\n \n /* Either directly branch, or indirect branch load. */\n if (d_offset == sextract64(d_offset, 0, 28)) {\n- insn = deposit32(I3206_B, 0, 26, d_offset >> 2);\n+ insn = deposit32(Ibranch_B, 0, 26, d_offset >> 2);\n } else {\n uintptr_t i_addr = (uintptr_t)&tb->jmp_target_addr[n];\n ptrdiff_t i_offset = i_addr - jmp_rx;\n \n /* Note that we asserted this in range in tcg_out_goto_tb. */\n- insn = deposit32(I3305_LDR | TCG_REG_TMP0, 5, 19, i_offset >> 2);\n+ insn = deposit32(Ildlit_LDR | TCG_REG_TMP0, 5, 19, i_offset >> 2);\n }\n qatomic_set((uint32_t *)jmp_rw, insn);\n flush_idcache_range(jmp_rx, jmp_rw, 4);\n@@ -2044,16 +2056,16 @@ void tb_target_set_jmp_target(const TranslationBlock *tb, int n,\n static void tgen_add(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, TCGReg a2)\n {\n- tcg_out_insn(s, 3502, ADD, type, a0, a1, a2);\n+ tcg_out_insn(s, addsub_shift, ADD, type, a0, a1, a2);\n }\n \n static void tgen_addi(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, tcg_target_long a2)\n {\n if (a2 >= 0) {\n- tcg_out_insn(s, 3401, ADDI, type, a0, a1, a2);\n+ tcg_out_insn(s, addsub_imm, ADDI, type, a0, a1, a2);\n } else {\n- tcg_out_insn(s, 3401, SUBI, type, a0, a1, -a2);\n+ tcg_out_insn(s, addsub_imm, SUBI, type, a0, a1, -a2);\n }\n }\n \n@@ -2066,16 +2078,16 @@ static const TCGOutOpBinary outop_add = {\n static void tgen_addco(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, TCGReg a2)\n {\n- tcg_out_insn(s, 3502, ADDS, type, a0, a1, a2);\n+ tcg_out_insn(s, addsub_shift, ADDS, type, a0, a1, a2);\n }\n \n static void tgen_addco_imm(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, tcg_target_long a2)\n {\n if (a2 >= 0) {\n- tcg_out_insn(s, 3401, ADDSI, type, a0, a1, a2);\n+ tcg_out_insn(s, addsub_imm, ADDSI, type, a0, a1, a2);\n } else {\n- tcg_out_insn(s, 3401, SUBSI, type, a0, a1, -a2);\n+ tcg_out_insn(s, addsub_imm, SUBSI, type, a0, a1, -a2);\n }\n }\n \n@@ -2088,7 +2100,7 @@ static const TCGOutOpBinary outop_addco = {\n static void tgen_addci_rrr(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, TCGReg a2)\n {\n- tcg_out_insn(s, 3503, ADC, type, a0, a1, a2);\n+ tcg_out_insn(s, rrr_sf, ADC, type, a0, a1, a2);\n }\n \n static void tgen_addci_rri(TCGContext *s, TCGType type,\n@@ -2099,9 +2111,9 @@ static void tgen_addci_rri(TCGContext *s, TCGType type,\n * that SBC = rn + ~rm + c, so adc -1 is sbc 0, and vice-versa.\n */\n if (a2) {\n- tcg_out_insn(s, 3503, SBC, type, a0, a1, TCG_REG_XZR);\n+ tcg_out_insn(s, rrr_sf, SBC, type, a0, a1, TCG_REG_XZR);\n } else {\n- tcg_out_insn(s, 3503, ADC, type, a0, a1, TCG_REG_XZR);\n+ tcg_out_insn(s, rrr_sf, ADC, type, a0, a1, TCG_REG_XZR);\n }\n }\n \n@@ -2114,7 +2126,7 @@ static const TCGOutOpAddSubCarry outop_addci = {\n static void tgen_addcio(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, TCGReg a2)\n {\n- tcg_out_insn(s, 3503, ADCS, type, a0, a1, a2);\n+ tcg_out_insn(s, rrr_sf, ADCS, type, a0, a1, a2);\n }\n \n static void tgen_addcio_imm(TCGContext *s, TCGType type,\n@@ -2122,9 +2134,9 @@ static void tgen_addcio_imm(TCGContext *s, TCGType type,\n {\n /* Use SBCS w/0 for ADCS w/-1 -- see above. */\n if (a2) {\n- tcg_out_insn(s, 3503, SBCS, type, a0, a1, TCG_REG_XZR);\n+ tcg_out_insn(s, rrr_sf, SBCS, type, a0, a1, TCG_REG_XZR);\n } else {\n- tcg_out_insn(s, 3503, ADCS, type, a0, a1, TCG_REG_XZR);\n+ tcg_out_insn(s, rrr_sf, ADCS, type, a0, a1, TCG_REG_XZR);\n }\n }\n \n@@ -2136,20 +2148,20 @@ static const TCGOutOpBinary outop_addcio = {\n \n static void tcg_out_set_carry(TCGContext *s)\n {\n- tcg_out_insn(s, 3502, SUBS, TCG_TYPE_I32,\n+ tcg_out_insn(s, addsub_shift, SUBS, TCG_TYPE_I32,\n TCG_REG_XZR, TCG_REG_XZR, TCG_REG_XZR);\n }\n \n static void tgen_and(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, TCGReg a2)\n {\n- tcg_out_insn(s, 3510, AND, type, a0, a1, a2);\n+ tcg_out_insn(s, logic_shift, AND, type, a0, a1, a2);\n }\n \n static void tgen_andi(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, tcg_target_long a2)\n {\n- tcg_out_logicali(s, I3404_ANDI, type, a0, a1, a2);\n+ tcg_out_logicali(s, Ilogic_imm_ANDI, type, a0, a1, a2);\n }\n \n static const TCGOutOpBinary outop_and = {\n@@ -2161,7 +2173,7 @@ static const TCGOutOpBinary outop_and = {\n static void tgen_andc(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, TCGReg a2)\n {\n- tcg_out_insn(s, 3510, BIC, type, a0, a1, a2);\n+ tcg_out_insn(s, logic_shift, BIC, type, a0, a1, a2);\n }\n \n static const TCGOutOpBinary outop_andc = {\n@@ -2173,31 +2185,31 @@ static void tgen_clz(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, TCGReg a2)\n {\n tcg_out_cmp(s, type, TCG_COND_NE, a1, 0, true);\n- tcg_out_insn(s, 3507, CLZ, type, TCG_REG_TMP0, a1);\n- tcg_out_insn(s, 3506, CSEL, type, a0, TCG_REG_TMP0, a2, TCG_COND_NE);\n+ tcg_out_insn(s, rr_sf, CLZ, type, TCG_REG_TMP0, a1);\n+ tcg_out_insn(s, csel, CSEL, type, a0, TCG_REG_TMP0, a2, TCG_COND_NE);\n }\n \n static void tgen_clzi(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, tcg_target_long a2)\n {\n if (a2 == (type == TCG_TYPE_I32 ? 32 : 64)) {\n- tcg_out_insn(s, 3507, CLZ, type, a0, a1);\n+ tcg_out_insn(s, rr_sf, CLZ, type, a0, a1);\n return;\n }\n \n tcg_out_cmp(s, type, TCG_COND_NE, a1, 0, true);\n- tcg_out_insn(s, 3507, CLZ, type, a0, a1);\n+ tcg_out_insn(s, rr_sf, CLZ, type, a0, a1);\n \n switch (a2) {\n case -1:\n- tcg_out_insn(s, 3506, CSINV, type, a0, a0, TCG_REG_XZR, TCG_COND_NE);\n+ tcg_out_insn(s, csel, CSINV, type, a0, a0, TCG_REG_XZR, TCG_COND_NE);\n break;\n case 0:\n- tcg_out_insn(s, 3506, CSEL, type, a0, a0, TCG_REG_XZR, TCG_COND_NE);\n+ tcg_out_insn(s, csel, CSEL, type, a0, a0, TCG_REG_XZR, TCG_COND_NE);\n break;\n default:\n tcg_out_movi(s, type, TCG_REG_TMP0, a2);\n- tcg_out_insn(s, 3506, CSEL, type, a0, a0, TCG_REG_TMP0, TCG_COND_NE);\n+ tcg_out_insn(s, csel, CSEL, type, a0, a0, TCG_REG_TMP0, TCG_COND_NE);\n break;\n }\n }\n@@ -2215,14 +2227,14 @@ static const TCGOutOpUnary outop_ctpop = {\n static void tgen_ctz(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, TCGReg a2)\n {\n- tcg_out_insn(s, 3507, RBIT, type, TCG_REG_TMP0, a1);\n+ tcg_out_insn(s, rr_sf, RBIT, type, TCG_REG_TMP0, a1);\n tgen_clz(s, type, a0, TCG_REG_TMP0, a2);\n }\n \n static void tgen_ctzi(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, tcg_target_long a2)\n {\n- tcg_out_insn(s, 3507, RBIT, type, TCG_REG_TMP0, a1);\n+ tcg_out_insn(s, rr_sf, RBIT, type, TCG_REG_TMP0, a1);\n tgen_clzi(s, type, a0, TCG_REG_TMP0, a2);\n }\n \n@@ -2235,7 +2247,7 @@ static const TCGOutOpBinary outop_ctz = {\n static void tgen_divs(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, TCGReg a2)\n {\n- tcg_out_insn(s, 3508, SDIV, type, a0, a1, a2);\n+ tcg_out_insn(s, rrr, SDIV, type, a0, a1, a2);\n }\n \n static const TCGOutOpBinary outop_divs = {\n@@ -2250,7 +2262,7 @@ static const TCGOutOpDivRem outop_divs2 = {\n static void tgen_divu(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, TCGReg a2)\n {\n- tcg_out_insn(s, 3508, UDIV, type, a0, a1, a2);\n+ tcg_out_insn(s, rrr, UDIV, type, a0, a1, a2);\n }\n \n static const TCGOutOpBinary outop_divu = {\n@@ -2265,7 +2277,7 @@ static const TCGOutOpDivRem outop_divu2 = {\n static void tgen_eqv(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, TCGReg a2)\n {\n- tcg_out_insn(s, 3510, EON, type, a0, a1, a2);\n+ tcg_out_insn(s, logic_shift, EON, type, a0, a1, a2);\n }\n \n static const TCGOutOpBinary outop_eqv = {\n@@ -2286,7 +2298,7 @@ static const TCGOutOpUnary outop_extrh_i64_i32 = {\n static void tgen_mul(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, TCGReg a2)\n {\n- tcg_out_insn(s, 3509, MADD, type, a0, a1, a2, TCG_REG_XZR);\n+ tcg_out_insn(s, rrrr, MADD, type, a0, a1, a2, TCG_REG_XZR);\n }\n \n static const TCGOutOpBinary outop_mul = {\n@@ -2306,7 +2318,7 @@ static TCGConstraintSetIndex cset_mulh(TCGType type, unsigned flags)\n static void tgen_mulsh(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, TCGReg a2)\n {\n- tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2);\n+ tcg_out_insn(s, rrr, SMULH, TCG_TYPE_I64, a0, a1, a2);\n }\n \n static const TCGOutOpBinary outop_mulsh = {\n@@ -2322,7 +2334,7 @@ static const TCGOutOpMul2 outop_mulu2 = {\n static void tgen_muluh(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, TCGReg a2)\n {\n- tcg_out_insn(s, 3508, UMULH, TCG_TYPE_I64, a0, a1, a2);\n+ tcg_out_insn(s, rrr, UMULH, TCG_TYPE_I64, a0, a1, a2);\n }\n \n static const TCGOutOpBinary outop_muluh = {\n@@ -2342,13 +2354,13 @@ static const TCGOutOpBinary outop_nor = {\n static void tgen_or(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, TCGReg a2)\n {\n- tcg_out_insn(s, 3510, ORR, type, a0, a1, a2);\n+ tcg_out_insn(s, logic_shift, ORR, type, a0, a1, a2);\n }\n \n static void tgen_ori(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, tcg_target_long a2)\n {\n- tcg_out_logicali(s, I3404_ORRI, type, a0, a1, a2);\n+ tcg_out_logicali(s, Ilogic_imm_ORRI, type, a0, a1, a2);\n }\n \n static const TCGOutOpBinary outop_or = {\n@@ -2360,7 +2372,7 @@ static const TCGOutOpBinary outop_or = {\n static void tgen_orc(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, TCGReg a2)\n {\n- tcg_out_insn(s, 3510, ORN, type, a0, a1, a2);\n+ tcg_out_insn(s, logic_shift, ORN, type, a0, a1, a2);\n }\n \n static const TCGOutOpBinary outop_orc = {\n@@ -2371,8 +2383,8 @@ static const TCGOutOpBinary outop_orc = {\n static void tgen_rems(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, TCGReg a2)\n {\n- tcg_out_insn(s, 3508, SDIV, type, TCG_REG_TMP0, a1, a2);\n- tcg_out_insn(s, 3509, MSUB, type, a0, TCG_REG_TMP0, a2, a1);\n+ tcg_out_insn(s, rrr, SDIV, type, TCG_REG_TMP0, a1, a2);\n+ tcg_out_insn(s, rrrr, MSUB, type, a0, TCG_REG_TMP0, a2, a1);\n }\n \n static const TCGOutOpBinary outop_rems = {\n@@ -2383,8 +2395,8 @@ static const TCGOutOpBinary outop_rems = {\n static void tgen_remu(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, TCGReg a2)\n {\n- tcg_out_insn(s, 3508, UDIV, type, TCG_REG_TMP0, a1, a2);\n- tcg_out_insn(s, 3509, MSUB, type, a0, TCG_REG_TMP0, a2, a1);\n+ tcg_out_insn(s, rrr, UDIV, type, TCG_REG_TMP0, a1, a2);\n+ tcg_out_insn(s, rrrr, MSUB, type, a0, TCG_REG_TMP0, a2, a1);\n }\n \n static const TCGOutOpBinary outop_remu = {\n@@ -2399,7 +2411,7 @@ static const TCGOutOpBinary outop_rotl = {\n static void tgen_rotr(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, TCGReg a2)\n {\n- tcg_out_insn(s, 3508, RORV, type, a0, a1, a2);\n+ tcg_out_insn(s, rrr, RORV, type, a0, a1, a2);\n }\n \n static void tgen_rotri(TCGContext *s, TCGType type,\n@@ -2418,7 +2430,7 @@ static const TCGOutOpBinary outop_rotr = {\n static void tgen_sar(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, TCGReg a2)\n {\n- tcg_out_insn(s, 3508, ASRV, type, a0, a1, a2);\n+ tcg_out_insn(s, rrr, ASRV, type, a0, a1, a2);\n }\n \n static void tgen_sari(TCGContext *s, TCGType type,\n@@ -2437,7 +2449,7 @@ static const TCGOutOpBinary outop_sar = {\n static void tgen_shl(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, TCGReg a2)\n {\n- tcg_out_insn(s, 3508, LSLV, type, a0, a1, a2);\n+ tcg_out_insn(s, rrr, LSLV, type, a0, a1, a2);\n }\n \n static void tgen_shli(TCGContext *s, TCGType type,\n@@ -2456,7 +2468,7 @@ static const TCGOutOpBinary outop_shl = {\n static void tgen_shr(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, TCGReg a2)\n {\n- tcg_out_insn(s, 3508, LSRV, type, a0, a1, a2);\n+ tcg_out_insn(s, rrr, LSRV, type, a0, a1, a2);\n }\n \n static void tgen_shri(TCGContext *s, TCGType type,\n@@ -2475,7 +2487,7 @@ static const TCGOutOpBinary outop_shr = {\n static void tgen_sub(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, TCGReg a2)\n {\n- tcg_out_insn(s, 3502, SUB, type, a0, a1, a2);\n+ tcg_out_insn(s, addsub_shift, SUB, type, a0, a1, a2);\n }\n \n static const TCGOutOpSubtract outop_sub = {\n@@ -2486,16 +2498,16 @@ static const TCGOutOpSubtract outop_sub = {\n static void tgen_subbo_rrr(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, TCGReg a2)\n {\n- tcg_out_insn(s, 3502, SUBS, type, a0, a1, a2);\n+ tcg_out_insn(s, addsub_shift, SUBS, type, a0, a1, a2);\n }\n \n static void tgen_subbo_rri(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, tcg_target_long a2)\n {\n if (a2 >= 0) {\n- tcg_out_insn(s, 3401, SUBSI, type, a0, a1, a2);\n+ tcg_out_insn(s, addsub_imm, SUBSI, type, a0, a1, a2);\n } else {\n- tcg_out_insn(s, 3401, ADDSI, type, a0, a1, -a2);\n+ tcg_out_insn(s, addsub_imm, ADDSI, type, a0, a1, -a2);\n }\n }\n \n@@ -2535,7 +2547,7 @@ static const TCGOutOpAddSubCarry outop_subbo = {\n static void tgen_subbi_rrr(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, TCGReg a2)\n {\n- tcg_out_insn(s, 3503, SBC, type, a0, a1, a2);\n+ tcg_out_insn(s, rrr_sf, SBC, type, a0, a1, a2);\n }\n \n static void tgen_subbi_rri(TCGContext *s, TCGType type,\n@@ -2553,7 +2565,7 @@ static const TCGOutOpAddSubCarry outop_subbi = {\n static void tgen_subbio_rrr(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, TCGReg a2)\n {\n- tcg_out_insn(s, 3503, SBCS, type, a0, a1, a2);\n+ tcg_out_insn(s, rrr_sf, SBCS, type, a0, a1, a2);\n }\n \n static void tgen_subbio_rri(TCGContext *s, TCGType type,\n@@ -2570,20 +2582,20 @@ static const TCGOutOpAddSubCarry outop_subbio = {\n \n static void tcg_out_set_borrow(TCGContext *s)\n {\n- tcg_out_insn(s, 3502, ADDS, TCG_TYPE_I32,\n+ tcg_out_insn(s, addsub_shift, ADDS, TCG_TYPE_I32,\n TCG_REG_XZR, TCG_REG_XZR, TCG_REG_XZR);\n }\n \n static void tgen_xor(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, TCGReg a2)\n {\n- tcg_out_insn(s, 3510, EOR, type, a0, a1, a2);\n+ tcg_out_insn(s, logic_shift, EOR, type, a0, a1, a2);\n }\n \n static void tgen_xori(TCGContext *s, TCGType type,\n TCGReg a0, TCGReg a1, tcg_target_long a2)\n {\n- tcg_out_logicali(s, I3404_EORI, type, a0, a1, a2);\n+ tcg_out_logicali(s, Ilogic_imm_EORI, type, a0, a1, a2);\n }\n \n static const TCGOutOpBinary outop_xor = {\n@@ -2657,7 +2669,7 @@ static const TCGOutOpUnary outop_not = {\n static void tgen_cset(TCGContext *s, TCGCond cond, TCGReg ret)\n {\n /* Use CSET alias of CSINC Wd, WZR, WZR, invert(cond). */\n- tcg_out_insn(s, 3506, CSINC, TCG_TYPE_I32, ret, TCG_REG_XZR,\n+ tcg_out_insn(s, csel, CSINC, TCG_TYPE_I32, ret, TCG_REG_XZR,\n TCG_REG_XZR, tcg_invert_cond(cond));\n }\n \n@@ -2684,7 +2696,7 @@ static const TCGOutOpSetcond outop_setcond = {\n static void tgen_csetm(TCGContext *s, TCGType ext, TCGCond cond, TCGReg ret)\n {\n /* Use CSETM alias of CSINV Wd, WZR, WZR, invert(cond). */\n- tcg_out_insn(s, 3506, CSINV, ext, ret, TCG_REG_XZR,\n+ tcg_out_insn(s, csel, CSINV, ext, ret, TCG_REG_XZR,\n TCG_REG_XZR, tcg_invert_cond(cond));\n }\n \n@@ -2713,7 +2725,7 @@ static void tgen_movcond(TCGContext *s, TCGType type, TCGCond cond,\n TCGArg vt, bool const_vt, TCGArg vf, bool const_vf)\n {\n tcg_out_cmp(s, type, cond, c1, c2, const_c2);\n- tcg_out_insn(s, 3506, CSEL, type, ret, vt, vf, cond);\n+ tcg_out_insn(s, csel, CSEL, type, ret, vt, vf, cond);\n }\n \n static const TCGOutOpMovcond outop_movcond = {\n@@ -2765,7 +2777,7 @@ static void tgen_extract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1,\n {\n if (ofs == 0) {\n uint64_t mask = MAKE_64BIT_MASK(0, len);\n- tcg_out_logicali(s, I3404_ANDI, type, a0, a1, mask);\n+ tcg_out_logicali(s, Ilogic_imm_ANDI, type, a0, a1, mask);\n } else {\n tcg_out_ubfm(s, type, a0, a1, ofs, ofs + len - 1);\n }\n@@ -2801,7 +2813,7 @@ static const TCGOutOpExtract2 outop_extract2 = {\n static void tgen_ld8u(TCGContext *s, TCGType type, TCGReg dest,\n TCGReg base, ptrdiff_t offset)\n {\n- tcg_out_ldst(s, I3312_LDRB, dest, base, offset, 0);\n+ tcg_out_ldst(s, Ildst_imm_LDRB, dest, base, offset, 0);\n }\n \n static const TCGOutOpLoad outop_ld8u = {\n@@ -2812,7 +2824,8 @@ static const TCGOutOpLoad outop_ld8u = {\n static void tgen_ld8s(TCGContext *s, TCGType type, TCGReg dest,\n TCGReg base, ptrdiff_t offset)\n {\n- AArch64Insn insn = type == TCG_TYPE_I32 ? I3312_LDRSBW : I3312_LDRSBX;\n+ AArch64Insn insn = type == TCG_TYPE_I32 ? Ildst_imm_LDRSBW\n+ : Ildst_imm_LDRSBX;\n tcg_out_ldst(s, insn, dest, base, offset, 0);\n }\n \n@@ -2824,7 +2837,7 @@ static const TCGOutOpLoad outop_ld8s = {\n static void tgen_ld16u(TCGContext *s, TCGType type, TCGReg dest,\n TCGReg base, ptrdiff_t offset)\n {\n- tcg_out_ldst(s, I3312_LDRH, dest, base, offset, 1);\n+ tcg_out_ldst(s, Ildst_imm_LDRH, dest, base, offset, 1);\n }\n \n static const TCGOutOpLoad outop_ld16u = {\n@@ -2835,7 +2848,8 @@ static const TCGOutOpLoad outop_ld16u = {\n static void tgen_ld16s(TCGContext *s, TCGType type, TCGReg dest,\n TCGReg base, ptrdiff_t offset)\n {\n- AArch64Insn insn = type == TCG_TYPE_I32 ? I3312_LDRSHW : I3312_LDRSHX;\n+ AArch64Insn insn = type == TCG_TYPE_I32 ? Ildst_imm_LDRSHW\n+ : Ildst_imm_LDRSHX;\n tcg_out_ldst(s, insn, dest, base, offset, 1);\n }\n \n@@ -2847,7 +2861,7 @@ static const TCGOutOpLoad outop_ld16s = {\n static void tgen_ld32u(TCGContext *s, TCGType type, TCGReg dest,\n TCGReg base, ptrdiff_t offset)\n {\n- tcg_out_ldst(s, I3312_LDRW, dest, base, offset, 2);\n+ tcg_out_ldst(s, Ildst_imm_LDRW, dest, base, offset, 2);\n }\n \n static const TCGOutOpLoad outop_ld32u = {\n@@ -2858,7 +2872,7 @@ static const TCGOutOpLoad outop_ld32u = {\n static void tgen_ld32s(TCGContext *s, TCGType type, TCGReg dest,\n TCGReg base, ptrdiff_t offset)\n {\n- tcg_out_ldst(s, I3312_LDRSWX, dest, base, offset, 2);\n+ tcg_out_ldst(s, Ildst_imm_LDRSWX, dest, base, offset, 2);\n }\n \n static const TCGOutOpLoad outop_ld32s = {\n@@ -2869,7 +2883,7 @@ static const TCGOutOpLoad outop_ld32s = {\n static void tgen_st8_r(TCGContext *s, TCGType type, TCGReg data,\n TCGReg base, ptrdiff_t offset)\n {\n- tcg_out_ldst(s, I3312_STRB, data, base, offset, 0);\n+ tcg_out_ldst(s, Ildst_imm_STRB, data, base, offset, 0);\n }\n \n static const TCGOutOpStore outop_st8 = {\n@@ -2880,7 +2894,7 @@ static const TCGOutOpStore outop_st8 = {\n static void tgen_st16_r(TCGContext *s, TCGType type, TCGReg data,\n TCGReg base, ptrdiff_t offset)\n {\n- tcg_out_ldst(s, I3312_STRH, data, base, offset, 1);\n+ tcg_out_ldst(s, Ildst_imm_STRH, data, base, offset, 1);\n }\n \n static const TCGOutOpStore outop_st16 = {\n@@ -2899,32 +2913,32 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,\n const int const_args[TCG_MAX_OP_ARGS])\n {\n static const AArch64Insn cmp_vec_insn[16] = {\n- [TCG_COND_EQ] = I3616_CMEQ,\n- [TCG_COND_GT] = I3616_CMGT,\n- [TCG_COND_GE] = I3616_CMGE,\n- [TCG_COND_GTU] = I3616_CMHI,\n- [TCG_COND_GEU] = I3616_CMHS,\n+ [TCG_COND_EQ] = Iqrrr_e_CMEQ,\n+ [TCG_COND_GT] = Iqrrr_e_CMGT,\n+ [TCG_COND_GE] = Iqrrr_e_CMGE,\n+ [TCG_COND_GTU] = Iqrrr_e_CMHI,\n+ [TCG_COND_GEU] = Iqrrr_e_CMHS,\n };\n static const AArch64Insn cmp_scalar_insn[16] = {\n- [TCG_COND_EQ] = I3611_CMEQ,\n- [TCG_COND_GT] = I3611_CMGT,\n- [TCG_COND_GE] = I3611_CMGE,\n- [TCG_COND_GTU] = I3611_CMHI,\n- [TCG_COND_GEU] = I3611_CMHS,\n+ [TCG_COND_EQ] = Irrr_e_CMEQ,\n+ [TCG_COND_GT] = Irrr_e_CMGT,\n+ [TCG_COND_GE] = Irrr_e_CMGE,\n+ [TCG_COND_GTU] = Irrr_e_CMHI,\n+ [TCG_COND_GEU] = Irrr_e_CMHS,\n };\n static const AArch64Insn cmp0_vec_insn[16] = {\n- [TCG_COND_EQ] = I3617_CMEQ0,\n- [TCG_COND_GT] = I3617_CMGT0,\n- [TCG_COND_GE] = I3617_CMGE0,\n- [TCG_COND_LT] = I3617_CMLT0,\n- [TCG_COND_LE] = I3617_CMLE0,\n+ [TCG_COND_EQ] = Iqrr_e_CMEQ0,\n+ [TCG_COND_GT] = Iqrr_e_CMGT0,\n+ [TCG_COND_GE] = Iqrr_e_CMGE0,\n+ [TCG_COND_LT] = Iqrr_e_CMLT0,\n+ [TCG_COND_LE] = Iqrr_e_CMLE0,\n };\n static const AArch64Insn cmp0_scalar_insn[16] = {\n- [TCG_COND_EQ] = I3612_CMEQ0,\n- [TCG_COND_GT] = I3612_CMGT0,\n- [TCG_COND_GE] = I3612_CMGE0,\n- [TCG_COND_LT] = I3612_CMLT0,\n- [TCG_COND_LE] = I3612_CMLE0,\n+ [TCG_COND_EQ] = Isimd_rr_CMEQ0,\n+ [TCG_COND_GT] = Isimd_rr_CMGT0,\n+ [TCG_COND_GE] = Isimd_rr_CMGE0,\n+ [TCG_COND_LT] = Isimd_rr_CMLT0,\n+ [TCG_COND_LE] = Isimd_rr_CMLE0,\n };\n \n TCGType type = vecl + TCG_TYPE_V64;\n@@ -2949,169 +2963,173 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,\n break;\n case INDEX_op_add_vec:\n if (is_scalar) {\n- tcg_out_insn(s, 3611, ADD, vece, a0, a1, a2);\n+ tcg_out_insn(s, rrr_e, ADD, vece, a0, a1, a2);\n } else {\n- tcg_out_insn(s, 3616, ADD, is_q, vece, a0, a1, a2);\n+ tcg_out_insn(s, qrrr_e, ADD, is_q, vece, a0, a1, a2);\n }\n break;\n case INDEX_op_sub_vec:\n if (is_scalar) {\n- tcg_out_insn(s, 3611, SUB, vece, a0, a1, a2);\n+ tcg_out_insn(s, rrr_e, SUB, vece, a0, a1, a2);\n } else {\n- tcg_out_insn(s, 3616, SUB, is_q, vece, a0, a1, a2);\n+ tcg_out_insn(s, qrrr_e, SUB, is_q, vece, a0, a1, a2);\n }\n break;\n case INDEX_op_mul_vec:\n- tcg_out_insn(s, 3616, MUL, is_q, vece, a0, a1, a2);\n+ tcg_out_insn(s, qrrr_e, MUL, is_q, vece, a0, a1, a2);\n break;\n case INDEX_op_neg_vec:\n if (is_scalar) {\n- tcg_out_insn(s, 3612, NEG, vece, a0, a1);\n+ tcg_out_insn(s, simd_rr, NEG, vece, a0, a1);\n } else {\n- tcg_out_insn(s, 3617, NEG, is_q, vece, a0, a1);\n+ tcg_out_insn(s, qrr_e, NEG, is_q, vece, a0, a1);\n }\n break;\n case INDEX_op_abs_vec:\n if (is_scalar) {\n- tcg_out_insn(s, 3612, ABS, vece, a0, a1);\n+ tcg_out_insn(s, simd_rr, ABS, vece, a0, a1);\n } else {\n- tcg_out_insn(s, 3617, ABS, is_q, vece, a0, a1);\n+ tcg_out_insn(s, qrr_e, ABS, is_q, vece, a0, a1);\n }\n break;\n case INDEX_op_and_vec:\n if (const_args[2]) {\n is_shimm1632(~a2, &cmode, &imm8);\n if (a0 == a1) {\n- tcg_out_insn(s, 3606, BIC, is_q, a0, 0, cmode, imm8);\n+ tcg_out_insn(s, simd_imm, BIC, is_q, a0, 0, cmode, imm8);\n return;\n }\n- tcg_out_insn(s, 3606, MVNI, is_q, a0, 0, cmode, imm8);\n+ tcg_out_insn(s, simd_imm, MVNI, is_q, a0, 0, cmode, imm8);\n a2 = a0;\n }\n- tcg_out_insn(s, 3616, AND, is_q, 0, a0, a1, a2);\n+ tcg_out_insn(s, qrrr_e, AND, is_q, 0, a0, a1, a2);\n break;\n case INDEX_op_or_vec:\n if (const_args[2]) {\n is_shimm1632(a2, &cmode, &imm8);\n if (a0 == a1) {\n- tcg_out_insn(s, 3606, ORR, is_q, a0, 0, cmode, imm8);\n+ tcg_out_insn(s, simd_imm, ORR, is_q, a0, 0, cmode, imm8);\n return;\n }\n- tcg_out_insn(s, 3606, MOVI, is_q, a0, 0, cmode, imm8);\n+ tcg_out_insn(s, simd_imm, MOVI, is_q, a0, 0, cmode, imm8);\n a2 = a0;\n }\n- tcg_out_insn(s, 3616, ORR, is_q, 0, a0, a1, a2);\n+ tcg_out_insn(s, qrrr_e, ORR, is_q, 0, a0, a1, a2);\n break;\n case INDEX_op_andc_vec:\n if (const_args[2]) {\n is_shimm1632(a2, &cmode, &imm8);\n if (a0 == a1) {\n- tcg_out_insn(s, 3606, BIC, is_q, a0, 0, cmode, imm8);\n+ tcg_out_insn(s, simd_imm, BIC, is_q, a0, 0, cmode, imm8);\n return;\n }\n- tcg_out_insn(s, 3606, MOVI, is_q, a0, 0, cmode, imm8);\n+ tcg_out_insn(s, simd_imm, MOVI, is_q, a0, 0, cmode, imm8);\n a2 = a0;\n }\n- tcg_out_insn(s, 3616, BIC, is_q, 0, a0, a1, a2);\n+ tcg_out_insn(s, qrrr_e, BIC, is_q, 0, a0, a1, a2);\n break;\n case INDEX_op_orc_vec:\n if (const_args[2]) {\n is_shimm1632(~a2, &cmode, &imm8);\n if (a0 == a1) {\n- tcg_out_insn(s, 3606, ORR, is_q, a0, 0, cmode, imm8);\n+ tcg_out_insn(s, simd_imm, ORR, is_q, a0, 0, cmode, imm8);\n return;\n }\n- tcg_out_insn(s, 3606, MVNI, is_q, a0, 0, cmode, imm8);\n+ tcg_out_insn(s, simd_imm, MVNI, is_q, a0, 0, cmode, imm8);\n a2 = a0;\n }\n- tcg_out_insn(s, 3616, ORN, is_q, 0, a0, a1, a2);\n+ tcg_out_insn(s, qrrr_e, ORN, is_q, 0, a0, a1, a2);\n break;\n case INDEX_op_xor_vec:\n- tcg_out_insn(s, 3616, EOR, is_q, 0, a0, a1, a2);\n+ tcg_out_insn(s, qrrr_e, EOR, is_q, 0, a0, a1, a2);\n break;\n case INDEX_op_ssadd_vec:\n if (is_scalar) {\n- tcg_out_insn(s, 3611, SQADD, vece, a0, a1, a2);\n+ tcg_out_insn(s, rrr_e, SQADD, vece, a0, a1, a2);\n } else {\n- tcg_out_insn(s, 3616, SQADD, is_q, vece, a0, a1, a2);\n+ tcg_out_insn(s, qrrr_e, SQADD, is_q, vece, a0, a1, a2);\n }\n break;\n case INDEX_op_sssub_vec:\n if (is_scalar) {\n- tcg_out_insn(s, 3611, SQSUB, vece, a0, a1, a2);\n+ tcg_out_insn(s, rrr_e, SQSUB, vece, a0, a1, a2);\n } else {\n- tcg_out_insn(s, 3616, SQSUB, is_q, vece, a0, a1, a2);\n+ tcg_out_insn(s, qrrr_e, SQSUB, is_q, vece, a0, a1, a2);\n }\n break;\n case INDEX_op_usadd_vec:\n if (is_scalar) {\n- tcg_out_insn(s, 3611, UQADD, vece, a0, a1, a2);\n+ tcg_out_insn(s, rrr_e, UQADD, vece, a0, a1, a2);\n } else {\n- tcg_out_insn(s, 3616, UQADD, is_q, vece, a0, a1, a2);\n+ tcg_out_insn(s, qrrr_e, UQADD, is_q, vece, a0, a1, a2);\n }\n break;\n case INDEX_op_ussub_vec:\n if (is_scalar) {\n- tcg_out_insn(s, 3611, UQSUB, vece, a0, a1, a2);\n+ tcg_out_insn(s, rrr_e, UQSUB, vece, a0, a1, a2);\n } else {\n- tcg_out_insn(s, 3616, UQSUB, is_q, vece, a0, a1, a2);\n+ tcg_out_insn(s, qrrr_e, UQSUB, is_q, vece, a0, a1, a2);\n }\n break;\n case INDEX_op_smax_vec:\n- tcg_out_insn(s, 3616, SMAX, is_q, vece, a0, a1, a2);\n+ tcg_out_insn(s, qrrr_e, SMAX, is_q, vece, a0, a1, a2);\n break;\n case INDEX_op_smin_vec:\n- tcg_out_insn(s, 3616, SMIN, is_q, vece, a0, a1, a2);\n+ tcg_out_insn(s, qrrr_e, SMIN, is_q, vece, a0, a1, a2);\n break;\n case INDEX_op_umax_vec:\n- tcg_out_insn(s, 3616, UMAX, is_q, vece, a0, a1, a2);\n+ tcg_out_insn(s, qrrr_e, UMAX, is_q, vece, a0, a1, a2);\n break;\n case INDEX_op_umin_vec:\n- tcg_out_insn(s, 3616, UMIN, is_q, vece, a0, a1, a2);\n+ tcg_out_insn(s, qrrr_e, UMIN, is_q, vece, a0, a1, a2);\n break;\n case INDEX_op_not_vec:\n- tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1);\n+ tcg_out_insn(s, qrr_e, NOT, is_q, 0, a0, a1);\n break;\n case INDEX_op_shli_vec:\n if (is_scalar) {\n- tcg_out_insn(s, 3609, SHL, a0, a1, a2 + (8 << vece));\n+ tcg_out_insn(s, q_shift, SHL, a0, a1, a2 + (8 << vece));\n } else {\n- tcg_out_insn(s, 3614, SHL, is_q, a0, a1, a2 + (8 << vece));\n+ tcg_out_insn(s, simd_shift_imm, SHL, is_q, a0, a1,\n+ a2 + (8 << vece));\n }\n break;\n case INDEX_op_shri_vec:\n if (is_scalar) {\n- tcg_out_insn(s, 3609, USHR, a0, a1, (16 << vece) - a2);\n+ tcg_out_insn(s, q_shift, USHR, a0, a1, (16 << vece) - a2);\n } else {\n- tcg_out_insn(s, 3614, USHR, is_q, a0, a1, (16 << vece) - a2);\n+ tcg_out_insn(s, simd_shift_imm, USHR, is_q, a0, a1,\n+ (16 << vece) - a2);\n }\n break;\n case INDEX_op_sari_vec:\n if (is_scalar) {\n- tcg_out_insn(s, 3609, SSHR, a0, a1, (16 << vece) - a2);\n+ tcg_out_insn(s, q_shift, SSHR, a0, a1, (16 << vece) - a2);\n } else {\n- tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2);\n+ tcg_out_insn(s, simd_shift_imm, SSHR, is_q, a0, a1,\n+ (16 << vece) - a2);\n }\n break;\n case INDEX_op_aa64_sli_vec:\n if (is_scalar) {\n- tcg_out_insn(s, 3609, SLI, a0, a2, args[3] + (8 << vece));\n+ tcg_out_insn(s, q_shift, SLI, a0, a2, args[3] + (8 << vece));\n } else {\n- tcg_out_insn(s, 3614, SLI, is_q, a0, a2, args[3] + (8 << vece));\n+ tcg_out_insn(s, simd_shift_imm, SLI, is_q, a0, a2,\n+ args[3] + (8 << vece));\n }\n break;\n case INDEX_op_shlv_vec:\n if (is_scalar) {\n- tcg_out_insn(s, 3611, USHL, vece, a0, a1, a2);\n+ tcg_out_insn(s, rrr_e, USHL, vece, a0, a1, a2);\n } else {\n- tcg_out_insn(s, 3616, USHL, is_q, vece, a0, a1, a2);\n+ tcg_out_insn(s, qrrr_e, USHL, is_q, vece, a0, a1, a2);\n }\n break;\n case INDEX_op_aa64_sshl_vec:\n if (is_scalar) {\n- tcg_out_insn(s, 3611, SSHL, vece, a0, a1, a2);\n+ tcg_out_insn(s, rrr_e, SSHL, vece, a0, a1, a2);\n } else {\n- tcg_out_insn(s, 3616, SSHL, is_q, vece, a0, a1, a2);\n+ tcg_out_insn(s, qrrr_e, SSHL, is_q, vece, a0, a1, a2);\n }\n break;\n case INDEX_op_cmp_vec:\n@@ -3123,17 +3141,17 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,\n case TCG_COND_NE:\n if (const_args[2]) {\n if (is_scalar) {\n- tcg_out_insn(s, 3611, CMTST, vece, a0, a1, a1);\n+ tcg_out_insn(s, rrr_e, CMTST, vece, a0, a1, a1);\n } else {\n- tcg_out_insn(s, 3616, CMTST, is_q, vece, a0, a1, a1);\n+ tcg_out_insn(s, qrrr_e, CMTST, is_q, vece, a0, a1, a1);\n }\n } else {\n if (is_scalar) {\n- tcg_out_insn(s, 3611, CMEQ, vece, a0, a1, a2);\n+ tcg_out_insn(s, rrr_e, CMEQ, vece, a0, a1, a2);\n } else {\n- tcg_out_insn(s, 3616, CMEQ, is_q, vece, a0, a1, a2);\n+ tcg_out_insn(s, qrrr_e, CMEQ, is_q, vece, a0, a1, a2);\n }\n- tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a0);\n+ tcg_out_insn(s, qrr_e, NOT, is_q, 0, a0, a0);\n }\n break;\n \n@@ -3146,12 +3164,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,\n break;\n }\n if (is_scalar) {\n- tcg_out_insn(s, 3611, CMTST, vece, a0, a1, a2);\n+ tcg_out_insn(s, rrr_e, CMTST, vece, a0, a1, a2);\n } else {\n- tcg_out_insn(s, 3616, CMTST, is_q, vece, a0, a1, a2);\n+ tcg_out_insn(s, qrrr_e, CMTST, is_q, vece, a0, a1, a2);\n }\n if (cond == TCG_COND_TSTEQ) {\n- tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a0);\n+ tcg_out_insn(s, qrr_e, NOT, is_q, 0, a0, a0);\n }\n break;\n \n@@ -3160,13 +3178,13 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,\n if (is_scalar) {\n insn = cmp0_scalar_insn[cond];\n if (insn) {\n- tcg_out_insn_3612(s, insn, vece, a0, a1);\n+ tcg_out_insn_simd_rr(s, insn, vece, a0, a1);\n break;\n }\n } else {\n insn = cmp0_vec_insn[cond];\n if (insn) {\n- tcg_out_insn_3617(s, insn, is_q, vece, a0, a1);\n+ tcg_out_insn_qrr_e(s, insn, is_q, vece, a0, a1);\n break;\n }\n }\n@@ -3182,7 +3200,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,\n insn = cmp_scalar_insn[cond];\n tcg_debug_assert(insn != 0);\n }\n- tcg_out_insn_3611(s, insn, vece, a0, a1, a2);\n+ tcg_out_insn_rrr_e(s, insn, vece, a0, a1, a2);\n } else {\n insn = cmp_vec_insn[cond];\n if (insn == 0) {\n@@ -3192,7 +3210,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,\n insn = cmp_vec_insn[cond];\n tcg_debug_assert(insn != 0);\n }\n- tcg_out_insn_3616(s, insn, is_q, vece, a0, a1, a2);\n+ tcg_out_insn_qrrr_e(s, insn, is_q, vece, a0, a1, a2);\n }\n break;\n }\n@@ -3202,14 +3220,14 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,\n case INDEX_op_bitsel_vec:\n a3 = args[3];\n if (a0 == a3) {\n- tcg_out_insn(s, 3616, BIT, is_q, 0, a0, a2, a1);\n+ tcg_out_insn(s, qrrr_e, BIT, is_q, 0, a0, a2, a1);\n } else if (a0 == a2) {\n- tcg_out_insn(s, 3616, BIF, is_q, 0, a0, a3, a1);\n+ tcg_out_insn(s, qrrr_e, BIF, is_q, 0, a0, a3, a1);\n } else {\n if (a0 != a1) {\n tcg_out_mov(s, type, a0, a1);\n }\n- tcg_out_insn(s, 3616, BSL, is_q, 0, a0, a2, a3);\n+ tcg_out_insn(s, qrrr_e, BSL, is_q, 0, a0, a2, a3);\n }\n break;\n \n@@ -3447,7 +3465,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)\n tcg_out_bti(s, BTI_C);\n \n /* Push (FP, LR) and allocate space for all saved registers. */\n- tcg_out_insn(s, 3314, STP, TCG_REG_FP, TCG_REG_LR,\n+ tcg_out_insn(s, ldstpair, STP, TCG_REG_FP, TCG_REG_LR,\n TCG_REG_SP, -PUSH_SIZE, 1, 1);\n \n /* Set up frame pointer for canonical unwinding. */\n@@ -3456,11 +3474,11 @@ static void tcg_target_qemu_prologue(TCGContext *s)\n /* Store callee-preserved regs x19..x28. */\n for (r = TCG_REG_X19; r <= TCG_REG_X27; r += 2) {\n int ofs = (r - TCG_REG_X19 + 2) * 8;\n- tcg_out_insn(s, 3314, STP, r, r + 1, TCG_REG_SP, ofs, 1, 0);\n+ tcg_out_insn(s, ldstpair, STP, r, r + 1, TCG_REG_SP, ofs, 1, 0);\n }\n \n /* Make stack space for TCG locals. */\n- tcg_out_insn(s, 3401, SUBI, TCG_TYPE_I64, TCG_REG_SP, TCG_REG_SP,\n+ tcg_out_insn(s, addsub_imm, SUBI, TCG_TYPE_I64, TCG_REG_SP, TCG_REG_SP,\n FRAME_SIZE - PUSH_SIZE);\n \n /* Inform TCG about how to find TCG locals with register, offset, size. */\n@@ -3479,7 +3497,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)\n }\n \n tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);\n- tcg_out_insn(s, 3207, BR, tcg_target_call_iarg_regs[1]);\n+ tcg_out_insn(s, bcond_reg, BR, tcg_target_call_iarg_regs[1]);\n \n /*\n * Return path for goto_ptr. Set return value to 0, a-la exit_tb,\n@@ -3494,19 +3512,19 @@ static void tcg_target_qemu_prologue(TCGContext *s)\n tcg_out_bti(s, BTI_J);\n \n /* Remove TCG locals stack space. */\n- tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_SP, TCG_REG_SP,\n+ tcg_out_insn(s, addsub_imm, ADDI, TCG_TYPE_I64, TCG_REG_SP, TCG_REG_SP,\n FRAME_SIZE - PUSH_SIZE);\n \n /* Restore registers x19..x28. */\n for (r = TCG_REG_X19; r <= TCG_REG_X27; r += 2) {\n int ofs = (r - TCG_REG_X19 + 2) * 8;\n- tcg_out_insn(s, 3314, LDP, r, r + 1, TCG_REG_SP, ofs, 1, 0);\n+ tcg_out_insn(s, ldstpair, LDP, r, r + 1, TCG_REG_SP, ofs, 1, 0);\n }\n \n /* Pop (FP, LR), restore SP to previous frame. */\n- tcg_out_insn(s, 3314, LDP, TCG_REG_FP, TCG_REG_LR,\n+ tcg_out_insn(s, ldstpair, LDP, TCG_REG_FP, TCG_REG_LR,\n TCG_REG_SP, PUSH_SIZE, 0, 1);\n- tcg_out_insn(s, 3207, RET, TCG_REG_LR);\n+ tcg_out_insn(s, bcond_reg, RET, TCG_REG_LR);\n }\n \n static void tcg_out_tb_start(TCGContext *s)\n","prefixes":["PULL","1/3"]}