{"id":2230471,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230471/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429183310.12455-8-harshpb@linux.ibm.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260429183310.12455-8-harshpb@linux.ibm.com>","date":"2026-04-29T18:32:57","name":"[PULL,07/13] pnv/mpipl: Write the preserved CPU and MDRT state","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"604c160ec06a95a434224c2e9842745697c6bc5c","submitter":{"id":85411,"url":"http://patchwork.ozlabs.org/api/1.1/people/85411/?format=json","name":"Harsh Prateek Bora","email":"harshpb@linux.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429183310.12455-8-harshpb@linux.ibm.com/mbox/","series":[{"id":502132,"url":"http://patchwork.ozlabs.org/api/1.1/series/502132/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502132","date":"2026-04-29T18:32:53","name":"[PULL,01/13] ppc/pnv: Move SBE host doorbell function to top of file","version":1,"mbox":"http://patchwork.ozlabs.org/series/502132/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230471/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230471/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 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:mime-version:references:subject:to; s=pp1; bh=yldXvNtGi4Nx79HXk\n sBy+Ox3vRjtxXUTxKqLeD78E8Q=; b=U93k8m1uwGTDst4Q1CoihmanJYJt5W3Z9\n w04r+nF7rEeHa/1QM04OxpF0ahIdBmJ8NnWR2XGyK0v08AKwEQBVvrRWwPIAGFiT\n Kmf55Ly1Tk/mR6ZFos5eNczG++Yc3LUJPRDE1v9o5ya39wqVupNUK0vcj6q6L0i7\n Lf4DViQ4YwfoitRWzeXsvRpgPZbJJsv0vUcblqmpZ8MXuo2jt9KhZd7jPQ7DaW4y\n Q5hI8njsLuaOCw6QSdpMTKTl83Q+18En8ixZjpCxlKbEsbyRLVE3Z3IQlnktneSo\n zwWSG/bbQQQXVGfNNCTuKc9ecUxkpnpG5I67fEseCD68DVSblbY1w==","From":"Harsh Prateek Bora ","To":"qemu-devel@nongnu.org","Cc":"Aditya Gupta ,\n Hari Bathini ,\n Sourabh Jain ,\n Shivang Upadhyay ","Subject":"[PULL 07/13] pnv/mpipl: Write the preserved CPU and MDRT state","Date":"Thu, 30 Apr 2026 00:02:57 +0530","Message-ID":"<20260429183310.12455-8-harshpb@linux.ibm.com>","X-Mailer":"git-send-email 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helo=mx0a-001b2d01.pphosted.com","X-Spam_score_int":"-26","X-Spam_score":"-2.7","X-Spam_bar":"--","X-Spam_report":"(-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7,\n RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Aditya Gupta \n\nLogic for preserving the CPU registers and memory regions has been done\nin previous patches.\n\nWrite those data at the relevant memory address, such as PROC_DUMP_AREA\nfor CPU registers, and MDRT for preserved memory regions.\n\nAlso export \"mpipl-boot\" device tree node, for kernel to know that it's\na 'dump active' boot\n\nReviewed-by: Hari Bathini \nReviewed-by: Sourabh Jain \nSigned-off-by: Aditya Gupta \nTested-by: Shivang Upadhyay \nLink: https://lore.kernel.org/qemu-devel/20260424083837.214947-8-adityag@linux.ibm.com\nSigned-off-by: Harsh Prateek Bora \n---\n include/hw/ppc/pnv.h | 1 +\n hw/ppc/pnv.c | 39 +++++++++++-\n hw/ppc/pnv_mpipl.c | 140 +++++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 179 insertions(+), 1 deletion(-)","diff":"diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h\nindex 19c7170e74..f8234fb3cd 100644\n--- a/include/hw/ppc/pnv.h\n+++ b/include/hw/ppc/pnv.h\n@@ -296,5 +296,6 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);\n \n /* MPIPL helpers */\n void do_mpipl_preserve(PnvMachineState *pnv);\n+bool do_mpipl_write(PnvMachineState *pnv);\n \n #endif /* PPC_PNV_H */\ndiff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c\nindex 09b69c355a..48f49bef82 100644\n--- a/hw/ppc/pnv.c\n+++ b/hw/ppc/pnv.c\n@@ -750,10 +750,47 @@ static void pnv_reset(MachineState *machine, ResetType type)\n {\n PnvMachineState *pnv = PNV_MACHINE(machine);\n void *fdt;\n+ int node_offset;\n+ bool mpipl_write_succeeded = false;\n \n qemu_devices_reset(type);\n \n- if (!pnv->mpipl_state.is_next_boot_mpipl) {\n+ /*\n+ * Only on success of writing MPIPL data will the next boot be provided\n+ * \"mpipl-boot\" property in device tree\n+ * Otherwise boot like a normal non-MPIPL boot\n+ */\n+ if (pnv->mpipl_state.is_next_boot_mpipl) {\n+ /* Write the preserved MDRT and CPU State Data */\n+ mpipl_write_succeeded = do_mpipl_write(pnv);\n+ }\n+\n+ /*\n+ * If it's a MPIPL boot, add the \"mpipl-boot\" property, and reset the\n+ * boolean for MPIPL boot for next boot\n+ */\n+ if (mpipl_write_succeeded) {\n+ void *fdt_copy = g_malloc0(FDT_MAX_SIZE);\n+\n+ /* Create a writable copy of the fdt */\n+ _FDT((fdt_open_into(fdt, fdt_copy, FDT_MAX_SIZE)));\n+\n+ node_offset = fdt_path_offset(fdt_copy, \"/ibm,opal/dump\");\n+ _FDT((fdt_appendprop_u64(fdt_copy, node_offset, \"mpipl-boot\", 1)));\n+\n+ /* Update the fdt, and free the original fdt */\n+ if (fdt != machine->fdt) {\n+ /*\n+ * Only free the fdt if it's not machine->fdt, to prevent\n+ * double free, since we already free machine->fdt later\n+ */\n+ g_free(fdt);\n+ }\n+ fdt = fdt_copy;\n+\n+ /* This boot is an MPIPL, reset the boolean for next boot */\n+ pnv->mpipl_state.is_next_boot_mpipl = false;\n+ } else {\n /*\n * Set the \"Thread Register State Entry Size\", so that firmware can\n * allocate enough memory to capture CPU state in the event of a\ndiff --git a/hw/ppc/pnv_mpipl.c b/hw/ppc/pnv_mpipl.c\nindex 308948b829..f5b228f5ba 100644\n--- a/hw/ppc/pnv_mpipl.c\n+++ b/hw/ppc/pnv_mpipl.c\n@@ -20,6 +20,8 @@\n (pnv->mpipl_state.skiboot_base + MDST_TABLE_OFF)\n #define MDDT_TABLE_RELOCATED \\\n (pnv->mpipl_state.skiboot_base + MDDT_TABLE_OFF)\n+#define MDRT_TABLE_RELOCATED \\\n+ (pnv->mpipl_state.skiboot_base + MDRT_TABLE_OFF)\n #define PROC_DUMP_RELOCATED \\\n (pnv->mpipl_state.skiboot_base + PROC_DUMP_AREA_OFF)\n \n@@ -320,6 +322,139 @@ static bool pnv_mpipl_preserve_cpu_state(PnvMachineState *pnv)\n return true;\n }\n \n+/*\n+ * Write the preserved CPU state data in Processor Dump Area (PROC_DUMP_AREA)\n+ *\n+ * Returns true if everything went fine, else false for any error\n+ */\n+static bool pnv_mpipl_write_cpu_state(PnvMachineState *pnv)\n+{\n+ MpiplProcDumpArea *proc_area = &pnv->mpipl_state.proc_area;\n+ MpiplPreservedCPUState *cpu_state = pnv->mpipl_state.cpu_states;\n+ const uint32_t num_cpu_states = pnv->mpipl_state.num_cpu_states;\n+ hwaddr next_regentries_hdr;\n+ AddressSpace *default_as = &address_space_memory;\n+ MemTxResult io_result;\n+ MemTxAttrs attrs;\n+\n+ /* Mark the memory transactions as privileged memory access */\n+ attrs.user = 0;\n+ attrs.memory = 1;\n+\n+ if (be32_to_cpu(proc_area->alloc_size) <\n+ (num_cpu_states * sizeof(MpiplPreservedCPUState))) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"MPIPL: Size of buffer allocate by skiboot (%u bytes) is not\"\n+ \"enough to save all CPUs registers needed (%zu bytes)\",\n+ be32_to_cpu(proc_area->alloc_size),\n+ num_cpu_states * sizeof(MpiplPreservedCPUState));\n+\n+ return false;\n+ }\n+\n+ proc_area->version = PROC_DUMP_AREA_VERSION_P9;\n+\n+ /*\n+ * This is the stride kernel/firmware should use to jump from a\n+ * register entries header to next CPU's header\n+ */\n+ proc_area->thread_size = cpu_to_be32(sizeof(MpiplPreservedCPUState));\n+\n+ /* Write the header and register entries for each CPU */\n+ next_regentries_hdr = be64_to_cpu(proc_area->alloc_addr) & (~HRMOR_BIT);\n+ for (int i = 0; i < num_cpu_states; ++i) {\n+ io_result = address_space_write(default_as, next_regentries_hdr, attrs,\n+ &cpu_state->hdr, sizeof(MpiplRegDataHdr));\n+ if (io_result != MEMTX_OK) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"MPIPL: Failed to write RegEntries Header\\n\");\n+ return false;\n+ }\n+\n+ io_result = address_space_write(default_as,\n+ next_regentries_hdr + sizeof(MpiplRegDataHdr), attrs,\n+ &cpu_state->reg_entries,\n+ NUM_REGS_PER_CPU * (sizeof(MpiplRegEntry)));\n+ if (io_result != MEMTX_OK) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"MPIPL: Failed to write Register Entries\\n\");\n+ return false;\n+ }\n+\n+ /*\n+ * According to HDAT section:\n+ * \"15.3.1.5 Architected Register Data content\":\n+ *\n+ * The next register entries header will be at current header +\n+ * \"Thread Register State Entry size\"\n+ *\n+ * Note: proc_area.thread_size == sizeof(MpiplPreservedCPUState)\n+ */\n+ next_regentries_hdr += sizeof(MpiplPreservedCPUState);\n+ ++cpu_state;\n+ }\n+\n+ /* Point the destination address to the preserved memory region */\n+ proc_area->dest_addr = proc_area->alloc_addr;\n+ proc_area->act_size = cpu_to_be32(num_cpu_states *\n+ sizeof(MpiplPreservedCPUState));\n+\n+ io_result = address_space_write(default_as, PROC_DUMP_AREA_OFF, attrs,\n+ proc_area, sizeof(MpiplProcDumpArea));\n+ if (io_result != MEMTX_OK) {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"MPIPL: Failed to write Register Entries\\n\");\n+ return false;\n+ }\n+\n+ return true;\n+}\n+\n+/*\n+ * Write the preserved MDRT table, representing preserved memory regions\n+ *\n+ * Returns true if everything went fine, else false for any error\n+ */\n+static bool pnv_mpipl_write_mdrt(PnvMachineState *pnv)\n+{\n+ MpiplPreservedState *state = &pnv->mpipl_state;\n+ AddressSpace *default_as = &address_space_memory;\n+ MemTxResult io_result;\n+ MemTxAttrs attrs;\n+\n+ /* Mark the memory transactions as privileged memory access */\n+ attrs.user = 0;\n+ attrs.memory = 1;\n+\n+ /*\n+ * Generally writes from platform during MPIPL don't go to a relocated\n+ * skiboot address\n+ *\n+ * Though for MDRT we are doing so, as this is the address skiboot\n+ * considers by default for MDRT\n+ *\n+ * MDRT/MDST/MDDT base addresses are actually meant to be shared by\n+ * platform in SPIRA structures.\n+ *\n+ * Not implementing SPIRA as it increases complexity for no gains.\n+ * Using the default address skiboot expects for MDRT, which is the\n+ * relocated MDRT, hence writing to it\n+ *\n+ * Other tables like MDST/MDDT should not be written to relocated\n+ * addresses, as skiboot will overwrite anything from SKIBOOT_BASE till\n+ * SKIBOOT_BASE+SKIBOOT_SIZE (which is 0x30000000-0x31c00000 by default)\n+ */\n+ io_result = address_space_write(default_as, MDRT_TABLE_RELOCATED, attrs,\n+ state->mdrt_table,\n+ state->num_mdrt_entries * sizeof(MdrtTableEntry));\n+ if (io_result != MEMTX_OK) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"MPIPL: Failed to write MDRT table\\n\");\n+ return false;\n+ }\n+\n+ return true;\n+}\n+\n void do_mpipl_preserve(PnvMachineState *pnv)\n {\n pause_all_vcpus();\n@@ -340,3 +475,8 @@ void do_mpipl_preserve(PnvMachineState *pnv)\n */\n qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);\n }\n+\n+bool do_mpipl_write(PnvMachineState *pnv)\n+{\n+ return pnv_mpipl_write_mdrt(pnv) && pnv_mpipl_write_cpu_state(pnv);\n+}\n","prefixes":["PULL","07/13"]}