{"id":2230468,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230468/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429183310.12455-13-harshpb@linux.ibm.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260429183310.12455-13-harshpb@linux.ibm.com>","date":"2026-04-29T18:33:02","name":"[PULL,12/13] ppc/pnv: Add a nest MMU model","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"bccc00852ae3ed21d02c748c0f8d1b96fe91bdda","submitter":{"id":85411,"url":"http://patchwork.ozlabs.org/api/1.1/people/85411/?format=json","name":"Harsh Prateek Bora","email":"harshpb@linux.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429183310.12455-13-harshpb@linux.ibm.com/mbox/","series":[{"id":502132,"url":"http://patchwork.ozlabs.org/api/1.1/series/502132/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502132","date":"2026-04-29T18:32:53","name":"[PULL,01/13] ppc/pnv: Move SBE host doorbell function to top of file","version":1,"mbox":"http://patchwork.ozlabs.org/series/502132/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230468/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230468/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=Lw1lLyKr;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc\n :content-transfer-encoding:date:from:in-reply-to:message-id\n :mime-version:references:subject:to; s=pp1; bh=gUK8qI+cFr+8wrktg\n 5ODjP3hFeZAj0T0v/OF5jVh3Iw=; b=Lw1lLyKr1JRl60cCpEYfv/YRf5dtLUuta\n gGHX/Y8Zyi2BuQdeM4mFcSs3Iy4DCPXMEFdd1kSXQmGL9tKVxoncsqGNvHZBEpCm\n gXqEe2hVVBre5Wv0S56yN5W4Lml1GH+k4iialQiViZBeGFGjMcXxxnhHARHCP5vf\n cqcoQ6VNrQu/RQmlN8t53GQTdval4x3mb53aTwAsowWZxCgZxXqsEu9OEiLciQHf\n bNxmyvmDFdoYnM9Zl3nknhoTwtE/kqsnROhytI45z8P8HGGm4mjzEdJ4NorGIW7B\n goPLPOhTP/TwayPlJQJdI7ByseKRwgl5PY8Gg1fT9krv+pENMPHRA==","From":"Harsh Prateek Bora ","To":"qemu-devel@nongnu.org","Cc":"Caleb Schlossin ,\n Chalapathi V ,\n Glenn Miles ,\n Frederic Barrat ,\n Aditya Gupta ","Subject":"[PULL 12/13] ppc/pnv: Add a nest MMU model","Date":"Thu, 30 Apr 2026 00:03:02 +0530","Message-ID":"<20260429183310.12455-13-harshpb@linux.ibm.com>","X-Mailer":"git-send-email 2.52.0","In-Reply-To":"<20260429183310.12455-1-harshpb@linux.ibm.com>","References":"<20260429183310.12455-1-harshpb@linux.ibm.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-TM-AS-GCONF":"00","X-Proofpoint-GUID":"fOnATU-HpktBP_OYrJHGUqHKawoOejSD","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDI5MDE4NCBTYWx0ZWRfXwkT0oz8JCzJq\n Me4HQO7J6HLcpcDH5qGWGOeo6KZSyurfvHxtgzbB9RGv5/LNsEUOGx8lumnO34et7ThzNt2PJCF\n WcU5L9eXQ9z7B4TfPrOhSWutoGB2ayBQ0b35RS26xUN3iLdbMu16DQr4Od6EtZWGpVsRdoE/xO7\n 6ZSe9d3QPo2mSfq4M9hJc1vbAorkD/q4A0h6cNnmpLsQzLpcrbAO5rmIC4SJjVtWwYw06Vft+Qb\n bWe/ws2FzPfEuPPsK/HuLBnfPSX5jQsNtgVJwvHwJjWT+diBorcxrS6bCyPrBFqC5PAxWSI2k3R\n MJ9z7QStw5EKlPe1znZtULH6+sHPyp9ZTe7ClWPEDwMvYFUNWNmwRl97gqj9zVeZ7eHjppTrncW\n jIpsQrE7zCJHxpXeEpMvwfX17hYh2+wSoKS8Jq65bdZ1mzcgSazQ6ztCQLVFxNSXdNSfn+EQbwQ\n 79Pu88QbZwBxva4DV4A==","X-Authority-Analysis":"v=2.4 cv=Kc7idwYD c=1 sm=1 tr=0 ts=69f24f1e cx=c_pps\n a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17\n a=A5OVakUREuEA:10 a=f7IdgyKtn90A:10 a=VkNPw1HP01LnGYTKEx00:22\n a=RnoormkPH1_aCDwRdu11:22 a=uAbxVGIbfxUO_5tXvNgY:22 a=VwQbUJbxAAAA:8\n a=VnNF1IyMAAAA:8 a=gBQiksIdkjhXAVLJLEgA:9","X-Proofpoint-ORIG-GUID":"fOnATU-HpktBP_OYrJHGUqHKawoOejSD","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-29_01,2026-04-28_01,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n clxscore=1015 phishscore=0 bulkscore=0 adultscore=0 spamscore=0\n malwarescore=0 impostorscore=0 priorityscore=1501 lowpriorityscore=0\n suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000\n definitions=main-2604290184","Received-SPF":"pass client-ip=148.163.156.1;\n envelope-from=harshpb@linux.ibm.com;\n helo=mx0a-001b2d01.pphosted.com","X-Spam_score_int":"-26","X-Spam_score":"-2.7","X-Spam_bar":"--","X-Spam_report":"(-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7,\n RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Caleb Schlossin \n\nThe nest MMU is used for translations needed by I/O subsystems\non Power10. The nest is the shared, on-chip infrastructure\nthat connects CPU cores, memory controllers, and I/O.\n\nThis patch sets up a basic skeleton with its xscom\narea, mapping both needed xscom regions. Support required\nfor PowerVM bringup.\n\nUse Power9 property for device tree to allow OPAL to\nwork with Power9 and Power10.\n\nReviewed-by: Chalapathi V \nReviewed-by: Glenn Miles \nSigned-off-by: Frederic Barrat \nSigned-off-by: Chalapathi V \nSigned-off-by: Caleb Schlossin \nReviewed-by: Aditya Gupta \nLink: https://lore.kernel.org/qemu-devel/20260120150139.714805-1-calebs@linux.ibm.com\nSigned-off-by: Harsh Prateek Bora \n---\n include/hw/ppc/pnv_chip.h | 3 +\n include/hw/ppc/pnv_nmmu.h | 28 ++++++++\n include/hw/ppc/pnv_xscom.h | 4 ++\n hw/ppc/pnv.c | 20 ++++++\n hw/ppc/pnv_nmmu.c | 132 +++++++++++++++++++++++++++++++++++++\n hw/ppc/meson.build | 1 +\n 6 files changed, 188 insertions(+)\n create mode 100644 include/hw/ppc/pnv_nmmu.h\n create mode 100644 hw/ppc/pnv_nmmu.c","diff":"diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h\nindex ea47c97dd3..8ef75fdcca 100644\n--- a/include/hw/ppc/pnv_chip.h\n+++ b/include/hw/ppc/pnv_chip.h\n@@ -7,6 +7,7 @@\n #include \"hw/ppc/pnv_core.h\"\n #include \"hw/ppc/pnv_homer.h\"\n #include \"hw/ppc/pnv_n1_chiplet.h\"\n+#include \"hw/ppc/pnv_nmmu.h\"\n #include \"hw/ssi/pnv_spi.h\"\n #include \"hw/ppc/pnv_lpc.h\"\n #include \"hw/ppc/pnv_occ.h\"\n@@ -126,6 +127,8 @@ struct Pnv10Chip {\n PnvN1Chiplet n1_chiplet;\n #define PNV10_CHIP_MAX_PIB_SPIC 6\n PnvSpi pib_spic[PNV10_CHIP_MAX_PIB_SPIC];\n+#define PNV10_CHIP_MAX_NMMU 2\n+ PnvNMMU nmmu[PNV10_CHIP_MAX_NMMU];\n \n uint32_t nr_quads;\n PnvQuad *quads;\ndiff --git a/include/hw/ppc/pnv_nmmu.h b/include/hw/ppc/pnv_nmmu.h\nnew file mode 100644\nindex 0000000000..d3ba46ecf4\n--- /dev/null\n+++ b/include/hw/ppc/pnv_nmmu.h\n@@ -0,0 +1,28 @@\n+/*\n+ * QEMU PowerPC nest MMU model\n+ *\n+ * Copyright (c) 2025, IBM Corporation.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ *\n+ * This code is licensed under the GPL version 2 or later. See the\n+ * COPYING file in the top-level directory.\n+ */\n+\n+#ifndef PPC_PNV_NMMU_H\n+#define PPC_PNV_NMMU_H\n+\n+#define TYPE_PNV_NMMU \"pnv-nmmu\"\n+#define PNV_NMMU(obj) OBJECT_CHECK(PnvNMMU, (obj), TYPE_PNV_NMMU)\n+\n+typedef struct PnvNMMU {\n+ DeviceState parent;\n+\n+ struct PnvChip *chip;\n+\n+ MemoryRegion xscom_regs;\n+ uint32_t nmmu_id;\n+ uint64_t ptcr;\n+} PnvNMMU;\n+\n+#endif /*PPC_PNV_NMMU_H */\ndiff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h\nindex 610b075a27..6dab803d1f 100644\n--- a/include/hw/ppc/pnv_xscom.h\n+++ b/include/hw/ppc/pnv_xscom.h\n@@ -196,6 +196,10 @@ struct PnvXScomInterfaceClass {\n #define PNV10_XSCOM_N1_PB_SCOM_ES_BASE 0x3011300\n #define PNV10_XSCOM_N1_PB_SCOM_ES_SIZE 0x100\n \n+#define PNV10_XSCOM_NEST0_MMU_BASE 0x2010c40\n+#define PNV10_XSCOM_NEST1_MMU_BASE 0x3010c40\n+#define PNV10_XSCOM_NMMU_SIZE 0x20\n+\n #define PNV10_XSCOM_PEC_NEST_BASE 0x3011800 /* index goes downwards ... */\n #define PNV10_XSCOM_PEC_NEST_SIZE 0x100\n \ndiff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c\nindex 89096f9a84..9ed918fa6a 100644\n--- a/hw/ppc/pnv.c\n+++ b/hw/ppc/pnv.c\n@@ -2297,6 +2297,11 @@ static void pnv_chip_power10_instance_init(Object *obj)\n TYPE_PNV_PHB5_PEC);\n }\n \n+ for (i = 0; i < PNV10_CHIP_MAX_NMMU; i++) {\n+ object_initialize_child(obj, \"nmmu[*]\", &chip10->nmmu[i],\n+ TYPE_PNV_NMMU);\n+ }\n+\n for (i = 0; i < pcc->i2c_num_engines; i++) {\n object_initialize_child(obj, \"i2c[*]\", &chip10->i2c[i], TYPE_PNV_I2C);\n }\n@@ -2511,6 +2516,21 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)\n pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_ES_BASE,\n &chip10->n1_chiplet.xscom_pb_es_mr);\n \n+ /* nest0/1 MMU */\n+ for (i = 0; i < PNV10_CHIP_MAX_NMMU; i++) {\n+ object_property_set_int(OBJECT(&chip10->nmmu[i]), \"nmmu_id\",\n+ i , &error_fatal);\n+ object_property_set_link(OBJECT(&chip10->nmmu[i]), \"chip\",\n+ OBJECT(chip), &error_abort);\n+ if (!qdev_realize(DEVICE(&chip10->nmmu[i]), NULL, errp)) {\n+ return;\n+ }\n+ }\n+ pnv_xscom_add_subregion(chip, PNV10_XSCOM_NEST0_MMU_BASE,\n+ &chip10->nmmu[0].xscom_regs);\n+ pnv_xscom_add_subregion(chip, PNV10_XSCOM_NEST1_MMU_BASE,\n+ &chip10->nmmu[1].xscom_regs);\n+\n /* PHBs */\n pnv_chip_power10_phb_realize(chip, &local_err);\n if (local_err) {\ndiff --git a/hw/ppc/pnv_nmmu.c b/hw/ppc/pnv_nmmu.c\nnew file mode 100644\nindex 0000000000..c1b00bac89\n--- /dev/null\n+++ b/hw/ppc/pnv_nmmu.c\n@@ -0,0 +1,132 @@\n+/*\n+ * QEMU PowerPC nest MMU model\n+ *\n+ * Copyright (c) 2025, IBM Corporation.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ *\n+ * This code is licensed under the GPL version 2 or later. See the\n+ * COPYING file in the top-level directory.\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"qemu/log.h\"\n+#include \"hw/core/qdev-properties.h\"\n+\n+#include \"hw/ppc/pnv.h\"\n+#include \"hw/ppc/pnv_xscom.h\"\n+#include \"hw/ppc/pnv_nmmu.h\"\n+#include \"hw/ppc/fdt.h\"\n+\n+#include \n+\n+#define NMMU_XLAT_CTL_PTCR 0xb\n+\n+static uint64_t pnv_nmmu_xscom_read(void *opaque, hwaddr addr, unsigned size)\n+{\n+ PnvNMMU *nmmu = PNV_NMMU(opaque);\n+ int reg = addr >> 3;\n+ uint64_t val;\n+\n+ if (reg == NMMU_XLAT_CTL_PTCR) {\n+ val = nmmu->ptcr;\n+ } else {\n+ val = 0xffffffffffffffffull;\n+ qemu_log_mask(LOG_UNIMP, \"nMMU: xscom read at 0x%\" PRIx32 \"\\n\", reg);\n+ }\n+ return val;\n+}\n+\n+static void pnv_nmmu_xscom_write(void *opaque, hwaddr addr,\n+ uint64_t val, unsigned size)\n+{\n+ PnvNMMU *nmmu = PNV_NMMU(opaque);\n+ int reg = addr >> 3;\n+\n+ if (reg == NMMU_XLAT_CTL_PTCR) {\n+ nmmu->ptcr = val;\n+ } else {\n+ qemu_log_mask(LOG_UNIMP, \"nMMU: xscom write at 0x%\" PRIx32 \"\\n\", reg);\n+ }\n+}\n+\n+static const MemoryRegionOps pnv_nmmu_xscom_ops = {\n+ .read = pnv_nmmu_xscom_read,\n+ .write = pnv_nmmu_xscom_write,\n+ .valid.min_access_size = 8,\n+ .valid.max_access_size = 8,\n+ .impl.min_access_size = 8,\n+ .impl.max_access_size = 8,\n+ .endianness = DEVICE_BIG_ENDIAN,\n+};\n+\n+static void pnv_nmmu_realize(DeviceState *dev, Error **errp)\n+{\n+ PnvNMMU *nmmu = PNV_NMMU(dev);\n+\n+ assert(nmmu->chip);\n+\n+ /* NMMU xscom region */\n+ pnv_xscom_region_init(&nmmu->xscom_regs, OBJECT(nmmu),\n+ &pnv_nmmu_xscom_ops, nmmu,\n+ \"xscom-nmmu\",\n+ PNV10_XSCOM_NMMU_SIZE);\n+}\n+\n+static int pnv_nmmu_dt_xscom(PnvXScomInterface *dev, void *fdt,\n+ int offset)\n+{\n+ PnvNMMU *nmmu = PNV_NMMU(dev);\n+ char *name;\n+ int nmmu_offset;\n+ const char compat[] = \"ibm,power9-nest-mmu\";\n+ uint32_t nmmu_pcba = PNV10_XSCOM_NEST0_MMU_BASE + nmmu->nmmu_id * 0x1000000;\n+ uint32_t reg[2] = {\n+ cpu_to_be32(nmmu_pcba),\n+ cpu_to_be32(PNV10_XSCOM_NMMU_SIZE)\n+ };\n+\n+ name = g_strdup_printf(\"nmmu@%x\", nmmu_pcba);\n+ nmmu_offset = fdt_add_subnode(fdt, offset, name);\n+ _FDT(nmmu_offset);\n+ g_free(name);\n+\n+ _FDT(fdt_setprop(fdt, nmmu_offset, \"reg\", reg, sizeof(reg)));\n+ _FDT(fdt_setprop(fdt, nmmu_offset, \"compatible\", compat, sizeof(compat)));\n+ return 0;\n+}\n+\n+static const Property pnv_nmmu_properties[] = {\n+ DEFINE_PROP_UINT32(\"nmmu_id\", PnvNMMU, nmmu_id, 0),\n+ DEFINE_PROP_LINK(\"chip\", PnvNMMU, chip, TYPE_PNV_CHIP, PnvChip *),\n+};\n+\n+static void pnv_nmmu_class_init(ObjectClass *klass, const void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(klass);\n+ PnvXScomInterfaceClass *xscomc = PNV_XSCOM_INTERFACE_CLASS(klass);\n+\n+ xscomc->dt_xscom = pnv_nmmu_dt_xscom;\n+\n+ dc->desc = \"PowerNV nest MMU\";\n+ dc->realize = pnv_nmmu_realize;\n+ device_class_set_props(dc, pnv_nmmu_properties);\n+}\n+\n+static const TypeInfo pnv_nmmu_info = {\n+ .name = TYPE_PNV_NMMU,\n+ .parent = TYPE_DEVICE,\n+ .instance_size = sizeof(PnvNMMU),\n+ .class_init = pnv_nmmu_class_init,\n+ .interfaces = (InterfaceInfo[]) {\n+ { TYPE_PNV_XSCOM_INTERFACE },\n+ { }\n+ }\n+};\n+\n+static void pnv_nmmu_register_types(void)\n+{\n+ type_register_static(&pnv_nmmu_info);\n+}\n+\n+type_init(pnv_nmmu_register_types);\ndiff --git a/hw/ppc/meson.build b/hw/ppc/meson.build\nindex c61fba4ec8..37aa535db2 100644\n--- a/hw/ppc/meson.build\n+++ b/hw/ppc/meson.build\n@@ -57,6 +57,7 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files(\n 'pnv_nest_pervasive.c',\n 'pnv_n1_chiplet.c',\n 'pnv_mpipl.c',\n+ 'pnv_nmmu.c'\n ))\n # PowerPC 4xx boards\n ppc_ss.add(when: 'CONFIG_PPC405', if_true: files(\n","prefixes":["PULL","12/13"]}