{"id":2230456,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230456/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/20260429183143.4146806-1-mmatti@linux.ibm.com/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/1.1/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260429183143.4146806-1-mmatti@linux.ibm.com>","date":"2026-04-29T18:31:43","name":"rs6000: Builtins for ECC cryptography instructions [RFC02669]","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"92fc917ee26c2384414a124151de2935311a8ce7","submitter":{"id":86304,"url":"http://patchwork.ozlabs.org/api/1.1/people/86304/?format=json","name":"Manjunath S Matti","email":"mmatti@linux.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/20260429183143.4146806-1-mmatti@linux.ibm.com/mbox/","series":[{"id":502130,"url":"http://patchwork.ozlabs.org/api/1.1/series/502130/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=502130","date":"2026-04-29T18:31:43","name":"rs6000: Builtins for ECC cryptography instructions [RFC02669]","version":1,"mbox":"http://patchwork.ozlabs.org/series/502130/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230456/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230456/checks/","tags":{},"headers":{"Return-Path":"<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=kLH4Gd2O;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)","sourceware.org;\n\tdkim=pass (2048-bit key,\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=kLH4Gd2O","sourceware.org;\n dmarc=none (p=none dis=none) header.from=linux.ibm.com","sourceware.org;\n spf=none smtp.mailfrom=kubota.pok.stglabs.ibm.com","server2.sourceware.org;\n arc=none smtp.remote-ip=148.163.156.1"],"Received":["from vm01.sourceware.org (vm01.sourceware.org\n [IPv6:2620:52:6:3111::32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5Qrs1ZGTz1yHX\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 30 Apr 2026 04:32:27 +1000 (AEST)","from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id B925D4B920DB\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 29 Apr 2026 18:32:25 +0000 (GMT)","from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n [148.163.156.1])\n by sourceware.org (Postfix) with ESMTPS id 9748A4BB58F3\n for <gcc-patches@gcc.gnu.org>; Wed, 29 Apr 2026 18:31:53 +0000 (GMT)","from pps.filterd (m0360083.ppops.net [127.0.0.1])\n by mx0a-001b2d01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63T9pbjs3108202; Wed, 29 Apr 2026 18:31:52 GMT","from ppma11.dal12v.mail.ibm.com\n (db.9e.1632.ip4.static.sl-reverse.com [50.22.158.219])\n by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 4drn44v614-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n Wed, 29 Apr 2026 18:31:52 +0000 (GMT)","from pps.filterd (ppma11.dal12v.mail.ibm.com [127.0.0.1])\n by ppma11.dal12v.mail.ibm.com (8.18.1.7/8.18.1.7) with ESMTP id\n 63TINkYf004842;\n Wed, 29 Apr 2026 18:31:51 GMT","from smtprelay03.wdc07v.mail.ibm.com ([172.16.1.70])\n by ppma11.dal12v.mail.ibm.com (PPS) with ESMTPS id 4dsamyfb9c-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n Wed, 29 Apr 2026 18:31:51 +0000 (GMT)","from smtpav06.dal12v.mail.ibm.com (smtpav06.dal12v.mail.ibm.com\n [10.241.53.105])\n by smtprelay03.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id\n 63TIVM1j31261190\n (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK);\n Wed, 29 Apr 2026 18:31:22 GMT","from smtpav06.dal12v.mail.ibm.com (unknown [127.0.0.1])\n by IMSVA (Postfix) with ESMTP id 5B7985805E;\n Wed, 29 Apr 2026 18:31:49 +0000 (GMT)","from smtpav06.dal12v.mail.ibm.com (unknown [127.0.0.1])\n by IMSVA (Postfix) with ESMTP id 3238358043;\n Wed, 29 Apr 2026 18:31:49 +0000 (GMT)","from kubota.pok.stglabs.ibm.com (unknown [9.114.39.181])\n by smtpav06.dal12v.mail.ibm.com (Postfix) with ESMTPS;\n Wed, 29 Apr 2026 18:31:49 +0000 (GMT)","by kubota.pok.stglabs.ibm.com (Postfix, from userid 19540)\n id 4746380BA845; Wed, 29 Apr 2026 13:31:48 -0500 (EST)"],"DKIM-Filter":["OpenDKIM Filter v2.11.0 sourceware.org B925D4B920DB","OpenDKIM Filter v2.11.0 sourceware.org 9748A4BB58F3"],"DMARC-Filter":"OpenDMARC Filter v1.4.2 sourceware.org 9748A4BB58F3","ARC-Filter":"OpenARC Filter v1.0.0 sourceware.org 9748A4BB58F3","ARC-Seal":"i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1777487513; cv=none;\n b=We4qi2emTz7/LhBEQKnoUkcCan+nKwT2sbkIK3RVP0Igt/2PWOWk7zSSkgpZbrHWX6fwpu4CeYdIBbmwczQK21VtYiMDnL6GPkYbP/wPfEz9vO1McHFjrW27Nkmr2/dAzp6i8nZ3MKeQGfxF8OiwRdOu4kDiY3W+vbAlUDkOb7E=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1777487513; c=relaxed/simple;\n bh=FFXcsNCV1WI2CtFsNVyKcZ9yV9D7A9XOo76YnLj17wc=;\n h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version;\n b=LLQmLV/H5yClZrFPy8hoxtTou0mLKJ6dwAj9hF6xbXAY9bIwOOvOrfNguFExruMt9CyTwy76xfg5C4sLPbcvhlAoYV64LoKd7vUfJ/sVwjMGrE9rNx5FJqkqPHpDfx09WH3q9kmlofH2iLfjqxnA4aieleWJ6HqLCmt6KgdZNCA=","ARC-Authentication-Results":"i=1; server2.sourceware.org","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc\n :content-transfer-encoding:content-type:date:from:message-id\n :mime-version:subject:to; s=pp1; bh=VmgH51DQcsE/qt128VxctumslZhY\n yb9HP1u1XQ5Dik8=; b=kLH4Gd2OQk8EzoP3UwmzosS1EDP7cgKbnIpjhal3X5E3\n H70JhRmcl3OHjLe9xlwc5NDKeblSW6QpCvLOX/Q/7CyVgtGC9f7wDToVV7wP76RV\n CdoMm5yuVqVPDa92Pp+J/G/iyL/CoEUk8UPBYo8mfZ6RqrxNq4m7Uhd3ohSVHdcr\n /dq+kycbXzs7fSafO+w5Hqb/UVoRq1AyWUqwz0GfcjuO0ju0NDPz2tvqixy1u+1f\n tBHh2h7BfundB6OeotPLFn2VQCcp/xJTFsMA1zaIrZ1xn6v2RDLKwEorrKc/1+V7\n yHQLtzwyEuQoSCPwVQq/ifQfWTFcOm4sv5BvQSDDHQ==","From":"Manjunath S Matti <mmatti@linux.ibm.com>","To":"gcc-patches@gcc.gnu.org, meissner@linux.ibm.com,\n segher@kernel.crashing.org, jskumari@linux.ibm.com","Cc":"Manjunath S Matti <mmatti@linux.ibm.com>","Subject":"[PATCH] rs6000: Builtins for ECC cryptography instructions [RFC02669]","Date":"Wed, 29 Apr 2026 13:31:43 -0500","Message-ID":"<20260429183143.4146806-1-mmatti@linux.ibm.com>","X-Mailer":"git-send-email 2.47.3","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","X-TM-AS-GCONF":"00","X-Proofpoint-ORIG-GUID":"MmkbpO3WU6NtV3VJYfZ7SiAO2eCvNsiB","X-Authority-Analysis":"v=2.4 cv=Ft81OWrq c=1 sm=1 tr=0 ts=69f24e98 cx=c_pps\n a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=RnoormkPH1_aCDwRdu11:22 a=iQ6ETzBq9ecOQQE5vZCe:22 a=VnNF1IyMAAAA:8\n a=pLs48D9BKjWelFrnwDAA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10","X-Proofpoint-GUID":"MmkbpO3WU6NtV3VJYfZ7SiAO2eCvNsiB","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDI5MDE4NCBTYWx0ZWRfX/AHKN9ax6wQ7\n 0Uap2eRUq1uluwCfrz+mm5CyRW00fGxzl8SvcKQ1SkoVtQYhexytl9X43t8CvrorVPIOuspzRJ4\n 0ADlT0/hE6FoC4Z5XMWRlmkXR/h2X94de6AtbkQmjWoammYkxsXMlsmttWJF1f961xatl4t7ycV\n ZI/pEck1/8EPbTc6j8tkgQ3+Zr62hnH42AAow5BlAqs2ipN9SQRS3sjainFuk08SSlMjhFZqX0/\n mW7noLKtkAXXXAVBH7OBPkouNvBtPDL0ROUSLaMQMP14DmOhQPRdLcmx6TtfArP+hXFa3pw4/QS\n wk4YleMQhj1PzGPdnZLUdGaGLrf38R+ICZQzpttv4NL/H9pVxndQl5f9b9VsSh6n3Ojo11aUwjt\n MsJ7uu3ERhTsnO/vsWvIXjFOI9jOx1VRRbri7cpwSmLzobsPhySTZW8Qo4ojW/fJVEYdQSaUIMn\n vdMONbcOA4DIh5r5z/Q==","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-29_01,2026-04-28_01,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n priorityscore=1501 lowpriorityscore=0 bulkscore=0 spamscore=0 impostorscore=0\n clxscore=1011 malwarescore=0 phishscore=0 suspectscore=0 adultscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604290184","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list <gcc-patches.gcc.gnu.org>","List-Unsubscribe":"<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>","List-Archive":"<https://gcc.gnu.org/pipermail/gcc-patches/>","List-Post":"<mailto:gcc-patches@gcc.gnu.org>","List-Help":"<mailto:gcc-patches-request@gcc.gnu.org?subject=help>","List-Subscribe":"<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"This patch depends on the -mcpu=future infrastructure.\nThe changes have been bootstrapped and regression tested\non powerpc64le-linux.\n\nThis patch implements builtin support for 21 new ECC (Elliptic\nCurve Cryptography) acceleration instructions defined in\nRFC02669 for Power ISA v3.2. These instructions are designed\nto accelerate P-256 and P-384 elliptic curve operations on\nPOWER future processors. These instructions may or may not\nbe supported in a future processor. Note, the names of the\nbuiltins may change in future.\n\nThe instructions are organized into five categories:\n\n1. Multiply-Multiply operations (3 instructions):\n   - xxmulmul: Multiply-multiply with scaling (scale values 0-6)\n   - xxmulmulhiadd: Multiply-multiply with high add and accumulator\n   - xxmulmulloadd: Multiply-multiply low add with accumulator\n\n2. Scaled Multiply-Sum operations (3 instructions):\n   - xxssumudm: Scaled sum unsigned doubleword modulo\n   - xxssumudmc: Scaled sum unsigned doubleword modulo carry\n   - xxssumudmcext: Extended version with separate accumulator\n     (prefixed)\n\n3. Quadword Add/Subtract operations (4 instructions):\n   - xsaddadduqm: Add add unsigned quadword modulo\n   - xsaddaddsuqm: Add add scaled unsigned quadword modulo\n   - xsaddsubuqm: Add subtract unsigned quadword modulo\n   - xsaddsubsuqm: Add subtract scaled unsigned quadword modulo\n\n4. Merge operations (4 instructions):\n   - xsmerge2t1uqm, xsmerge2t2uqm, xsmerge2t3uqm: 2-operand merge\n   - xsmerge3t1uqm: 3-operand merge with accumulator\n\n5. Rebase operations (7 instructions):\n   - xsrebase2t1uqm through xsrebase2t4uqm: 2-operand rebase\n   - xsrebase3t1uqm through xsrebase3t3uqm: 3-operand rebase with\n     accumulator\n\nAll instructions operate on 128-bit unsigned integers\n(vector unsigned __int128) and use VSX registers.\nThe xxssumudmcext instruction is a prefixed instruction (8 bytes),\nwhile all others use the standard XX3 form (4 bytes).\n\n2026-04-29 Manjunath Matti <mmatti@linux.ibm.com>\n\ngcc/ChangeLog:\n      * config/rs6000/predicates.md (const_0_to_6_operand): New\n\tpredicate for xxmulmul scale field validation.\n      * config/rs6000/rs6000-builtins.def: Add 21 ECC builtin\n\tdefinitions under [future] stanza.\n      * config/rs6000/vsx.md: Add UNSPEC constants for ECC instructions.\n\tAdd 21 instruction patterns with appropriate attributes.\n      * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions): Add\n\tdocumentation for ECC cryptography builtins available on\n\tISA 3.2.\n\ngcc/testsuite/ChangeLog:\n      * gcc.target/powerpc/ecc-builtin-1.c: New test for ECC builtins.","diff":"diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md\nindex 54dbc8bcc95..4162c22f8f6 100644\n--- a/gcc/config/rs6000/predicates.md\n+++ b/gcc/config/rs6000/predicates.md\n@@ -312,6 +312,11 @@\n   (and (match_code \"const_int\")\n        (match_test \"IN_RANGE (INTVAL (op), 2, 3)\")))\n \n+;; Match op = 0..6.\n+(define_predicate \"const_0_to_6_operand\"\n+  (and (match_code \"const_int\")\n+       (match_test \"IN_RANGE (INTVAL (op), 0, 6)\")))\n+\n ;; Match op = 0..7.\n (define_predicate \"const_0_to_7_operand\"\n   (and (match_code \"const_int\")\ndiff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def\nindex 7e5a4fb96e7..0c62872b62f 100644\n--- a/gcc/config/rs6000/rs6000-builtins.def\n+++ b/gcc/config/rs6000/rs6000-builtins.def\n@@ -3924,3 +3924,72 @@\n \n   void __builtin_vsx_stxvp (v256, unsigned long, const v256 *);\n     STXVP nothing {mma,pair}\n+\n+\n+; ECC (Elliptic Curve Cryptography) acceleration instructions for Power future.\n+; These instructions support P-256 and P-384 elliptic curve operations.\n+[future]\n+  const vuq __builtin_vsx_xxmulmul (vull, vull, const int<0,6>);\n+    XXMULMUL vsx_xxmulmul {}\n+\n+  const vuq __builtin_vsx_xxmulmulhiadd (vuq, vull, vull, const int<1>, \\\n+                                          const int<1>, const int<1>);\n+    XXMULMULHIADD vsx_xxmulmulhiadd {}\n+\n+  const vuq __builtin_vsx_xxmulmulloadd (vuq, vull, vull, const int<1>, \\\n+                                          const int<1>);\n+    XXMULMULLOADD vsx_xxmulmulloadd {}\n+\n+  const vuq __builtin_vsx_xxssumudm (vull, vull, const int<1>);\n+    XXSSUMUDM vsx_xxssumudm {}\n+\n+  const vuq __builtin_vsx_xxssumudmc (vull, vull, const int<1>);\n+    XXSSUMUDMC vsx_xxssumudmc {}\n+\n+  const vuq __builtin_vsx_xxssumudmcext (vull, vull, vuq, const int<1>);\n+    XXSSUMUDMCEXT vsx_xxssumudmcext {}\n+\n+  const vuq __builtin_vsx_xsaddadduqm (vuq, vuq, vuq);\n+    XSADDADDUQM vsx_xsaddadduqm {}\n+\n+  const vuq __builtin_vsx_xsaddaddsuqm (vuq, vuq, vuq);\n+    XSADDADDSUQM vsx_xsaddaddsuqm {}\n+\n+  const vuq __builtin_vsx_xsaddsubuqm (vuq, vuq, vuq);\n+    XSADDSUBUQM vsx_xsaddsubuqm {}\n+\n+  const vuq __builtin_vsx_xsaddsubsuqm (vuq, vuq, vuq);\n+    XSADDSUBSUQM vsx_xsaddsubsuqm {}\n+\n+  const vuq __builtin_vsx_xsmerge2t1uqm (vuq, vuq);\n+    XSMERGE2T1UQM vsx_xsmerge2t1uqm {}\n+\n+  const vuq __builtin_vsx_xsmerge2t2uqm (vuq, vuq);\n+    XSMERGE2T2UQM vsx_xsmerge2t2uqm {}\n+\n+  const vuq __builtin_vsx_xsmerge2t3uqm (vuq, vuq);\n+    XSMERGE2T3UQM vsx_xsmerge2t3uqm {}\n+\n+  const vuq __builtin_vsx_xsmerge3t1uqm (vuq, vuq, vuq);\n+    XSMERGE3T1UQM vsx_xsmerge3t1uqm {}\n+\n+  const vuq __builtin_vsx_xsrebase2t1uqm (vuq, vuq);\n+    XSREBASE2T1UQM vsx_xsrebase2t1uqm {}\n+\n+  const vuq __builtin_vsx_xsrebase2t2uqm (vuq, vuq);\n+    XSREBASE2T2UQM vsx_xsrebase2t2uqm {}\n+\n+  const vuq __builtin_vsx_xsrebase2t3uqm (vuq, vuq);\n+    XSREBASE2T3UQM vsx_xsrebase2t3uqm {}\n+\n+  const vuq __builtin_vsx_xsrebase2t4uqm (vuq, vuq);\n+    XSREBASE2T4UQM vsx_xsrebase2t4uqm {}\n+\n+  const vuq __builtin_vsx_xsrebase3t1uqm (vuq, vuq, vuq);\n+    XSREBASE3T1UQM vsx_xsrebase3t1uqm {}\n+\n+  const vuq __builtin_vsx_xsrebase3t2uqm (vuq, vuq, vuq);\n+    XSREBASE3T2UQM vsx_xsrebase3t2uqm {}\n+\n+  const vuq __builtin_vsx_xsrebase3t3uqm (vuq, vuq, vuq);\n+    XSREBASE3T3UQM vsx_xsrebase3t3uqm {}\ndiff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md\nindex cfad9b8c6d5..5351535f46a 100644\n--- a/gcc/config/rs6000/vsx.md\n+++ b/gcc/config/rs6000/vsx.md\n@@ -369,6 +369,27 @@\n    UNSPEC_XXSPLTI32DX\n    UNSPEC_XXBLEND\n    UNSPEC_XXPERMX\n+   UNSPEC_XXMULMUL\n+   UNSPEC_XXMULMULHIADD\n+   UNSPEC_XXMULMULLOADD\n+   UNSPEC_XXSSUMUDM\n+   UNSPEC_XXSSUMUDMC\n+   UNSPEC_XXSSUMUDMCEXT\n+   UNSPEC_XSADDADDUQM\n+   UNSPEC_XSADDADDSUQM\n+   UNSPEC_XSADDSUBUQM\n+   UNSPEC_XSADDSUBSUQM\n+   UNSPEC_XSMERGE2T1UQM\n+   UNSPEC_XSMERGE2T2UQM\n+   UNSPEC_XSMERGE2T3UQM\n+   UNSPEC_XSMERGE3T1UQM\n+   UNSPEC_XSREBASE2T1UQM\n+   UNSPEC_XSREBASE2T2UQM\n+   UNSPEC_XSREBASE2T3UQM\n+   UNSPEC_XSREBASE2T4UQM\n+   UNSPEC_XSREBASE3T1UQM\n+   UNSPEC_XSREBASE3T2UQM\n+   UNSPEC_XSREBASE3T3UQM\n   ])\n \n (define_int_iterator XVCVBF16\t[UNSPEC_VSX_XVCVSPBF16\n@@ -6807,3 +6828,259 @@\n   emit_insn (gen_vsx_extract_v2di (dest_op1, src_op, const1_rtx));\n   DONE;\n })\n+\n+\n+;; ECC (Elliptic Curve Cryptography) acceleration instructions for Power future\n+;; These instructions support P-256 and P-384 elliptic curve operations\n+\n+;; xxmulmul - Multiply-Multiply with scaling\n+(define_insn \"vsx_xxmulmul\"\n+  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n+\t(unspec:V1TI [(match_operand:V2DI 1 \"vsx_register_operand\" \"wa\")\n+\t\t      (match_operand:V2DI 2 \"vsx_register_operand\" \"wa\")\n+\t\t      (match_operand:SI 3 \"const_0_to_6_operand\" \"n\")]\n+\t\t     UNSPEC_XXMULMUL))]\n+  \"TARGET_FUTURE\"\n+  \"xxmulmul %x0,%x1,%x2,%3\"\n+  [(set_attr \"type\" \"veccomplex\")\n+   (set_attr \"size\" \"128\")])\n+\n+;; xxmulmulhiadd - Multiply-Multiply with high add and accumulator\n+(define_insn \"vsx_xxmulmulhiadd\"\n+  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n+\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"0\")\n+\t\t      (match_operand:V2DI 2 \"vsx_register_operand\" \"wa\")\n+\t\t      (match_operand:V2DI 3 \"vsx_register_operand\" \"wa\")\n+\t\t      (match_operand:SI 4 \"const_0_to_1_operand\" \"n\")\n+\t\t      (match_operand:SI 5 \"const_0_to_1_operand\" \"n\")\n+\t\t      (match_operand:SI 6 \"const_0_to_1_operand\" \"n\")]\n+\t\t     UNSPEC_XXMULMULHIADD))]\n+  \"TARGET_FUTURE\"\n+  \"xxmulmulhiadd %x0,%x2,%x3,%4,%5,%6\"\n+  [(set_attr \"type\" \"veccomplex\")\n+   (set_attr \"size\" \"128\")])\n+\n+;; xxmulmulloadd - Multiply-Multiply low add with accumulator\n+(define_insn \"vsx_xxmulmulloadd\"\n+  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n+\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"0\")\n+\t\t      (match_operand:V2DI 2 \"vsx_register_operand\" \"wa\")\n+\t\t      (match_operand:V2DI 3 \"vsx_register_operand\" \"wa\")\n+\t\t      (match_operand:SI 4 \"const_0_to_1_operand\" \"n\")\n+\t\t      (match_operand:SI 5 \"const_0_to_1_operand\" \"n\")]\n+\t\t     UNSPEC_XXMULMULLOADD))]\n+  \"TARGET_FUTURE\"\n+  \"xxmulmulloadd %x0,%x2,%x3,%4,%5\"\n+  [(set_attr \"type\" \"veccomplex\")\n+   (set_attr \"size\" \"128\")])\n+\n+;; xxssumudm - Scaled sum unsigned doubleword modulo\n+(define_insn \"vsx_xxssumudm\"\n+  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n+\t(unspec:V1TI [(match_operand:V2DI 1 \"vsx_register_operand\" \"wa\")\n+\t\t      (match_operand:V2DI 2 \"vsx_register_operand\" \"wa\")\n+\t\t      (match_operand:SI 3 \"const_0_to_1_operand\" \"n\")]\n+\t\t     UNSPEC_XXSSUMUDM))]\n+  \"TARGET_FUTURE\"\n+  \"xxssumudm %x0,%x1,%x2,%3\"\n+  [(set_attr \"type\" \"veccomplex\")\n+   (set_attr \"size\" \"128\")])\n+\n+;; xxssumudmc - Scaled sum unsigned doubleword modulo carry\n+(define_insn \"vsx_xxssumudmc\"\n+  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n+\t(unspec:V1TI [(match_operand:V2DI 1 \"vsx_register_operand\" \"wa\")\n+\t\t      (match_operand:V2DI 2 \"vsx_register_operand\" \"wa\")\n+\t\t      (match_operand:SI 3 \"const_0_to_1_operand\" \"n\")]\n+\t\t     UNSPEC_XXSSUMUDMC))]\n+  \"TARGET_FUTURE\"\n+  \"xxssumudmc %x0,%x1,%x2,%3\"\n+  [(set_attr \"type\" \"veccomplex\")\n+   (set_attr \"size\" \"128\")])\n+\n+;; xxssumudmcext - Scaled sum unsigned doubleword modulo carry extended (prefixed)\n+(define_insn \"vsx_xxssumudmcext\"\n+  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n+\t(unspec:V1TI [(match_operand:V2DI 1 \"vsx_register_operand\" \"wa\")\n+\t\t      (match_operand:V2DI 2 \"vsx_register_operand\" \"wa\")\n+\t\t      (match_operand:V1TI 3 \"vsx_register_operand\" \"wa\")\n+\t\t      (match_operand:SI 4 \"const_0_to_1_operand\" \"n\")]\n+\t\t     UNSPEC_XXSSUMUDMCEXT))]\n+  \"TARGET_FUTURE\"\n+  \"xxssumudmcext %x0,%x1,%x2,%x3,%4\"\n+  [(set_attr \"type\" \"veccomplex\")\n+   (set_attr \"size\" \"128\")\n+   (set_attr \"length\" \"8\")])\n+\n+;; xsaddadduqm - Add add unsigned quadword modulo\n+(define_insn \"vsx_xsaddadduqm\"\n+  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n+\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"0\")\n+\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")\n+\t\t      (match_operand:V1TI 3 \"vsx_register_operand\" \"wa\")]\n+\t\t     UNSPEC_XSADDADDUQM))]\n+  \"TARGET_FUTURE\"\n+  \"xsaddadduqm %x0,%x2,%x3\"\n+  [(set_attr \"type\" \"veccomplex\")\n+   (set_attr \"size\" \"128\")])\n+\n+;; xsaddaddsuqm - Add add scaled unsigned quadword modulo\n+(define_insn \"vsx_xsaddaddsuqm\"\n+  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n+\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"0\")\n+\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")\n+\t\t      (match_operand:V1TI 3 \"vsx_register_operand\" \"wa\")]\n+\t\t     UNSPEC_XSADDADDSUQM))]\n+  \"TARGET_FUTURE\"\n+  \"xsaddaddsuqm %x0,%x2,%x3\"\n+  [(set_attr \"type\" \"veccomplex\")\n+   (set_attr \"size\" \"128\")])\n+\n+;; xsaddsubuqm - Add subtract unsigned quadword modulo\n+(define_insn \"vsx_xsaddsubuqm\"\n+  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n+\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"0\")\n+\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")\n+\t\t      (match_operand:V1TI 3 \"vsx_register_operand\" \"wa\")]\n+\t\t     UNSPEC_XSADDSUBUQM))]\n+  \"TARGET_FUTURE\"\n+  \"xsaddsubuqm %x0,%x2,%x3\"\n+  [(set_attr \"type\" \"veccomplex\")\n+   (set_attr \"size\" \"128\")])\n+\n+;; xsaddsubsuqm - Add subtract scaled unsigned quadword modulo\n+(define_insn \"vsx_xsaddsubsuqm\"\n+  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n+\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"0\")\n+\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")\n+\t\t      (match_operand:V1TI 3 \"vsx_register_operand\" \"wa\")]\n+\t\t     UNSPEC_XSADDSUBSUQM))]\n+  \"TARGET_FUTURE\"\n+  \"xsaddsubsuqm %x0,%x2,%x3\"\n+  [(set_attr \"type\" \"veccomplex\")\n+   (set_attr \"size\" \"128\")])\n+\n+;; xsmerge2t1uqm - Merge type 1 (2-operand)\n+(define_insn \"vsx_xsmerge2t1uqm\"\n+  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n+\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"wa\")\n+\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")]\n+\t\t     UNSPEC_XSMERGE2T1UQM))]\n+  \"TARGET_FUTURE\"\n+  \"xsmerge2t1uqm %x0,%x1,%x2\"\n+  [(set_attr \"type\" \"vecperm\")\n+   (set_attr \"size\" \"128\")])\n+\n+;; xsmerge2t2uqm - Merge type 2 (2-operand)\n+(define_insn \"vsx_xsmerge2t2uqm\"\n+  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n+\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"wa\")\n+\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")]\n+\t\t     UNSPEC_XSMERGE2T2UQM))]\n+  \"TARGET_FUTURE\"\n+  \"xsmerge2t2uqm %x0,%x1,%x2\"\n+  [(set_attr \"type\" \"vecperm\")\n+   (set_attr \"size\" \"128\")])\n+\n+;; xsmerge2t3uqm - Merge type 3 (2-operand)\n+(define_insn \"vsx_xsmerge2t3uqm\"\n+  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n+\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"wa\")\n+\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")]\n+\t\t     UNSPEC_XSMERGE2T3UQM))]\n+  \"TARGET_FUTURE\"\n+  \"xsmerge2t3uqm %x0,%x1,%x2\"\n+  [(set_attr \"type\" \"vecperm\")\n+   (set_attr \"size\" \"128\")])\n+\n+;; xsmerge3t1uqm - Merge type 1 (3-operand with accumulator)\n+(define_insn \"vsx_xsmerge3t1uqm\"\n+  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n+\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"0\")\n+\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")\n+\t\t      (match_operand:V1TI 3 \"vsx_register_operand\" \"wa\")]\n+\t\t     UNSPEC_XSMERGE3T1UQM))]\n+  \"TARGET_FUTURE\"\n+  \"xsmerge3t1uqm %x0,%x2,%x3\"\n+  [(set_attr \"type\" \"vecperm\")\n+   (set_attr \"size\" \"128\")])\n+\n+;; xsrebase2t1uqm - Rebase type 1 (2-operand)\n+(define_insn \"vsx_xsrebase2t1uqm\"\n+  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n+\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"wa\")\n+\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")]\n+\t\t     UNSPEC_XSREBASE2T1UQM))]\n+  \"TARGET_FUTURE\"\n+  \"xsrebase2t1uqm %x0,%x1,%x2\"\n+  [(set_attr \"type\" \"vecperm\")\n+   (set_attr \"size\" \"128\")])\n+\n+;; xsrebase2t2uqm - Rebase type 2 (2-operand)\n+(define_insn \"vsx_xsrebase2t2uqm\"\n+  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n+\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"wa\")\n+\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")]\n+\t\t     UNSPEC_XSREBASE2T2UQM))]\n+  \"TARGET_FUTURE\"\n+  \"xsrebase2t2uqm %x0,%x1,%x2\"\n+  [(set_attr \"type\" \"vecperm\")\n+   (set_attr \"size\" \"128\")])\n+\n+;; xsrebase2t3uqm - Rebase type 3 (2-operand)\n+(define_insn \"vsx_xsrebase2t3uqm\"\n+  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n+\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"wa\")\n+\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")]\n+\t\t     UNSPEC_XSREBASE2T3UQM))]\n+  \"TARGET_FUTURE\"\n+  \"xsrebase2t3uqm %x0,%x1,%x2\"\n+  [(set_attr \"type\" \"vecperm\")\n+   (set_attr \"size\" \"128\")])\n+\n+;; xsrebase2t4uqm - Rebase type 4 (2-operand)\n+(define_insn \"vsx_xsrebase2t4uqm\"\n+  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n+\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"wa\")\n+\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")]\n+\t\t     UNSPEC_XSREBASE2T4UQM))]\n+  \"TARGET_FUTURE\"\n+  \"xsrebase2t4uqm %x0,%x1,%x2\"\n+  [(set_attr \"type\" \"vecperm\")\n+   (set_attr \"size\" \"128\")])\n+\n+;; xsrebase3t1uqm - Rebase type 1 (3-operand with accumulator)\n+(define_insn \"vsx_xsrebase3t1uqm\"\n+  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n+\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"0\")\n+\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")\n+\t\t      (match_operand:V1TI 3 \"vsx_register_operand\" \"wa\")]\n+\t\t     UNSPEC_XSREBASE3T1UQM))]\n+  \"TARGET_FUTURE\"\n+  \"xsrebase3t1uqm %x0,%x2,%x3\"\n+  [(set_attr \"type\" \"vecperm\")\n+   (set_attr \"size\" \"128\")])\n+\n+;; xsrebase3t2uqm - Rebase type 2 (3-operand with accumulator)\n+(define_insn \"vsx_xsrebase3t2uqm\"\n+  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n+\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"0\")\n+\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")\n+\t\t      (match_operand:V1TI 3 \"vsx_register_operand\" \"wa\")]\n+\t\t     UNSPEC_XSREBASE3T2UQM))]\n+  \"TARGET_FUTURE\"\n+  \"xsrebase3t2uqm %x0,%x2,%x3\"\n+  [(set_attr \"type\" \"vecperm\")\n+   (set_attr \"size\" \"128\")])\n+\n+;; xsrebase3t3uqm - Rebase type 3 (3-operand with accumulator)\n+(define_insn \"vsx_xsrebase3t3uqm\"\n+  [(set (match_operand:V1TI 0 \"vsx_register_operand\" \"=wa\")\n+\t(unspec:V1TI [(match_operand:V1TI 1 \"vsx_register_operand\" \"0\")\n+\t\t      (match_operand:V1TI 2 \"vsx_register_operand\" \"wa\")\n+\t\t      (match_operand:V1TI 3 \"vsx_register_operand\" \"wa\")]\n+\t\t     UNSPEC_XSREBASE3T3UQM))]\n+  \"TARGET_FUTURE\"\n+  \"xsrebase3t3uqm %x0,%x2,%x3\"\n+  [(set_attr \"type\" \"vecperm\")\n+   (set_attr \"size\" \"128\")])\ndiff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi\nindex 0faa5323ce1..4615fa74fae 100644\n--- a/gcc/doc/extend.texi\n+++ b/gcc/doc/extend.texi\n@@ -24696,6 +24696,7 @@ The PVIPR documents the following overloaded functions:\n * PowerPC AltiVec Built-in Functions Available on ISA 2.07::\n * PowerPC AltiVec Built-in Functions Available on ISA 3.0::\n * PowerPC AltiVec Built-in Functions Available on ISA 3.1::\n+* PowerPC AltiVec Built-in Functions Available on ISA 3.2 (Future)::\n @end menu\n \n @node PowerPC AltiVec Built-in Functions on ISA 2.05\n@@ -26729,6 +26730,268 @@ vector unsigned char);\n vector unsigned char);\n @end smallexample\n \n+@node PowerPC AltiVec Built-in Functions Available on ISA 3.2 (Future)\n+@subsubsection PowerPC AltiVec Built-in Functions Available on ISA 3.2 (Future)\n+\n+The following additional built-in functions are available for the\n+PowerPC family of processors, starting with ISA 3.2 (@option{-mcpu=future}).\n+These instructions provide hardware acceleration for Elliptic Curve\n+Cryptography (ECC) operations, specifically optimized for P-256 and P-384\n+elliptic curves.\n+\n+All ECC built-in functions operate on 128-bit unsigned integers\n+(@code{vector unsigned __int128}) and use VSX registers. The functions\n+are organized into five categories: multiply-multiply operations, scaled\n+multiply-sum operations, quadword add/subtract operations, merge operations,\n+and rebase operations.\n+\n+@subsubheading Multiply-Multiply Operations\n+\n+@smallexample\n+vector unsigned __int128\n+__builtin_vsx_xxmulmul (vector unsigned long long @var{a},\n+                        vector unsigned long long @var{b},\n+                        const int @var{scale});\n+@end smallexample\n+@findex __builtin_vsx_xxmulmul\n+\n+Perform a multiply-multiply operation with scaling. The @var{scale} parameter\n+must be a literal integer value between 0 and 6 inclusive. This instruction\n+multiplies elements from vectors @var{a} and @var{b} and applies the specified\n+scaling factor, producing a 128-bit result.\n+\n+@smallexample\n+vector unsigned __int128\n+__builtin_vsx_xxmulmulhiadd (vector unsigned __int128 @var{acc},\n+                             vector unsigned long long @var{a},\n+                             vector unsigned long long @var{b},\n+                             const int @var{m1},\n+                             const int @var{m2},\n+                             const int @var{m3});\n+@end smallexample\n+@findex __builtin_vsx_xxmulmulhiadd\n+\n+Perform a multiply-multiply operation with high add and accumulator. The\n+accumulator @var{acc} is updated with the result. The @var{m1}, @var{m2},\n+and @var{m3} parameters must be literal integer values of 0 or 1, controlling\n+the operation mode.\n+\n+@smallexample\n+vector unsigned __int128\n+__builtin_vsx_xxmulmulloadd (vector unsigned __int128 @var{acc},\n+                             vector unsigned long long @var{a},\n+                             vector unsigned long long @var{b},\n+                             const int @var{m1},\n+                             const int @var{m2});\n+@end smallexample\n+@findex __builtin_vsx_xxmulmulloadd\n+\n+Perform a multiply-multiply low add operation with accumulator. The\n+accumulator @var{acc} is updated with the result. The @var{m1} and @var{m2}\n+parameters must be literal integer values of 0 or 1, controlling the\n+operation mode.\n+\n+@subsubheading Scaled Multiply-Sum Operations\n+\n+@smallexample\n+vector unsigned __int128\n+__builtin_vsx_xxssumudm (vector unsigned long long @var{a},\n+                         vector unsigned long long @var{b},\n+                         const int @var{scale});\n+@end smallexample\n+@findex __builtin_vsx_xxssumudm\n+\n+Perform a scaled sum of unsigned doubleword elements modulo 2^128. The\n+@var{scale} parameter must be a literal integer value of 0 or 1.\n+\n+@smallexample\n+vector unsigned __int128\n+__builtin_vsx_xxssumudmc (vector unsigned long long @var{a},\n+                          vector unsigned long long @var{b},\n+                          const int @var{scale});\n+@end smallexample\n+@findex __builtin_vsx_xxssumudmc\n+\n+Perform a scaled sum of unsigned doubleword elements modulo 2^128 with carry\n+output. The @var{scale} parameter must be a literal integer value of 0 or 1.\n+\n+@smallexample\n+vector unsigned __int128\n+__builtin_vsx_xxssumudmcext (vector unsigned long long @var{a},\n+                             vector unsigned long long @var{b},\n+                             vector unsigned __int128 @var{c},\n+                             const int @var{scale});\n+@end smallexample\n+@findex __builtin_vsx_xxssumudmcext\n+\n+Perform an extended scaled sum of unsigned doubleword elements with a separate\n+accumulator @var{c}. The @var{scale} parameter must be a literal integer value\n+of 0 or 1. This is a prefixed instruction (8 bytes).\n+\n+@subsubheading Quadword Add/Subtract Operations\n+\n+@smallexample\n+vector unsigned __int128\n+__builtin_vsx_xsaddadduqm (vector unsigned __int128 @var{acc},\n+                           vector unsigned __int128 @var{a},\n+                           vector unsigned __int128 @var{b});\n+@end smallexample\n+@findex __builtin_vsx_xsaddadduqm\n+\n+Add two unsigned quadword values @var{a} and @var{b}, then add the result\n+to the accumulator @var{acc}, performing all operations modulo 2^128.\n+\n+@smallexample\n+vector unsigned __int128\n+__builtin_vsx_xsaddaddsuqm (vector unsigned __int128 @var{acc},\n+                            vector unsigned __int128 @var{a},\n+                            vector unsigned __int128 @var{b});\n+@end smallexample\n+@findex __builtin_vsx_xsaddaddsuqm\n+\n+Add two unsigned quadword values @var{a} and @var{b} with scaling, then add\n+the result to the accumulator @var{acc}, performing all operations modulo 2^128.\n+\n+@smallexample\n+vector unsigned __int128\n+__builtin_vsx_xsaddsubuqm (vector unsigned __int128 @var{acc},\n+                           vector unsigned __int128 @var{a},\n+                           vector unsigned __int128 @var{b});\n+@end smallexample\n+@findex __builtin_vsx_xsaddsubuqm\n+\n+Subtract unsigned quadword @var{b} from @var{a}, then add the result to the\n+accumulator @var{acc}, performing all operations modulo 2^128.\n+\n+@smallexample\n+vector unsigned __int128\n+__builtin_vsx_xsaddsubsuqm (vector unsigned __int128 @var{acc},\n+                            vector unsigned __int128 @var{a},\n+                            vector unsigned __int128 @var{b});\n+@end smallexample\n+@findex __builtin_vsx_xsaddsubsuqm\n+\n+Subtract unsigned quadword @var{b} from @var{a} with scaling, then add the\n+result to the accumulator @var{acc}, performing all operations modulo 2^128.\n+\n+@subsubheading Merge Operations\n+\n+@smallexample\n+vector unsigned __int128\n+__builtin_vsx_xsmerge2t1uqm (vector unsigned __int128 @var{a},\n+                             vector unsigned __int128 @var{b});\n+@end smallexample\n+@findex __builtin_vsx_xsmerge2t1uqm\n+\n+Perform a type 1 merge operation on two unsigned quadword values @var{a}\n+and @var{b}.\n+\n+@smallexample\n+vector unsigned __int128\n+__builtin_vsx_xsmerge2t2uqm (vector unsigned __int128 @var{a},\n+                             vector unsigned __int128 @var{b});\n+@end smallexample\n+@findex __builtin_vsx_xsmerge2t2uqm\n+\n+Perform a type 2 merge operation on two unsigned quadword values @var{a}\n+and @var{b}.\n+\n+@smallexample\n+vector unsigned __int128\n+__builtin_vsx_xsmerge2t3uqm (vector unsigned __int128 @var{a},\n+                             vector unsigned __int128 @var{b});\n+@end smallexample\n+@findex __builtin_vsx_xsmerge2t3uqm\n+\n+Perform a type 3 merge operation on two unsigned quadword values @var{a}\n+and @var{b}.\n+\n+@smallexample\n+vector unsigned __int128\n+__builtin_vsx_xsmerge3t1uqm (vector unsigned __int128 @var{acc},\n+                             vector unsigned __int128 @var{a},\n+                             vector unsigned __int128 @var{b});\n+@end smallexample\n+@findex __builtin_vsx_xsmerge3t1uqm\n+\n+Perform a type 1 merge operation on two unsigned quadword values @var{a}\n+and @var{b} with accumulator @var{acc}.\n+\n+@subsubheading Rebase Operations\n+\n+@smallexample\n+vector unsigned __int128\n+__builtin_vsx_xsrebase2t1uqm (vector unsigned __int128 @var{a},\n+                              vector unsigned __int128 @var{b});\n+@end smallexample\n+@findex __builtin_vsx_xsrebase2t1uqm\n+\n+Perform a type 1 rebase operation on two unsigned quadword values @var{a}\n+and @var{b}.\n+\n+@smallexample\n+vector unsigned __int128\n+__builtin_vsx_xsrebase2t2uqm (vector unsigned __int128 @var{a},\n+                              vector unsigned __int128 @var{b});\n+@end smallexample\n+@findex __builtin_vsx_xsrebase2t2uqm\n+\n+Perform a type 2 rebase operation on two unsigned quadword values @var{a}\n+and @var{b}.\n+\n+@smallexample\n+vector unsigned __int128\n+__builtin_vsx_xsrebase2t3uqm (vector unsigned __int128 @var{a},\n+                              vector unsigned __int128 @var{b});\n+@end smallexample\n+@findex __builtin_vsx_xsrebase2t3uqm\n+\n+Perform a type 3 rebase operation on two unsigned quadword values @var{a}\n+and @var{b}.\n+\n+@smallexample\n+vector unsigned __int128\n+__builtin_vsx_xsrebase2t4uqm (vector unsigned __int128 @var{a},\n+                              vector unsigned __int128 @var{b});\n+@end smallexample\n+@findex __builtin_vsx_xsrebase2t4uqm\n+\n+Perform a type 4 rebase operation on two unsigned quadword values @var{a}\n+and @var{b}.\n+\n+@smallexample\n+vector unsigned __int128\n+__builtin_vsx_xsrebase3t1uqm (vector unsigned __int128 @var{acc},\n+                              vector unsigned __int128 @var{a},\n+                              vector unsigned __int128 @var{b});\n+@end smallexample\n+@findex __builtin_vsx_xsrebase3t1uqm\n+\n+Perform a type 1 rebase operation on two unsigned quadword values @var{a}\n+and @var{b} with accumulator @var{acc}.\n+\n+@smallexample\n+vector unsigned __int128\n+__builtin_vsx_xsrebase3t2uqm (vector unsigned __int128 @var{acc},\n+                              vector unsigned __int128 @var{a},\n+                              vector unsigned __int128 @var{b});\n+@end smallexample\n+@findex __builtin_vsx_xsrebase3t2uqm\n+\n+Perform a type 2 rebase operation on two unsigned quadword values @var{a}\n+and @var{b} with accumulator @var{acc}.\n+\n+@smallexample\n+vector unsigned __int128\n+__builtin_vsx_xsrebase3t3uqm (vector unsigned __int128 @var{acc},\n+                              vector unsigned __int128 @var{a},\n+                              vector unsigned __int128 @var{b});\n+@end smallexample\n+@findex __builtin_vsx_xsrebase3t3uqm\n+\n+Perform a type 3 rebase operation on two unsigned quadword values @var{a}\n+and @var{b} with accumulator @var{acc}.\n+\n @node PowerPC Hardware Transactional Memory Built-in Functions\n @subsection PowerPC Hardware Transactional Memory Built-in Functions\n GCC provides two interfaces for accessing the Hardware Transactional\ndiff --git a/gcc/testsuite/gcc.target/powerpc/ecc-builtin-1.c b/gcc/testsuite/gcc.target/powerpc/ecc-builtin-1.c\nnew file mode 100644\nindex 00000000000..2275d50ffdf\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/powerpc/ecc-builtin-1.c\n@@ -0,0 +1,198 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-mdejagnu-cpu=future -O2\" } */\n+\n+/* Test the ECC (Elliptic Curve Cryptography) acceleration builtins for Power future.\n+   These instructions support P-256 and P-384 elliptic curve operations. */\n+\n+#include <altivec.h>\n+\n+/* Test xxmulmul - Multiply-Multiply with scaling */\n+vector unsigned __int128\n+test_xxmulmul (vector unsigned long long a, vector unsigned long long b)\n+{\n+  return __builtin_vsx_xxmulmul (a, b, 3);\n+}\n+\n+/* Test xxmulmulhiadd - Multiply-Multiply with high add and accumulator */\n+vector unsigned __int128\n+test_xxmulmulhiadd (vector unsigned __int128 acc,\n+                    vector unsigned long long a,\n+                    vector unsigned long long b)\n+{\n+  return __builtin_vsx_xxmulmulhiadd (acc, a, b, 1, 0, 1);\n+}\n+\n+/* Test xxmulmulloadd - Multiply-Multiply low add with accumulator */\n+vector unsigned __int128\n+test_xxmulmulloadd (vector unsigned __int128 acc,\n+                    vector unsigned long long a,\n+                    vector unsigned long long b)\n+{\n+  return __builtin_vsx_xxmulmulloadd (acc, a, b, 1, 0);\n+}\n+\n+/* Test xxssumudm - Scaled sum unsigned doubleword modulo */\n+vector unsigned __int128\n+test_xxssumudm (vector unsigned long long a, vector unsigned long long b)\n+{\n+  return __builtin_vsx_xxssumudm (a, b, 1);\n+}\n+\n+/* Test xxssumudmc - Scaled sum unsigned doubleword modulo carry */\n+vector unsigned __int128\n+test_xxssumudmc (vector unsigned long long a, vector unsigned long long b)\n+{\n+  return __builtin_vsx_xxssumudmc (a, b, 0);\n+}\n+\n+/* Test xxssumudmcext - Scaled sum unsigned doubleword modulo carry extended */\n+vector unsigned __int128\n+test_xxssumudmcext (vector unsigned long long a,\n+                    vector unsigned long long b,\n+                    vector unsigned __int128 c)\n+{\n+  return __builtin_vsx_xxssumudmcext (a, b, c, 1);\n+}\n+\n+/* Test xsaddadduqm - Add add unsigned quadword modulo */\n+vector unsigned __int128\n+test_xsaddadduqm (vector unsigned __int128 acc,\n+                  vector unsigned __int128 a,\n+                  vector unsigned __int128 b)\n+{\n+  return __builtin_vsx_xsaddadduqm (acc, a, b);\n+}\n+\n+/* Test xsaddaddsuqm - Add add scaled unsigned quadword modulo */\n+vector unsigned __int128\n+test_xsaddaddsuqm (vector unsigned __int128 acc,\n+                   vector unsigned __int128 a,\n+                   vector unsigned __int128 b)\n+{\n+  return __builtin_vsx_xsaddaddsuqm (acc, a, b);\n+}\n+\n+/* Test xsaddsubuqm - Add subtract unsigned quadword modulo */\n+vector unsigned __int128\n+test_xsaddsubuqm (vector unsigned __int128 acc,\n+                  vector unsigned __int128 a,\n+                  vector unsigned __int128 b)\n+{\n+  return __builtin_vsx_xsaddsubuqm (acc, a, b);\n+}\n+\n+/* Test xsaddsubsuqm - Add subtract scaled unsigned quadword modulo */\n+vector unsigned __int128\n+test_xsaddsubsuqm (vector unsigned __int128 acc,\n+                   vector unsigned __int128 a,\n+                   vector unsigned __int128 b)\n+{\n+  return __builtin_vsx_xsaddsubsuqm (acc, a, b);\n+}\n+\n+/* Test xsmerge2t1uqm - Merge type 1 (2-operand) */\n+vector unsigned __int128\n+test_xsmerge2t1uqm (vector unsigned __int128 a, vector unsigned __int128 b)\n+{\n+  return __builtin_vsx_xsmerge2t1uqm (a, b);\n+}\n+\n+/* Test xsmerge2t2uqm - Merge type 2 (2-operand) */\n+vector unsigned __int128\n+test_xsmerge2t2uqm (vector unsigned __int128 a, vector unsigned __int128 b)\n+{\n+  return __builtin_vsx_xsmerge2t2uqm (a, b);\n+}\n+\n+/* Test xsmerge2t3uqm - Merge type 3 (2-operand) */\n+vector unsigned __int128\n+test_xsmerge2t3uqm (vector unsigned __int128 a, vector unsigned __int128 b)\n+{\n+  return __builtin_vsx_xsmerge2t3uqm (a, b);\n+}\n+\n+/* Test xsmerge3t1uqm - Merge type 1 (3-operand with accumulator) */\n+vector unsigned __int128\n+test_xsmerge3t1uqm (vector unsigned __int128 acc,\n+                    vector unsigned __int128 a,\n+                    vector unsigned __int128 b)\n+{\n+  return __builtin_vsx_xsmerge3t1uqm (acc, a, b);\n+}\n+\n+/* Test xsrebase2t1uqm - Rebase type 1 (2-operand) */\n+vector unsigned __int128\n+test_xsrebase2t1uqm (vector unsigned __int128 a, vector unsigned __int128 b)\n+{\n+  return __builtin_vsx_xsrebase2t1uqm (a, b);\n+}\n+\n+/* Test xsrebase2t2uqm - Rebase type 2 (2-operand) */\n+vector unsigned __int128\n+test_xsrebase2t2uqm (vector unsigned __int128 a, vector unsigned __int128 b)\n+{\n+  return __builtin_vsx_xsrebase2t2uqm (a, b);\n+}\n+\n+/* Test xsrebase2t3uqm - Rebase type 3 (2-operand) */\n+vector unsigned __int128\n+test_xsrebase2t3uqm (vector unsigned __int128 a, vector unsigned __int128 b)\n+{\n+  return __builtin_vsx_xsrebase2t3uqm (a, b);\n+}\n+\n+/* Test xsrebase2t4uqm - Rebase type 4 (2-operand) */\n+vector unsigned __int128\n+test_xsrebase2t4uqm (vector unsigned __int128 a, vector unsigned __int128 b)\n+{\n+  return __builtin_vsx_xsrebase2t4uqm (a, b);\n+}\n+\n+/* Test xsrebase3t1uqm - Rebase type 1 (3-operand with accumulator) */\n+vector unsigned __int128\n+test_xsrebase3t1uqm (vector unsigned __int128 acc,\n+                     vector unsigned __int128 a,\n+                     vector unsigned __int128 b)\n+{\n+  return __builtin_vsx_xsrebase3t1uqm (acc, a, b);\n+}\n+\n+/* Test xsrebase3t2uqm - Rebase type 2 (3-operand with accumulator) */\n+vector unsigned __int128\n+test_xsrebase3t2uqm (vector unsigned __int128 acc,\n+                     vector unsigned __int128 a,\n+                     vector unsigned __int128 b)\n+{\n+  return __builtin_vsx_xsrebase3t2uqm (acc, a, b);\n+}\n+\n+/* Test xsrebase3t3uqm - Rebase type 3 (3-operand with accumulator) */\n+vector unsigned __int128\n+test_xsrebase3t3uqm (vector unsigned __int128 acc,\n+                     vector unsigned __int128 a,\n+                     vector unsigned __int128 b)\n+{\n+  return __builtin_vsx_xsrebase3t3uqm (acc, a, b);\n+}\n+\n+/* { dg-final { scan-assembler-times {\\mxxmulmul\\M} 1 } } */\n+/* { dg-final { scan-assembler-times {\\mxxmulmulhiadd\\M} 1 } } */\n+/* { dg-final { scan-assembler-times {\\mxxmulmulloadd\\M} 1 } } */\n+/* { dg-final { scan-assembler-times {\\mxxssumudm\\M} 1 } } */\n+/* { dg-final { scan-assembler-times {\\mxxssumudmc\\M} 1 } } */\n+/* { dg-final { scan-assembler-times {\\mxxssumudmcext\\M} 1 } } */\n+/* { dg-final { scan-assembler-times {\\mxsaddadduqm\\M} 1 } } */\n+/* { dg-final { scan-assembler-times {\\mxsaddaddsuqm\\M} 1 } } */\n+/* { dg-final { scan-assembler-times {\\mxsaddsubuqm\\M} 1 } } */\n+/* { dg-final { scan-assembler-times {\\mxsaddsubsuqm\\M} 1 } } */\n+/* { dg-final { scan-assembler-times {\\mxsmerge2t1uqm\\M} 1 } } */\n+/* { dg-final { scan-assembler-times {\\mxsmerge2t2uqm\\M} 1 } } */\n+/* { dg-final { scan-assembler-times {\\mxsmerge2t3uqm\\M} 1 } } */\n+/* { dg-final { scan-assembler-times {\\mxsmerge3t1uqm\\M} 1 } } */\n+/* { dg-final { scan-assembler-times {\\mxsrebase2t1uqm\\M} 1 } } */\n+/* { dg-final { scan-assembler-times {\\mxsrebase2t2uqm\\M} 1 } } */\n+/* { dg-final { scan-assembler-times {\\mxsrebase2t3uqm\\M} 1 } } */\n+/* { dg-final { scan-assembler-times {\\mxsrebase2t4uqm\\M} 1 } } */\n+/* { dg-final { scan-assembler-times {\\mxsrebase3t1uqm\\M} 1 } } */\n+/* { dg-final { scan-assembler-times {\\mxsrebase3t2uqm\\M} 1 } } */\n+/* { dg-final { scan-assembler-times {\\mxsrebase3t3uqm\\M} 1 } } */\n","prefixes":[]}