{"id":2230116,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230116/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/20260429093257.62004-1-jinma@linux.alibaba.com/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/1.1/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260429093257.62004-1-jinma@linux.alibaba.com>","date":"2026-04-29T09:32:57","name":"RISC-V: Fix missing braces in riscv_rtx_costs for slli.uw pattern [PR???]","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"5d7af6b23c83438538ca95a797891a9f471d458e","submitter":{"id":85474,"url":"http://patchwork.ozlabs.org/api/1.1/people/85474/?format=json","name":"Jin Ma","email":"jinma@linux.alibaba.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/20260429093257.62004-1-jinma@linux.alibaba.com/mbox/","series":[{"id":502024,"url":"http://patchwork.ozlabs.org/api/1.1/series/502024/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=502024","date":"2026-04-29T09:32:57","name":"RISC-V: Fix missing braces in riscv_rtx_costs for slli.uw pattern [PR???]","version":1,"mbox":"http://patchwork.ozlabs.org/series/502024/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230116/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230116/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.alibaba.com header.i=@linux.alibaba.com\n header.a=rsa-sha256 header.s=default header.b=fhFT7Lhp;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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c=relaxed/simple;\n bh=TuSTJ2/atu9Ws38FHvgJT4iJc+coD9A88pABEwHmO3M=;\n h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version;\n b=PprlDyngIosvymHZBNR9ODHThN0L3ddVJUvMUPXLLMYeBHtRuXSmYCczuiLVCpIPW1pHn2jL7v+ONilfDEk8yM+WTFEblYm55hYfL36iLjpLRvzKee+WXTomwaiG67n2JcL98ImIFVqQ9KdTP+K01RdjL5RAhXdUZkEjWmRVQAI=","ARC-Authentication-Results":"i=1; server2.sourceware.org","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linux.alibaba.com; s=default;\n t=1777455186; h=From:To:Subject:Date:Message-ID:MIME-Version;\n bh=nXK/pgcjCPjhn3n95QkehBxjvS+1EJCc+iHJabIZ+Sw=;\n b=fhFT7LhpyfzCyjzR+VKgy2AQuxfhv5DQHSLv5a30zu9LkeuTTUi5UmkW1t2Qye/j9YNijSKJ1XEUb4Egru3rX+qiKo9g2eL5xw3767tXZVtf0eh3Z0RvS82TybbBRuKI5sDboo7Y1OAZlS1KbmNBeY4LSBHvA7gVL4SDBxRvIes=","X-Alimail-AntiSpam":"AC=PASS; BC=-1|-1; BR=01201311R451e4; CH=green;\n DM=||false|;\n DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033037009110;\n MF=jinma@linux.alibaba.com; NM=1; PH=DS; RN=5; SR=0;\n TI=SMTPD_---0X1xCDFT_1777455180;","From":"Jin Ma ","To":"gcc-patches@gcc.gnu.org","Cc":"jeffreyalaw@gmail.com, palmer@dabbelt.com, richard.sandiford@arm.com,\n Jin Ma ","Subject":"[PATCH] RISC-V: Fix missing braces in riscv_rtx_costs for slli.uw\n pattern [PR???]","Date":"Wed, 29 Apr 2026 17:32:57 +0800","Message-ID":"<20260429093257.62004-1-jinma@linux.alibaba.com>","X-Mailer":"git-send-email 2.50.1","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"The AND case in riscv_rtx_costs for the slli.uw pattern (zba extension)\nhas a multi-statement if body without braces. This causes the\n'return true' to execute unconditionally whenever the left operand of\nAND is an ASHIFT, regardless of whether the inner condition (checking\nregister_operand, CONST_INT_P, and the 0xffffffff mask) is satisfied.\n\nThis effectively short-circuits the entire AND cost calculation for any\nAND+ASHIFT combination when TARGET_ZBA && TARGET_64BIT && DImode,\nskipping subsequent pattern checks (bclri, bclr, etc.) and the\nfallthrough to PLUS/MINUS.\n\ngcc/ChangeLog:\n\n\t* config/riscv/riscv.cc (riscv_rtx_costs): Add missing braces\n\taround the if body for the slli.uw pattern in the AND case.\n---\n gcc/config/riscv/riscv.cc | 6 ++++--\n 1 file changed, 4 insertions(+), 2 deletions(-)","diff":"diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc\nindex 97272b4349a..39da4410cd8 100644\n--- a/gcc/config/riscv/riscv.cc\n+++ b/gcc/config/riscv/riscv.cc\n@@ -4377,8 +4377,10 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN\n \t && CONST_INT_P (ashift_rhs)\n \t && CONST_INT_P (and_rhs)\n \t && ((INTVAL (and_rhs) >> INTVAL (ashift_rhs)) == 0xffffffff))\n-\t *total = COSTS_N_INSNS (1);\n-\t return true;\n+\t {\n+\t *total = COSTS_N_INSNS (1);\n+\t return true;\n+\t }\n \t}\n /* bclri pattern for zbs. */\n if (TARGET_ZBS\n","prefixes":[]}