{"id":2230101,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230101/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260429081313.151656-1-weijie.gao@mediatek.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.1/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260429081313.151656-1-weijie.gao@mediatek.com>","date":"2026-04-29T08:13:13","name":"mtd: spinand: add support for Etron SPI-NAND flashes","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"379d4894560af11c8d5ed158cbca43cd825b119f","submitter":{"id":75269,"url":"http://patchwork.ozlabs.org/api/1.1/people/75269/?format=json","name":"Weijie Gao","email":"weijie.gao@mediatek.com"},"delegate":{"id":17739,"url":"http://patchwork.ozlabs.org/api/1.1/users/17739/?format=json","username":"jagan","first_name":"Jagannadha Sutradharudu","last_name":"Teki","email":"jagannadh.teki@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260429081313.151656-1-weijie.gao@mediatek.com/mbox/","series":[{"id":502013,"url":"http://patchwork.ozlabs.org/api/1.1/series/502013/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=502013","date":"2026-04-29T08:13:13","name":"mtd: spinand: add support for Etron SPI-NAND flashes","version":1,"mbox":"http://patchwork.ozlabs.org/series/502013/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230101/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230101/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256\n header.s=dk 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b=cuWL3v3MSKcBpbXIggT0aLgrpFG2MzrzhZspz+ntO4BjqFI9OFHu+okeqUZZqGJ+B+3X1nIqx0Wy70+gwDlnOqEgzCLmoCJ6RzBzT8iltfawdlLM7I09fgOckFL/Mp9Hj7yLmF8n4SPBH5HghdWYSGccbvzNiW6ouaXI6JTStsQ=;","X-CID-P-RULE":"Release_Ham","X-CID-O-INFO":"VERSION:1.3.12, REQID:5c485fd4-03c6-4dd8-a333-83a4dbfbd8b2,\n IP:0,\n U\n RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO\n N:release,TS:-25","X-CID-META":"VersionHash:e7bac3a, CLOUDID:c4e2b070-3b7f-4b26-b2f9-40f0deecb36d,\n B\n ulkID:nil,BulkQuantity:0,Recheck:0,SF:102|836|865|888|898,TC:-5,Content:0|\n 15|50,EDM:-3,IP:nil,URL:99|1,File:130,RT:0,Bulk:nil,QS:nil,BEC:-1,COL:0,OS\n I:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0","X-CID-BVR":"2,SSN|SDN","X-CID-BAS":"2,SSN|SDN,0,_","X-CID-FACTOR":"TF_CID_SPAM_SNR,TF_CID_SPAM_ULS","X-CID-RHF":"D41D8CD98F00B204E9800998ECF8427E","From":"Weijie Gao ","To":"","CC":"GSS_MTK_Uboot_upstream , Tom Rini\n , Dario Binacchi ,\n Michael Trimarchi , Frieder Schrempf\n , Mikhail Kshevetskiy\n , Tianling Shen , Miquel\n Raynal , Cheng Ming Lin\n , Takahiro Kuwano ,\n Weijie Gao ","Subject":"[PATCH] mtd: spinand: add support for Etron SPI-NAND flashes","Date":"Wed, 29 Apr 2026 16:13:13 +0800","Message-ID":"<20260429081313.151656-1-weijie.gao@mediatek.com>","X-Mailer":"git-send-email 2.17.0","MIME-Version":"1.0","Content-Type":"text/plain","X-MTK":"N","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"This patch adds some Etron SPI-NAND flashes from 1Gb to 8Gb with\n4-bits/8-bits On-die ECC support.\n\nEM73C044VCF/EM73D044VCO/EM73E044VCE/EM73F044VCA are tested on MediaTek\nfilogic MT7988 reference board.\n\nDatasheets:\nhttps://etron.com/wp-content/uploads/2024/08/EM73C044VCF-SPI-NAND-Flash_Rev-1.03.pdf\nhttps://etron.com/wp-content/uploads/2022/04/EM73D044VCOR-SPI-NAND-Flash_Rev-1.00.pdf\nhttps://etron.com/wp-content/uploads/2022/04/EM78DE044VC-SPI-NAND-Flash_Rev-1.01.pdf\nhttps://etron.com/wp-content/uploads/2024/08/EM73E044VCEG-SPI-NAND-Flash_Rev-1.00.pdf\nhttps://etron.com/wp-content/uploads/2022/04/EM738F044VCA-SPI-NAND-Flash_Rev-1.02.pdf\n\nSigned-off-by: Weijie Gao \n---\n drivers/mtd/nand/spi/Makefile | 5 +-\n drivers/mtd/nand/spi/core.c | 1 +\n drivers/mtd/nand/spi/etron.c | 240 ++++++++++++++++++++++++++++++++++\n include/linux/mtd/spinand.h | 1 +\n 4 files changed, 245 insertions(+), 2 deletions(-)\n create mode 100644 drivers/mtd/nand/spi/etron.c","diff":"diff --git a/drivers/mtd/nand/spi/Makefile b/drivers/mtd/nand/spi/Makefile\nindex a7a0b2cb4b9..4664280c8d6 100644\n--- a/drivers/mtd/nand/spi/Makefile\n+++ b/drivers/mtd/nand/spi/Makefile\n@@ -1,6 +1,7 @@\n # SPDX-License-Identifier: GPL-2.0\n \n spinand-objs := core.o otp.o\n-spinand-objs += alliancememory.o ato.o esmt.o fmsh.o foresee.o gigadevice.o macronix.o\n-spinand-objs += micron.o paragon.o skyhigh.o toshiba.o winbond.o xtx.o\n+spinand-objs += alliancememory.o ato.o esmt.o etron.o fmsh.o foresee.o\n+spinand-objs += gigadevice.o macronix.o micron.o paragon.o skyhigh.o toshiba.o\n+spinand-objs += winbond.o xtx.o\n obj-$(CONFIG_MTD_SPI_NAND) += spinand.o\ndiff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c\nindex 14af4264612..b032b0fec24 100644\n--- a/drivers/mtd/nand/spi/core.c\n+++ b/drivers/mtd/nand/spi/core.c\n@@ -1227,6 +1227,7 @@ static const struct spinand_manufacturer *spinand_manufacturers[] = {\n \t&alliancememory_spinand_manufacturer,\n \t&ato_spinand_manufacturer,\n \t&esmt_c8_spinand_manufacturer,\n+\t&etron_spinand_manufacturer,\n \t&fmsh_spinand_manufacturer,\n \t&foresee_spinand_manufacturer,\n \t&gigadevice_spinand_manufacturer,\ndiff --git a/drivers/mtd/nand/spi/etron.c b/drivers/mtd/nand/spi/etron.c\nnew file mode 100644\nindex 00000000000..35d60180b34\n--- /dev/null\n+++ b/drivers/mtd/nand/spi/etron.c\n@@ -0,0 +1,240 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (c) 2020 Etron Technology, Inc.\n+ *\n+ */\n+#ifndef __UBOOT__\n+#include \n+#include \n+#endif\n+#include \n+\n+#define SPINAND_MFR_ETRON\t\t0xD5\n+\n+#define STATUS_ECC_LIMIT_BITFLIPS\t(3 << 4)\n+\n+static SPINAND_OP_VARIANTS(read_cache_variants,\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_1S_4S_4S_OP(0, 1, NULL, 0, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_1S_1S_4S_OP(0, 1, NULL, 0, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_1S_2S_2S_OP(0, 1, NULL, 0, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_1S_1S_2S_OP(0, 1, NULL, 0, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_FAST_1S_1S_1S_OP(0, 1, NULL, 0, 0),\n+\t\tSPINAND_PAGE_READ_FROM_CACHE_1S_1S_1S_OP(0, 1, NULL, 0, 0));\n+\n+static SPINAND_OP_VARIANTS(write_cache_variants,\n+\t\tSPINAND_PROG_LOAD_1S_1S_4S_OP(true, 0, NULL, 0),\n+\t\tSPINAND_PROG_LOAD_1S_1S_1S_OP(true, 0, NULL, 0));\n+\n+static SPINAND_OP_VARIANTS(update_cache_variants,\n+\t\tSPINAND_PROG_LOAD_1S_1S_4S_OP(false, 0, NULL, 0),\n+\t\tSPINAND_PROG_LOAD_1S_1S_1S_OP(false, 0, NULL, 0));\n+\n+static int etron_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section,\n+\t\t\t\t struct mtd_oob_region *region)\n+{\n+\tstruct spinand_device *spinand = mtd_to_spinand(mtd);\n+\n+\tif (section >= spinand->base.memorg.pagesize / mtd->ecc_step_size)\n+\t\treturn -ERANGE;\n+\n+\tregion->offset = (8 * section) + 32;\n+\tregion->length = 8;\n+\n+\treturn 0;\n+}\n+\n+static int etron_ecc4_ooblayout_free(struct mtd_info *mtd, int section,\n+\t\t\t\t struct mtd_oob_region *region)\n+{\n+\tstruct spinand_device *spinand = mtd_to_spinand(mtd);\n+\n+\tif (section >= spinand->base.memorg.pagesize / mtd->ecc_step_size)\n+\t\treturn -ERANGE;\n+\n+\tif (section) {\n+\t\tregion->offset = 8 * section;\n+\t\tregion->length = 8;\n+\t} else {\n+\t\t/* section 0 has two bytes reserved for bad block mark */\n+\t\tregion->offset = 2;\n+\t\tregion->length = 6;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct mtd_ooblayout_ops etron_ecc4_ooblayout = {\n+\t.ecc = etron_ecc4_ooblayout_ecc,\n+\t.rfree = etron_ecc4_ooblayout_free,\n+};\n+\n+static int etron_ecc8_ooblayout_ecc(struct mtd_info *mtd, int section,\n+\t\t\t\t struct mtd_oob_region *region)\n+{\n+\tstruct spinand_device *spinand = mtd_to_spinand(mtd);\n+\n+\tif (section >= spinand->base.memorg.pagesize / mtd->ecc_step_size)\n+\t\treturn -ERANGE;\n+\n+\tregion->offset = (14 * section) + 72;\n+\tregion->length = 14;\n+\n+\treturn 0;\n+}\n+\n+static int etron_ecc8_ooblayout_free(struct mtd_info *mtd, int section,\n+\t\t\t\t struct mtd_oob_region *region)\n+{\n+\tstruct spinand_device *spinand = mtd_to_spinand(mtd);\n+\n+\tif (section >= spinand->base.memorg.pagesize / mtd->ecc_step_size)\n+\t\treturn -ERANGE;\n+\n+\tif (section) {\n+\t\tregion->offset = 18 * section;\n+\t\tregion->length = 18;\n+\t} else {\n+\t\t/* section 0 has two bytes reserved for bad block mark */\n+\t\tregion->offset = 2;\n+\t\tregion->length = 16;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct mtd_ooblayout_ops etron_ecc8_ooblayout = {\n+\t.ecc = etron_ecc8_ooblayout_ecc,\n+\t.rfree = etron_ecc8_ooblayout_free,\n+};\n+\n+static int etron_ecc_get_status(struct spinand_device *spinand, u8 status)\n+{\n+\tstruct nand_device *nand = spinand_to_nand(spinand);\n+\n+\tswitch (status & STATUS_ECC_MASK) {\n+\tcase STATUS_ECC_NO_BITFLIPS:\n+\t\treturn 0;\n+\n+\tcase STATUS_ECC_UNCOR_ERROR:\n+\t\treturn -EBADMSG;\n+\n+\tcase STATUS_ECC_HAS_BITFLIPS:\n+\t\treturn nand->eccreq.strength >> 1;\n+\n+\tcase STATUS_ECC_LIMIT_BITFLIPS:\n+\t\treturn nand->eccreq.strength;\n+\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn -EINVAL;\n+}\n+\n+static const struct spinand_info etron_spinand_table[] = {\n+\t/* EM73C 1Gb 3.3V */\n+\tSPINAND_INFO(\"EM73C044VCF\",\n+\t\t SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x25),\n+\t\t NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),\n+\t\t NAND_ECCREQ(4, 512),\n+\t\t SPINAND_INFO_OP_VARIANTS(&read_cache_variants,\n+\t\t\t\t\t &write_cache_variants,\n+\t\t\t\t\t &update_cache_variants),\n+\t\t SPINAND_HAS_QE_BIT,\n+\t\t SPINAND_ECCINFO(&etron_ecc4_ooblayout,\n+\t\t\t\t etron_ecc_get_status)),\n+\t/* EM7xD 2Gb */\n+\tSPINAND_INFO(\"EM73D044VCR\",\n+\t\t SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x41),\n+\t\t NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),\n+\t\t NAND_ECCREQ(4, 512),\n+\t\t SPINAND_INFO_OP_VARIANTS(&read_cache_variants,\n+\t\t\t\t\t &write_cache_variants,\n+\t\t\t\t\t &update_cache_variants),\n+\t\t SPINAND_HAS_QE_BIT,\n+\t\t SPINAND_ECCINFO(&etron_ecc4_ooblayout,\n+\t\t\t\t etron_ecc_get_status)),\n+\tSPINAND_INFO(\"EM73D044VCO\",\n+\t\t SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3A),\n+\t\t NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),\n+\t\t NAND_ECCREQ(8, 512),\n+\t\t SPINAND_INFO_OP_VARIANTS(&read_cache_variants,\n+\t\t\t\t\t &write_cache_variants,\n+\t\t\t\t\t &update_cache_variants),\n+\t\t SPINAND_HAS_QE_BIT,\n+\t\t SPINAND_ECCINFO(&etron_ecc8_ooblayout,\n+\t\t\t\t etron_ecc_get_status)),\n+\tSPINAND_INFO(\"EM78D044VCM\",\n+\t\t SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x8E),\n+\t\t NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),\n+\t\t NAND_ECCREQ(8, 512),\n+\t\t SPINAND_INFO_OP_VARIANTS(&read_cache_variants,\n+\t\t\t\t\t &write_cache_variants,\n+\t\t\t\t\t &update_cache_variants),\n+\t\t SPINAND_HAS_QE_BIT,\n+\t\t SPINAND_ECCINFO(&etron_ecc8_ooblayout,\n+\t\t\t\t etron_ecc_get_status)),\n+\t/* EM7xE 4Gb */\n+\tSPINAND_INFO(\"EM73E044VCG\",\n+\t\t SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x42),\n+\t\t NAND_MEMORG(1, 2048, 64, 64, 4096, 80, 1, 1, 1),\n+\t\t NAND_ECCREQ(4, 512),\n+\t\t SPINAND_INFO_OP_VARIANTS(&read_cache_variants,\n+\t\t\t\t\t &write_cache_variants,\n+\t\t\t\t\t &update_cache_variants),\n+\t\t SPINAND_HAS_QE_BIT,\n+\t\t SPINAND_ECCINFO(&etron_ecc4_ooblayout,\n+\t\t\t\t etron_ecc_get_status)),\n+\tSPINAND_INFO(\"EM73E044VCE\",\n+\t\t SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3B),\n+\t\t NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),\n+\t\t NAND_ECCREQ(8, 512),\n+\t\t SPINAND_INFO_OP_VARIANTS(&read_cache_variants,\n+\t\t\t\t\t &write_cache_variants,\n+\t\t\t\t\t &update_cache_variants),\n+\t\t SPINAND_HAS_QE_BIT,\n+\t\t SPINAND_ECCINFO(&etron_ecc8_ooblayout,\n+\t\t\t\t etron_ecc_get_status)),\n+\tSPINAND_INFO(\"EM78E044VCD\",\n+\t\t SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x8F),\n+\t\t NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),\n+\t\t NAND_ECCREQ(8, 512),\n+\t\t SPINAND_INFO_OP_VARIANTS(&read_cache_variants,\n+\t\t\t\t\t &write_cache_variants,\n+\t\t\t\t\t &update_cache_variants),\n+\t\t SPINAND_HAS_QE_BIT,\n+\t\t SPINAND_ECCINFO(&etron_ecc8_ooblayout,\n+\t\t\t\t etron_ecc_get_status)),\n+\t/* EM7xF 8Gb */\n+\tSPINAND_INFO(\"EM73F044VCA\",\n+\t\t SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x2D),\n+\t\t NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),\n+\t\t NAND_ECCREQ(8, 512),\n+\t\t SPINAND_INFO_OP_VARIANTS(&read_cache_variants,\n+\t\t\t\t\t &write_cache_variants,\n+\t\t\t\t\t &update_cache_variants),\n+\t\t SPINAND_HAS_QE_BIT,\n+\t\t SPINAND_ECCINFO(&etron_ecc8_ooblayout,\n+\t\t\t\t etron_ecc_get_status)),\n+\tSPINAND_INFO(\"EM78F044VCA\",\n+\t\t SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x8D),\n+\t\t NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1),\n+\t\t NAND_ECCREQ(8, 512),\n+\t\t SPINAND_INFO_OP_VARIANTS(&read_cache_variants,\n+\t\t\t\t\t &write_cache_variants,\n+\t\t\t\t\t &update_cache_variants),\n+\t\t SPINAND_HAS_QE_BIT,\n+\t\t SPINAND_ECCINFO(&etron_ecc8_ooblayout,\n+\t\t\t\t etron_ecc_get_status)),\n+};\n+\n+static const struct spinand_manufacturer_ops etron_spinand_manuf_ops = {\n+};\n+\n+const struct spinand_manufacturer etron_spinand_manufacturer = {\n+\t.id = SPINAND_MFR_ETRON,\n+\t.name = \"Etron\",\n+\t.chips = etron_spinand_table,\n+\t.nchips = ARRAY_SIZE(etron_spinand_table),\n+\t.ops = &etron_spinand_manuf_ops,\n+};\ndiff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h\nindex e9561c0a395..8f46c31a427 100644\n--- a/include/linux/mtd/spinand.h\n+++ b/include/linux/mtd/spinand.h\n@@ -361,6 +361,7 @@ struct spinand_manufacturer {\n extern const struct spinand_manufacturer alliancememory_spinand_manufacturer;\n extern const struct spinand_manufacturer ato_spinand_manufacturer;\n extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer;\n+extern const struct spinand_manufacturer etron_spinand_manufacturer;\n extern const struct spinand_manufacturer fmsh_spinand_manufacturer;\n extern const struct spinand_manufacturer foresee_spinand_manufacturer;\n extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;\n","prefixes":[]}