{"id":2230067,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230067/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260429-d3cold-v5-4-89e9735b9df6@oss.qualcomm.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.1/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260429-d3cold-v5-4-89e9735b9df6@oss.qualcomm.com>","date":"2026-04-29T06:42:26","name":"[v5,4/5] PCI: dwc: Use common D3cold eligibility helper in suspend path","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"635cab1774ff2c09ce9af00b697ca2cc7b67f977","submitter":{"id":89908,"url":"http://patchwork.ozlabs.org/api/1.1/people/89908/?format=json","name":"Krishna Chaitanya Chundru","email":"krishna.chundru@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260429-d3cold-v5-4-89e9735b9df6@oss.qualcomm.com/mbox/","series":[{"id":502001,"url":"http://patchwork.ozlabs.org/api/1.1/series/502001/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=502001","date":"2026-04-29T06:42:22","name":"PCI: qcom: Add D3cold support","version":5,"mbox":"http://patchwork.ozlabs.org/series/502001/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230067/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230067/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=ZOIJzAjH;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=Uyz2fRGj;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260429-d3cold-v5-4-89e9735b9df6@oss.qualcomm.com>","References":"<20260429-d3cold-v5-0-89e9735b9df6@oss.qualcomm.com>","In-Reply-To":"<20260429-d3cold-v5-0-89e9735b9df6@oss.qualcomm.com>","To":"Jingoo Han ,\n Manivannan Sadhasivam ,\n Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= , Rob Herring ,\n Bjorn Helgaas , Will Deacon ","Cc":"linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,\n linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n jonathanh@nvidia.com, bjorn.andersson@oss.qualcomm.com,\n Krishna Chaitanya Chundru ","X-Mailer":"b4 0.15.2","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1777444949; l=3749;\n i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id;\n bh=5PQqOmdR5OOC75CCpY/aytMD49zycczPJnqwX7jwyag=;\n b=w+R58IbthfJ5zUxuVUnEnIOCN/KuwhYjhFN9dhYCENxXhUC/7WxDiftz3Zj1nuozc4k/w19wj\n NaeGrMJzDtkC/fvBKOymfM2HEcyFt57ItD5WSujJebuWSV9kTuvBwYA","X-Developer-Key":"i=krishna.chundru@oss.qualcomm.com; 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However, such\ndevices typically remain in D0 and are already covered by the new helper's\nrequirement that all endpoints be in D3hot before the devices under host\nbridge may enter D3cold.\n\nSo, replace the local L1/L1SS-based check in dw_pcie_suspend_noirq() with\nthe shared pci_host_common_d3cold_possible() helper to decide whether the\ndevices under host bridge can safely transition to D3cold.\n\nIn addition, propagate PME-from-D3cold capability information from the\nhelper and record it in skip_pwrctrl_off. Some devices (e.g. M.2 cards\nwithout auxiliary power) may lose PME detection when main power is\nremoved, even if they advertise PME-from-D3cold support. This allows\ncontroller power-off to be skipped when required to preserve wakeup\nfunctionality.\n\nUpdate the suspended flag in dw_pcie_resume_noirq() only after the PCIe\nlink resumes successfully, to avoid marking the controller active when\nlink resume fails.\n\nSigned-off-by: Krishna Chaitanya Chundru \n---\n drivers/pci/controller/dwc/pcie-designware-host.c | 15 +++++++--------\n drivers/pci/controller/dwc/pcie-designware.h | 1 +\n 2 files changed, 8 insertions(+), 8 deletions(-)","diff":"diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c\nindex c9517a348836..9e409a1909e6 100644\n--- a/drivers/pci/controller/dwc/pcie-designware-host.c\n+++ b/drivers/pci/controller/dwc/pcie-designware-host.c\n@@ -16,9 +16,11 @@\n #include \n #include \n #include \n+#include \n #include \n #include \n \n+#include \"../pci-host-common.h\"\n #include \"../../pci.h\"\n #include \"pcie-designware.h\"\n \n@@ -1218,18 +1220,14 @@ static int dw_pcie_pme_turn_off(struct dw_pcie *pci)\n \n int dw_pcie_suspend_noirq(struct dw_pcie *pci)\n {\n-\tu8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);\n+\tbool pme_capable = false;\n \tint ret = 0;\n \tu32 val;\n \n \tif (!dw_pcie_link_up(pci))\n \t\tgoto stop_link;\n \n-\t/*\n-\t * If L1SS is supported, then do not put the link into L2 as some\n-\t * devices such as NVMe expect low resume latency.\n-\t */\n-\tif (dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKCTL) & PCI_EXP_LNKCTL_ASPM_L1)\n+\tif (!pci_host_common_d3cold_possible(pci->pp.bridge, &pme_capable))\n \t\treturn 0;\n \n \tif (pci->pp.ops->pme_turn_off) {\n@@ -1273,6 +1271,7 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci)\n \tudelay(1);\n \n stop_link:\n+\tpci->pp.skip_pwrctrl_off = pme_capable;\n \tdw_pcie_stop_link(pci);\n \tif (pci->pp.ops->deinit)\n \t\tpci->pp.ops->deinit(&pci->pp);\n@@ -1290,8 +1289,6 @@ int dw_pcie_resume_noirq(struct dw_pcie *pci)\n \tif (!pci->suspended)\n \t\treturn 0;\n \n-\tpci->suspended = false;\n-\n \tif (pci->pp.ops->init) {\n \t\tret = pci->pp.ops->init(&pci->pp);\n \t\tif (ret) {\n@@ -1313,6 +1310,8 @@ int dw_pcie_resume_noirq(struct dw_pcie *pci)\n \tif (pci->pp.ops->post_init)\n \t\tpci->pp.ops->post_init(&pci->pp);\n \n+\tpci->suspended = false;\n+\n \treturn 0;\n \n err_stop_link:\ndiff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h\nindex 3e69ef60165b..e759c5c7257e 100644\n--- a/drivers/pci/controller/dwc/pcie-designware.h\n+++ b/drivers/pci/controller/dwc/pcie-designware.h\n@@ -450,6 +450,7 @@ struct dw_pcie_rp {\n \tbool\t\t\tecam_enabled;\n \tbool\t\t\tnative_ecam;\n \tbool skip_l23_ready;\n+\tbool\t\t\tskip_pwrctrl_off;\n };\n \n struct dw_pcie_ep_ops {\n","prefixes":["v5","4/5"]}