{"id":2230065,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230065/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260429-d3cold-v5-2-89e9735b9df6@oss.qualcomm.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.1/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260429-d3cold-v5-2-89e9735b9df6@oss.qualcomm.com>","date":"2026-04-29T06:42:24","name":"[v5,2/5] PCI: qcom: Add .get_ltssm() helper","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"6f0ad8207658fb02ad76c6e1e45ee0ff3055911f","submitter":{"id":89908,"url":"http://patchwork.ozlabs.org/api/1.1/people/89908/?format=json","name":"Krishna Chaitanya Chundru","email":"krishna.chundru@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260429-d3cold-v5-2-89e9735b9df6@oss.qualcomm.com/mbox/","series":[{"id":502001,"url":"http://patchwork.ozlabs.org/api/1.1/series/502001/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=502001","date":"2026-04-29T06:42:22","name":"PCI: qcom: Add D3cold support","version":5,"mbox":"http://patchwork.ozlabs.org/series/502001/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230065/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230065/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=B8IQRfIN;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=ZmWRYlJQ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260429-d3cold-v5-2-89e9735b9df6@oss.qualcomm.com>","References":"<20260429-d3cold-v5-0-89e9735b9df6@oss.qualcomm.com>","In-Reply-To":"<20260429-d3cold-v5-0-89e9735b9df6@oss.qualcomm.com>","To":"Jingoo Han ,\n Manivannan Sadhasivam ,\n Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= , Rob Herring ,\n Bjorn Helgaas , Will Deacon ","Cc":"linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,\n linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n jonathanh@nvidia.com, bjorn.andersson@oss.qualcomm.com,\n Krishna Chaitanya Chundru ","X-Mailer":"b4 0.15.2","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1777444949; l=4016;\n i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id;\n bh=kJOcLpJ2/X+O6jVsxBIhyhEdHIhlOc1Lfh/fcN/6y0g=;\n b=XJXnUN7dlDghLSLQOMsNyk25AY1nkORIexsqqq+avIno/Mb0yfR49fPhveofsZcDVoM3HEBRC\n QbzePAgnlAbAtE0iREwuOauc0FMh5cJy2CWrHfPnjffh5SR3E15uxZo","X-Developer-Key":"i=krishna.chundru@oss.qualcomm.com; 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For newer platforms, the LTSSM state is read from the\nPARF_LTSSM register, while older platforms continue to retrieve it from\nELBI_SYS_STTS.\n\nThis helper is used in place of direct DBI-based link state checks in\nthe D3cold path after sending PME turn-off message, ensuring the LTSSM\nstate can be queried safely even after DBI access is no longer valid.\n\nSigned-off-by: Krishna Chaitanya Chundru \n---\n drivers/pci/controller/dwc/pcie-qcom.c | 31 +++++++++++++++++++++++++++++++\n 1 file changed, 31 insertions(+)","diff":"diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c\nindex af6bf5cce65b..085300c1d1ec 100644\n--- a/drivers/pci/controller/dwc/pcie-qcom.c\n+++ b/drivers/pci/controller/dwc/pcie-qcom.c\n@@ -71,6 +71,7 @@\n \n /* ELBI registers */\n #define ELBI_SYS_CTRL\t\t\t\t0x04\n+#define ELBI_SYS_STTS\t\t\t\t0x08\n \n /* DBI registers */\n #define AXI_MSTR_RESP_COMP_CTRL0\t\t0x818\n@@ -131,6 +132,7 @@\n \n /* PARF_LTSSM register fields */\n #define LTSSM_EN\t\t\t\tBIT(8)\n+#define PARF_LTSSM_STATE_MASK\t\t\tGENMASK(5, 0)\n \n /* PARF_NO_SNOOP_OVERRIDE register fields */\n #define WR_NO_SNOOP_OVERRIDE_EN\t\t\tBIT(1)\n@@ -145,6 +147,9 @@\n /* ELBI_SYS_CTRL register fields */\n #define ELBI_SYS_CTRL_LT_ENABLE\t\t\tBIT(0)\n \n+/* ELBI_SYS_STTS register fields */\n+#define ELBI_SYS_STTS_LTSSM_STATE_MASK\t\tGENMASK(17, 12)\n+\n /* AXI_MSTR_RESP_COMP_CTRL0 register fields */\n #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K\t0x4\n #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K\t0x5\n@@ -245,6 +250,7 @@ struct qcom_pcie_ops {\n \tvoid (*deinit)(struct qcom_pcie *pcie);\n \tvoid (*ltssm_enable)(struct qcom_pcie *pcie);\n \tint (*config_sid)(struct qcom_pcie *pcie);\n+\tenum dw_pcie_ltssm (*get_ltssm)(struct qcom_pcie *pcie);\n };\n \n /**\n@@ -428,6 +434,15 @@ static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie)\n \twritel(val, pci->elbi_base + ELBI_SYS_CTRL);\n }\n \n+static enum dw_pcie_ltssm qcom_pcie_2_1_0_get_ltssm(struct qcom_pcie *pcie)\n+{\n+\tstruct dw_pcie *pci = pcie->pci;\n+\tu32 val;\n+\n+\tval = readl(pci->elbi_base + ELBI_SYS_STTS);\n+\treturn (enum dw_pcie_ltssm)FIELD_GET(ELBI_SYS_STTS_LTSSM_STATE_MASK, val);\n+}\n+\n static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)\n {\n \tstruct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;\n@@ -1260,6 +1275,19 @@ static bool qcom_pcie_link_up(struct dw_pcie *pci)\n \treturn val & PCI_EXP_LNKSTA_DLLLA;\n }\n \n+static enum dw_pcie_ltssm qcom_pcie_get_ltssm(struct dw_pcie *pci)\n+{\n+\tstruct qcom_pcie *pcie = to_qcom_pcie(pci);\n+\tu32 val;\n+\n+\tif (pcie->cfg->ops->ltssm_enable)\n+\t\treturn pcie->cfg->ops->get_ltssm(pcie);\n+\n+\tval = readl(pcie->parf + PARF_LTSSM);\n+\n+\treturn (enum dw_pcie_ltssm)FIELD_GET(PARF_LTSSM_STATE_MASK, val);\n+}\n+\n static void qcom_pcie_phy_power_off(struct qcom_pcie *pcie)\n {\n \tstruct qcom_pcie_port *port;\n@@ -1385,6 +1413,7 @@ static const struct qcom_pcie_ops ops_2_1_0 = {\n \t.post_init = qcom_pcie_post_init_2_1_0,\n \t.deinit = qcom_pcie_deinit_2_1_0,\n \t.ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,\n+\t.get_ltssm = qcom_pcie_2_1_0_get_ltssm,\n };\n \n /* Qcom IP rev.: 1.0.0\tSynopsys IP rev.: 4.11a */\n@@ -1394,6 +1423,7 @@ static const struct qcom_pcie_ops ops_1_0_0 = {\n \t.post_init = qcom_pcie_post_init_1_0_0,\n \t.deinit = qcom_pcie_deinit_1_0_0,\n \t.ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,\n+\t.get_ltssm = qcom_pcie_2_1_0_get_ltssm,\n };\n \n /* Qcom IP rev.: 2.3.2\tSynopsys IP rev.: 4.21a */\n@@ -1512,6 +1542,7 @@ static const struct qcom_pcie_cfg cfg_fw_managed = {\n static const struct dw_pcie_ops dw_pcie_ops = {\n \t.link_up = qcom_pcie_link_up,\n \t.start_link = qcom_pcie_start_link,\n+\t.get_ltssm = qcom_pcie_get_ltssm,\n };\n \n static int qcom_pcie_icc_init(struct qcom_pcie *pcie)\n","prefixes":["v5","2/5"]}