{"id":2230049,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230049/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260429061122.807346-1-amhetre@nvidia.com/","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/1.1/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260429061122.807346-1-amhetre@nvidia.com>","date":"2026-04-29T06:11:22","name":"memory: tegra: Wire up system sleep PM ops","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"89a09fb903a6cb0bf9699c52f40c7d3eb0781444","submitter":{"id":75198,"url":"http://patchwork.ozlabs.org/api/1.1/people/75198/?format=json","name":"Ashish Mhetre","email":"amhetre@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260429061122.807346-1-amhetre@nvidia.com/mbox/","series":[{"id":501990,"url":"http://patchwork.ozlabs.org/api/1.1/series/501990/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/list/?series=501990","date":"2026-04-29T06:11:22","name":"memory: tegra: Wire up system sleep PM ops","version":1,"mbox":"http://patchwork.ozlabs.org/series/501990/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230049/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230049/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=nyxVOYRw;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-tegra+bounces-14047-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=\"nyxVOYRw\"","smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=40.107.200.10","smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com","smtp.subspace.kernel.org;\n spf=fail smtp.mailfrom=nvidia.com"],"Received":["from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g56QT1BVHz1yHX\n\tfor ; Wed, 29 Apr 2026 16:12:01 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id 29A8C300B849\n\tfor ; Wed, 29 Apr 2026 06:11:58 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id A6826330644;\n\tWed, 29 Apr 2026 06:11:57 +0000 (UTC)","from CH5PR02CU005.outbound.protection.outlook.com\n (mail-northcentralusazon11012010.outbound.protection.outlook.com\n [40.107.200.10])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id ED3AE320CCF;\n\tWed, 29 Apr 2026 06:11:55 +0000 (UTC)","from BY5PR16CA0023.namprd16.prod.outlook.com (2603:10b6:a03:1a0::36)\n by CY3PR12MB9554.namprd12.prod.outlook.com (2603:10b6:930:109::19) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9870.16; Wed, 29 Apr\n 2026 06:11:51 +0000","from SJ1PEPF00001CDD.namprd05.prod.outlook.com\n (2603:10b6:a03:1a0:cafe::ed) by BY5PR16CA0023.outlook.office365.com\n (2603:10b6:a03:1a0::36) with Microsoft SMTP Server (version=TLS1_3,\n cipher=TLS_AES_256_GCM_SHA384) id 15.20.9846.30 via Frontend Transport; Wed,\n 29 Apr 2026 06:11:51 +0000","from mail.nvidia.com (216.228.117.161) by\n SJ1PEPF00001CDD.mail.protection.outlook.com (10.167.242.5) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.9846.18 via Frontend Transport; Wed, 29 Apr 2026 06:11:46 +0000","from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com\n (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 28 Apr\n 2026 23:11:30 -0700","from rnnvmail203.nvidia.com (10.129.68.9) by rnnvmail203.nvidia.com\n (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 28 Apr\n 2026 23:11:30 -0700","from build-amhetre-focal-20250829.internal (10.127.8.12) by\n mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server id 15.2.2562.20 via\n Frontend Transport; Tue, 28 Apr 2026 23:11:30 -0700"],"ARC-Seal":["i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1777443117; cv=fail;\n b=rs8Sxm83l9027lU/r0q+i1jZFBXh8GbflZ5MAksIaVOSTUZEGbZjZ0bXDmfb/ksQ/xHyXyYSIPca4M42ZC1NowvtfHdSPcu81rrNuBZtvgTj49nWPRI0GCBpZjfqtO+AqNnxLGPCA1+UspWRUVbSY7txW4OVYK50DTRpjRqh3PI=","i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=HOCEjT4KSznTF3WW6fcfDht+r+osnASCd9XtDuwa4hDoKA15VBKAsag0yoeRFfyNNNETVltDNZShW7Tn3e8p3uVJuk8aQqrRq1DfuRGJ7j8qXKB8OWOmON9ukZKJxJLlcrQqXvhQSIqOKNonvGW+GK9OK7m3x9wjx9Wsm7hptJiqcKwqrYSxTsV1ADrmm8cAgheIVR6ZktCA6Z7vZdlcQgaVrDgHUZjKB6T57HxDLweqNC6e3if6yTEDkoSGPVPFyDMQqV3n74QJlxyBvkddiwkicvyfCQRo10rWzFM6PYvK9g3yp6wbFffiBIAUrHvTRQoy79DUXej9YYbF0DIGdw=="],"ARC-Message-Signature":["i=2; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1777443117; c=relaxed/simple;\n\tbh=2QL7o27rN8lvcMKbGaC6A1xO46kjKR7/ltWm81538qU=;\n\th=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type;\n b=MSlHEV18Ty6EE7pP3n22dUgplY3HPPlEffXH0dxj0V5J5kDHC17iWTJaIlEI+YMG4npEsK1+Z4WKuD7kPonGrCK+YHDjHNWCjmVzekbvIaEGPG90YTIGKMsuuPdr5vXHzqvm98UV+ljHyXDN09ldnsDqMsF3O3ZCc2RkEIJ05dI=","i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=4rJ7+el17Bl3pz6UOPTpNB+zZOXHzxrw2A29bzS7qlA=;\n b=w0NR//HM3d3kEzStN2DB9g8i5w95JlZSkk4N9fxUdUMbXzb2M0tlHFCcD7MKebREa/5zT7Y9r8Ll3F9E5Y0PE+yWCI4cQD6J6kUR6MbRbr5Dpt9tj9BaSPTACjPFmGEnkFcKLa89FwKK8+U6xfor3eSrrqWV5tD7cHJYuTwjviLEjmbCOhtZVhAX+FIkuWdZgYkf+CnmloO0koP+vVZ8tN9kPPh39rVqzW/fkOuMektCIZVU46EMstktHVVSHKsmXsVvlTIh2P6/29Qk6q1hqFOeZh7flqLFY4HUqDX28tp2+32oCrqYLTPWQ70IuWIhF4Y3J6MAMcppaxRQnA8W7g=="],"ARC-Authentication-Results":["i=2; smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=nvidia.com;\n spf=fail smtp.mailfrom=nvidia.com;\n dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=nyxVOYRw; arc=fail smtp.client-ip=40.107.200.10","i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.161) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none (0)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=4rJ7+el17Bl3pz6UOPTpNB+zZOXHzxrw2A29bzS7qlA=;\n b=nyxVOYRwwv98tuVCDT7otO7cDyXN0SLSTp/yxMiNac6JG19BT0DXP1ebEw956ObhRS4xx1+bUEyd6p4LrLGMpb5/cOJU1bl+5Arywg2o2W5QenWkynscuUmPEMw0zSlDrBEk8Wn5Fz0q8BmbxI3/iRgMDSElXvzHC7DFmsvo19rhL8ET9nqZbsGxcsvK7rKGRqCixmbwwJRI9KkLV3+vkqc0BOx3pDjIxaloFbMZaYkxHyM/4emwFMW/WHpFn13pIvDoI9lLOj8c6gNOM3I0SlEaGBK3B0mb5gxHxFk6bgzL3U+C65DrmABvOkXtRDPcYilsmvNt7IO4esM6vtmldw==","X-MS-Exchange-Authentication-Results":"spf=pass (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;","Received-SPF":"Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C","From":"Ashish Mhetre ","To":", , ","CC":", ,\n\t, Ashish Mhetre ","Subject":"[PATCH] memory: tegra: Wire up system sleep PM ops","Date":"Wed, 29 Apr 2026 06:11:22 +0000","Message-ID":"<20260429061122.807346-1-amhetre@nvidia.com>","X-Mailer":"git-send-email 2.50.1","Precedence":"bulk","X-Mailing-List":"linux-tegra@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","X-NVConfidentiality":"public","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-NV-OnPremToCloud":"ExternallySecured","X-EOPAttributedMessage":"0","X-MS-PublicTrafficType":"Email","X-MS-TrafficTypeDiagnostic":"SJ1PEPF00001CDD:EE_|CY3PR12MB9554:EE_","X-MS-Office365-Filtering-Correlation-Id":"7fd09dc6-a60c-4df8-4761-08dea5b6314d","X-MS-Exchange-SenderADCheck":"1","X-MS-Exchange-AntiSpam-Relay":"0","X-Microsoft-Antispam":"\n\tBCL:0;ARA:13230040|82310400026|376014|36860700016|1800799024|56012099003|18002099003;","X-Microsoft-Antispam-Message-Info":"\n\tBaGNyuQ2K5jv84CLw0vv+dL5ShjqLseOlMj2+MJU0twVFkDnWx5LdBFlpP5N7R+g3n3hGG9cnc0NgpN2v4vnZrWCAXviIw/X93JGdYk1iNLj4YsUhAm60MTXwYITPY21VNZ+DkpqcQBTA+abuiXHvOIDlL01nSqxkwjWFhtJNZsMLtq5SSVF1IJEjMGCFSEKj0feDhXSxK60h6bxee1UUZJlkrUDJzmFnGIxCv+7CSCjClC7krO2mJWi4yeai13slY9a1/xVzLj+tI9NGI3E+/lXQeGSM132LeJncKiUfbnIDrGHV6pzfdQJIIkPYoJMClOiEj4hePT/fEO08nnbICLLiLNSIsMcxIdvrKGcpKwGxJO4zzIn7jm4REboyh4L9GiHvzs+AnT4ZYx5mjCGl0ZZGB9+O8jFqglWGA2v/fjBr1sw0OwDjLw8nGHcoCr/UAohFQpP/VM453wID6gakkoXi5ySo4qBilsCxi6YvVgKHdW4ghM1PN20Fzbb5H5TZvt4KiKwCNmZmksjWPHicjIdrDNspicrWDB3FfwrdsXJ/+d2QINZWLhwHFUxqVyPaFkTrWwf6yX1DmkUVa2k8tQnl4NTm3xpPzg/YmidrF4GPBb0P/kZe6MMaEWGzCgJ5s2PAp7u5y+RRDQxRxm8fCvAL80Ef2JWZ52WXBzOp3CP3vjDIoQ84m7UtbMc2yCztm1hsSdCj802493ZVMzuCZASyKQoVZyZhVUJ72wdJefEYGdnJHXewmE3CTMhy/x4bH8PZ2LIFDobpXe5R3eyUg==","X-Forefront-Antispam-Report":"\n\tCIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700016)(1800799024)(56012099003)(18002099003);DIR:OUT;SFP:1101;","X-MS-Exchange-AntiSpam-MessageData-ChunkCount":"1","X-MS-Exchange-AntiSpam-MessageData-0":"\n\tqOCKMl8O+3ufmTspmopFpwvglJ18YM1NwyZH692HX2WLIlRhTJyD8ZNfQXQ0x7KKW0QJLem+GLL8fj59i1z9cC4Gvm+2yPeKIf4bZnxzlT2Z5/z/X1ezF5yOZRfvXI0OQJcmOmEztJpNX70RBjRya+0+V0PIWgv4LTmizEMlTa+M26gSstKo2j5yZQ5Rw+fhxlXy7K3IwQFGvuSub2+icROEqJ1wnsHTB5djBJApCG+aXoULZs2gMkTINBHTAZ6qO4sgoivkPQB0b2mc/vnkGjBJnbQ1EiJdjImNWQlb4uQSyXXCq5703FRfOTMECO+O/grDBtkg0aMXIOSsiJRAh15Twx12XczAVYEHgXwJ75fqx9eUVjQftk83cmRYslIOYmnbFRivvcDipMohynpeb6e2DZrsoWYwqiI/sa9F9OWramUpO4deasS9iHnhBu9J","X-OriginatorOrg":"Nvidia.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"29 Apr 2026 06:11:46.2586\n (UTC)","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 7fd09dc6-a60c-4df8-4761-08dea5b6314d","X-MS-Exchange-CrossTenant-Id":"43083d15-7273-40c1-b7db-39efd9ccc17a","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n\tSJ1PEPF00001CDD.namprd05.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"CY3PR12MB9554"},"content":"The tegra-mc platform driver does not register any dev_pm_ops, so the\nthe SoC-specific ->resume() is never invoked (e.g. tegra186_mc_resume)\non system wake. On Tegra186 and later this means MC client Stream-ID\noverride registers are not reprogrammed.\n\nRegister a dev_pm_ops on the tegra-mc driver and route the system\nresume callback into mc->soc->ops->resume() so the existing SID\nrestore path runs again on wake.\n\nThe MC interrupt mask registers also lose state across SC7, so\nre-apply them on resume. Factor the existing intmask programming\nout of tegra_mc_probe() into tegra_mc_setup_intmask() and reuse it\nfrom both probe and resume to avoid duplicating the loop.\n\nNo suspend callback is needed as the resume path reprograms all MC\nstate from the static SoC tables, so there is nothing to save.\n\nSigned-off-by: Ashish Mhetre \n---\n drivers/memory/tegra/mc.c | 46 +++++++++++++++++++++++++++++++++------\n 1 file changed, 39 insertions(+), 7 deletions(-)","diff":"diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c\nindex d620660da331..cddcefdd16c5 100644\n--- a/drivers/memory/tegra/mc.c\n+++ b/drivers/memory/tegra/mc.c\n@@ -13,6 +13,7 @@\n #include \n #include \n #include \n+#include \n #include \n #include \n #include \n@@ -910,6 +911,19 @@ static void tegra_mc_num_channel_enabled(struct tegra_mc *mc)\n \t}\n }\n \n+static void tegra_mc_setup_intmask(struct tegra_mc *mc)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < mc->soc->num_intmasks; i++) {\n+\t\tif (mc->soc->num_channels)\n+\t\t\tmc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmasks[i].mask,\n+\t\t\t\t mc->soc->intmasks[i].reg);\n+\t\telse\n+\t\t\tmc_writel(mc, mc->soc->intmasks[i].mask, mc->soc->intmasks[i].reg);\n+\t}\n+}\n+\n static int tegra_mc_probe(struct platform_device *pdev)\n {\n \tstruct tegra_mc *mc;\n@@ -970,13 +984,7 @@ static int tegra_mc_probe(struct platform_device *pdev)\n \t\t\t}\n \t\t}\n \n-\t\tfor (i = 0; i < mc->soc->num_intmasks; i++) {\n-\t\t\tif (mc->soc->num_channels)\n-\t\t\t\tmc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmasks[i].mask,\n-\t\t\t\t\t mc->soc->intmasks[i].reg);\n-\t\t\telse\n-\t\t\t\tmc_writel(mc, mc->soc->intmasks[i].mask, mc->soc->intmasks[i].reg);\n-\t\t}\n+\t\ttegra_mc_setup_intmask(mc);\n \t}\n \n \tif (mc->soc->reset_ops) {\n@@ -1010,10 +1018,34 @@ static void tegra_mc_sync_state(struct device *dev)\n \t\ticc_sync_state(dev);\n }\n \n+static int tegra_mc_resume(struct device *dev)\n+{\n+\tstruct tegra_mc *mc = dev_get_drvdata(dev);\n+\tint err;\n+\n+\tif (mc->soc->ops && mc->soc->ops->resume) {\n+\t\terr = mc->soc->ops->resume(mc);\n+\t\tif (err)\n+\t\t\treturn err;\n+\t}\n+\n+\ttegra_mc_setup_intmask(mc);\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * No suspend callback is needed because the resume path reinitializes all\n+ * necessary MC register state (SID overrides, interrupt masks) from static\n+ * SoC data tables rather than from saved runtime state.\n+ */\n+static DEFINE_SIMPLE_DEV_PM_OPS(tegra_mc_pm_ops, NULL, tegra_mc_resume);\n+\n static struct platform_driver tegra_mc_driver = {\n \t.driver = {\n \t\t.name = \"tegra-mc\",\n \t\t.of_match_table = tegra_mc_of_match,\n+\t\t.pm = pm_sleep_ptr(&tegra_mc_pm_ops),\n \t\t.suppress_bind_attrs = true,\n \t\t.sync_state = tegra_mc_sync_state,\n \t},\n","prefixes":[]}