{"id":2230036,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230036/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-34-alistair.francis@wdc.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260429044752.4176397-34-alistair.francis@wdc.com>","date":"2026-04-29T04:47:34","name":"[PULL,33/51] target/riscv: Introduce BF16 canonical NaN for Zvfbfa extension","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f7276d7e94701d8446f21cf81b46b7219cdd68d5","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/1.1/people/64571/?format=json","name":"Alistair Francis","email":"alistair23@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-34-alistair.francis@wdc.com/mbox/","series":[{"id":501983,"url":"http://patchwork.ozlabs.org/api/1.1/series/501983/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501983","date":"2026-04-29T04:47:05","name":"[PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI","version":1,"mbox":"http://patchwork.ozlabs.org/series/501983/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230036/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230036/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=sxxW0sFc;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pl1-x62c.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Max Chou \n\nAccording to the Zvfbfa ISA spec (v0.1), improperly NaN-boxed\nf-register operands must substitute the BF16 canonical NaN instead of\nthe FP16 canonical NaN for some vector floating-point instructions.\n\nReviewed-by: Daniel Henrique Barboza \nReviewed-by: Chao Liu \nReviewed-by: Alistair Francis \nSigned-off-by: Max Chou \nMessage-ID: <20260402125234.1371897-8-max.chou@sifive.com>\nSigned-off-by: Alistair Francis \n---\n target/riscv/translate.c | 8 ++++++++\n target/riscv/insn_trans/trans_rvv.c.inc | 18 +++++++++---------\n 2 files changed, 17 insertions(+), 9 deletions(-)","diff":"diff --git a/target/riscv/translate.c b/target/riscv/translate.c\nindex f8ccf34438..1e4f340256 100644\n--- a/target/riscv/translate.c\n+++ b/target/riscv/translate.c\n@@ -214,6 +214,14 @@ static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in)\n tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);\n }\n \n+static void gen_check_nanbox_h_bf16(TCGv_i64 out, TCGv_i64 in)\n+{\n+ TCGv_i64 t_max = tcg_constant_i64(0xffffffffffff0000ull);\n+ TCGv_i64 t_nan = tcg_constant_i64(0xffffffffffff7fc0ull);\n+\n+ tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);\n+}\n+\n static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)\n {\n TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull);\ndiff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc\nindex 4df9a40b44..03ae85796a 100644\n--- a/target/riscv/insn_trans/trans_rvv.c.inc\n+++ b/target/riscv/insn_trans/trans_rvv.c.inc\n@@ -2319,17 +2319,17 @@ GEN_OPIWI_NARROW_TRANS(vnclip_wi, IMM_ZX, vnclip_wx)\n */\n static void do_nanbox(DisasContext *s, TCGv_i64 out, TCGv_i64 in)\n {\n- switch (s->sew) {\n- case 1:\n- gen_check_nanbox_h(out, in);\n- break;\n- case 2:\n+ if (s->sew == MO_16) {\n+ if (s->altfmt) {\n+ gen_check_nanbox_h_bf16(out, in);\n+ } else {\n+ gen_check_nanbox_h(out, in);\n+ }\n+ } else if (s->sew == MO_32) {\n gen_check_nanbox_s(out, in);\n- break;\n- case 3:\n+ } else if (s->sew == MO_64) {\n tcg_gen_mov_i64(out, in);\n- break;\n- default:\n+ } else {\n g_assert_not_reached();\n }\n }\n","prefixes":["PULL","33/51"]}