{"id":2230035,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230035/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-18-alistair.francis@wdc.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260429044752.4176397-18-alistair.francis@wdc.com>","date":"2026-04-29T04:47:18","name":"[PULL,17/51] target/riscv: Replace MO_TE -> MO_LE","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"b5a5f4ccc13fb085a79cd05e9ba632074d5bf230","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/1.1/people/64571/?format=json","name":"Alistair Francis","email":"alistair23@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-18-alistair.francis@wdc.com/mbox/","series":[{"id":501983,"url":"http://patchwork.ozlabs.org/api/1.1/series/501983/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501983","date":"2026-04-29T04:47:05","name":"[PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI","version":1,"mbox":"http://patchwork.ozlabs.org/series/501983/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230035/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230035/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=jB6tx6oE;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::1035;\n envelope-from=alistair23@gmail.com; helo=mail-pj1-x1035.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Philippe Mathieu-Daudé \n\nWe only build the RISC-V target using little endianness order,\ntherefore the MO_TE definitions expand to the little endian\none. Use the latter which is more explicit.\n\nMechanical change running:\n\n $ sed -i -e s/MO_TE/MO_LE/ \\\n $(git grep -wl MO_TE target/riscv/)\n\nSigned-off-by: Philippe Mathieu-Daudé \nReviewed-by: Alistair Francis \nMessage-ID: <20260318103122.97244-15-philmd@linaro.org>\nSigned-off-by: Alistair Francis \n---\n target/riscv/internals.h | 2 +-\n target/riscv/translate.c | 2 +-\n 2 files changed, 2 insertions(+), 2 deletions(-)","diff":"diff --git a/target/riscv/internals.h b/target/riscv/internals.h\nindex 860c47732b..460346dd6d 100644\n--- a/target/riscv/internals.h\n+++ b/target/riscv/internals.h\n@@ -71,7 +71,7 @@ static inline MemOp mo_endian_env(CPURISCVState *env)\n * - MSTATUS_MBE (Machine-mode)\n * but we don't implement that yet.\n */\n- return MO_TE;\n+ return MO_LE;\n }\n \n /* share data between vector helpers and decode code */\ndiff --git a/target/riscv/translate.c b/target/riscv/translate.c\nindex 711080f3fd..1a25c517a2 100644\n--- a/target/riscv/translate.c\n+++ b/target/riscv/translate.c\n@@ -135,7 +135,7 @@ static inline MemOp mo_endian(DisasContext *ctx)\n * - MSTATUS_MBE (Machine-mode)\n * but we don't implement that yet.\n */\n- return MO_TE;\n+ return MO_LE;\n }\n \n #ifdef TARGET_RISCV32\n","prefixes":["PULL","17/51"]}