{"id":2230031,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230031/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-51-alistair.francis@wdc.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260429044752.4176397-51-alistair.francis@wdc.com>","date":"2026-04-29T04:47:51","name":"[PULL,50/51] target/riscv: Fix pointer masking translation mode check bug","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"2a8a6f003dc2ebd428fcb52245960877b0e2133d","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/1.1/people/64571/?format=json","name":"Alistair Francis","email":"alistair23@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-51-alistair.francis@wdc.com/mbox/","series":[{"id":501983,"url":"http://patchwork.ozlabs.org/api/1.1/series/501983/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501983","date":"2026-04-29T04:47:05","name":"[PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI","version":1,"mbox":"http://patchwork.ozlabs.org/series/501983/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230031/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230031/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=c56JDI28;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::635;\n envelope-from=alistair23@gmail.com; helo=mail-pl1-x635.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Frank Chang \n\nWhen running with virtualization in VS/VU mode, or when executing the\nvirtual-machine load/store instructions (HLV.* and HSV.*), the type of\naddress that determines which pointer masking rules apply should be\nchecked against vsatp rather than satp.\n\nAs a result, sign extension also applies to the virtual-machine\nload/store instructions.\n\nSigned-off-by: Frank Chang \nReviewed-by: Radim Krčmář \nReviewed-by: Alistair Francis \nMessage-ID: <20260421093715.2995067-7-frank.chang@sifive.com>\nSigned-off-by: Alistair Francis \n---\n target/riscv/cpu.h | 2 +-\n target/riscv/internals.h | 4 +---\n target/riscv/cpu_helper.c | 19 +++++++++++++++----\n target/riscv/tcg/tcg-cpu.c | 4 ++--\n 4 files changed, 19 insertions(+), 10 deletions(-)","diff":"diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\nindex 138183e017..81c41e3429 100644\n--- a/target/riscv/cpu.h\n+++ b/target/riscv/cpu.h\n@@ -888,7 +888,7 @@ static inline uint32_t vext_get_vlmax(uint32_t vlenb, uint32_t vsew,\n \n bool riscv_cpu_is_32bit(RISCVCPU *cpu);\n \n-bool riscv_cpu_virt_mem_enabled(CPURISCVState *env);\n+bool riscv_cpu_virt_mem_enabled(CPURISCVState *env, bool is_vm_ldst);\n RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env);\n RISCVPmPmm riscv_pm_get_vm_ldst_pmm(CPURISCVState *env);\n uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm);\ndiff --git a/target/riscv/internals.h b/target/riscv/internals.h\nindex 7eb6edbe90..bac6c8032a 100644\n--- a/target/riscv/internals.h\n+++ b/target/riscv/internals.h\n@@ -219,9 +219,7 @@ static inline target_ulong adjust_addr_body(CPURISCVState *env,\n return addr;\n }\n \n- if (!is_virt_addr) {\n- signext = riscv_cpu_virt_mem_enabled(env);\n- }\n+ signext = riscv_cpu_virt_mem_enabled(env, is_virt_addr);\n pmlen = riscv_pm_get_pmlen(pmm);\n addr = addr << pmlen;\n \ndiff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c\nindex ef1ff7cb0b..39c3486ae0 100644\n--- a/target/riscv/cpu_helper.c\n+++ b/target/riscv/cpu_helper.c\n@@ -240,16 +240,27 @@ RISCVPmPmm riscv_pm_get_vm_ldst_pmm(CPURISCVState *env)\n #endif\n }\n \n-bool riscv_cpu_virt_mem_enabled(CPURISCVState *env)\n+bool riscv_cpu_virt_mem_enabled(CPURISCVState *env, bool is_vm_ldst)\n {\n #ifndef CONFIG_USER_ONLY\n int satp_mode = 0;\n- int priv_mode = cpu_address_mode(env);\n+ uint64_t satp;\n+ int priv_mode;\n+ bool virt = false;\n+\n+ if (!is_vm_ldst) {\n+ riscv_cpu_eff_priv(env, &priv_mode, &virt);\n+ } else {\n+ priv_mode = get_field(env->hstatus, HSTATUS_SPVP);\n+ virt = true;\n+ }\n+\n+ satp = virt ? env->vsatp : env->satp;\n \n if (riscv_cpu_mxl(env) == MXL_RV32) {\n- satp_mode = get_field(env->satp, SATP32_MODE);\n+ satp_mode = get_field(satp, SATP32_MODE);\n } else {\n- satp_mode = get_field(env->satp, SATP64_MODE);\n+ satp_mode = get_field(satp, SATP64_MODE);\n }\n \n return ((satp_mode != VM_1_10_MBARE) && (priv_mode != PRV_M));\ndiff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\nindex f3f7808895..02c98cc2db 100644\n--- a/target/riscv/tcg/tcg-cpu.c\n+++ b/target/riscv/tcg/tcg-cpu.c\n@@ -105,7 +105,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)\n RISCVExtStatus fs, vs;\n uint32_t flags = 0;\n uint64_t ext_flags = 0;\n- bool pm_signext = riscv_cpu_virt_mem_enabled(env);\n+ bool pm_signext = riscv_cpu_virt_mem_enabled(env, false);\n \n if (cpu->cfg.ext_zve32x) {\n /*\n@@ -260,7 +260,7 @@ static vaddr riscv_pointer_wrap(CPUState *cs, int mmu_idx,\n return result;\n }\n \n- pm_signext = riscv_cpu_virt_mem_enabled(env);\n+ pm_signext = riscv_cpu_virt_mem_enabled(env, false);\n if (pm_signext) {\n return sextract64(result, 0, 64 - pm_len);\n }\n","prefixes":["PULL","50/51"]}