{"id":2230027,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230027/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-52-alistair.francis@wdc.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260429044752.4176397-52-alistair.francis@wdc.com>","date":"2026-04-29T04:47:52","name":"[PULL,51/51] target/riscv: rvv: Handle mask/source overlap of vector reduction instructions","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"8da7e218d90d1fbfa6ca6d9f95d47e8010273e95","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/1.1/people/64571/?format=json","name":"Alistair Francis","email":"alistair23@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-52-alistair.francis@wdc.com/mbox/","series":[{"id":501983,"url":"http://patchwork.ozlabs.org/api/1.1/series/501983/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501983","date":"2026-04-29T04:47:05","name":"[PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI","version":1,"mbox":"http://patchwork.ozlabs.org/series/501983/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230027/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230027/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=R7aG7bGt;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pl1-x631.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Anton Blanchard \n\nMasked vector reduction instructions must not use v0 as a source register.\nCheck rs1 and rs2 against the mask register when vm=0.\n\nSigned-off-by: Anton Blanchard \nReviewed-by: Daniel Henrique Barboza \nMessage-ID: <20260417120626.77415-1-antonb@tenstorrent.com>\nSigned-off-by: Alistair Francis \n---\n target/riscv/insn_trans/trans_rvv.c.inc | 2 ++\n 1 file changed, 2 insertions(+)","diff":"diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc\nindex 5b72926b3c..e65356eb7c 100644\n--- a/target/riscv/insn_trans/trans_rvv.c.inc\n+++ b/target/riscv/insn_trans/trans_rvv.c.inc\n@@ -3265,6 +3265,8 @@ static bool reduction_check(DisasContext *s, arg_rmrr *a)\n {\n return require_rvv(s) &&\n vext_check_isa_ill(s) &&\n+ require_vm(a->vm, a->rs1) &&\n+ require_vm(a->vm, a->rs2) &&\n vext_check_reduction(s, a->rs2);\n }\n \n","prefixes":["PULL","51/51"]}