{"id":2230025,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230025/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-27-alistair.francis@wdc.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260429044752.4176397-27-alistair.francis@wdc.com>","date":"2026-04-29T04:47:27","name":"[PULL,26/51] target/riscv: preserve RV32 henvcfgh on henvcfg writes","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"b7ab9ecb9287179db25e7d2137254880e850daf0","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/1.1/people/64571/?format=json","name":"Alistair Francis","email":"alistair23@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-27-alistair.francis@wdc.com/mbox/","series":[{"id":501983,"url":"http://patchwork.ozlabs.org/api/1.1/series/501983/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501983","date":"2026-04-29T04:47:05","name":"[PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI","version":1,"mbox":"http://patchwork.ozlabs.org/series/501983/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230025/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230025/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=Bb22FATZ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pl1-x636.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Bruno Sa \n\nOn RV32, STCE/ADUE/PBMTE/DTE are implemented in henvcfgh. A write to\nhenvcfg should therefore only update the low 32 bits of env->henvcfg.\n\nThe current write_henvcfg() path overwrites env->henvcfg with the\nlow-half value and clears any bits previously written via henvcfgh.\n\nPreserve the upper 32 bits on RV32 henvcfg writes and keep the existing\nRV64 behaviour unchanged.\n\nSigned-off-by: Bruno Sa \nReviewed-by: Alistair Francis \nMessage-ID: <20260409155344.2849233-2-bruno.vilaca.sa@gmail.com>\nSigned-off-by: Alistair Francis \n---\n target/riscv/csr.c | 10 +++++++++-\n 1 file changed, 9 insertions(+), 1 deletion(-)","diff":"diff --git a/target/riscv/csr.c b/target/riscv/csr.c\nindex a75281539b..cfd076b368 100644\n--- a/target/riscv/csr.c\n+++ b/target/riscv/csr.c\n@@ -3353,7 +3353,15 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,\n }\n }\n \n- env->henvcfg = val & mask;\n+ if (riscv_cpu_mxl(env) == MXL_RV32) {\n+ /*\n+ * RV32 stores STCE/ADUE/PBMTE/DTE in henvcfgh, so a low-half henvcfg\n+ * write must not clobber the upper 32 bits.\n+ */\n+ env->henvcfg = (env->henvcfg & ~0xFFFFFFFFULL) | (val & mask);\n+ } else {\n+ env->henvcfg = val & mask;\n+ }\n if ((env->henvcfg & HENVCFG_DTE) == 0) {\n env->vsstatus &= ~MSTATUS_SDT;\n }\n","prefixes":["PULL","26/51"]}