{"id":2230024,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230024/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-15-alistair.francis@wdc.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260429044752.4176397-15-alistair.francis@wdc.com>","date":"2026-04-29T04:47:15","name":"[PULL,14/51] target/riscv: Replace MO_TE by mo_endian (MIPS extension)","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"3776e5eea55ca5dc70a8602627c6fd8fd9f453ee","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/1.1/people/64571/?format=json","name":"Alistair Francis","email":"alistair23@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-15-alistair.francis@wdc.com/mbox/","series":[{"id":501983,"url":"http://patchwork.ozlabs.org/api/1.1/series/501983/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501983","date":"2026-04-29T04:47:05","name":"[PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI","version":1,"mbox":"http://patchwork.ozlabs.org/series/501983/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230024/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230024/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=nIbJ2a3p;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::636;\n envelope-from=alistair23@gmail.com; helo=mail-pl1-x636.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Philippe Mathieu-Daudé \n\nReplace compile-time MO_TE evaluation by runtime mo_endian()\none, which expand target endianness from DisasContext.\n\nSigned-off-by: Philippe Mathieu-Daudé \nReviewed-by: Alistair Francis \nMessage-ID: <20260318103122.97244-12-philmd@linaro.org>\nSigned-off-by: Alistair Francis \n---\n target/riscv/insn_trans/trans_xmips.c.inc | 24 +++++++++++++++--------\n 1 file changed, 16 insertions(+), 8 deletions(-)","diff":"diff --git a/target/riscv/insn_trans/trans_xmips.c.inc b/target/riscv/insn_trans/trans_xmips.c.inc\nindex 37572563ae..c1a30156d3 100644\n--- a/target/riscv/insn_trans/trans_xmips.c.inc\n+++ b/target/riscv/insn_trans/trans_xmips.c.inc\n@@ -47,6 +47,8 @@ static bool trans_ccmov(DisasContext *ctx, arg_ccmov *a)\n /* Load Doubleword Pair. */\n static bool trans_ldp(DisasContext *ctx, arg_ldp *a)\n {\n+ MemOp memop = MO_SQ | mo_endian(ctx);\n+\n REQUIRE_XMIPSLSP(ctx);\n REQUIRE_64_OR_128BIT(ctx);\n \n@@ -56,11 +58,11 @@ static bool trans_ldp(DisasContext *ctx, arg_ldp *a)\n TCGv addr = tcg_temp_new();\n \n tcg_gen_addi_tl(addr, src, a->imm_y);\n- tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TE | MO_SQ);\n+ tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, memop);\n gen_set_gpr(ctx, a->rd, dest0);\n \n tcg_gen_addi_tl(addr, addr, 8);\n- tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TE | MO_SQ);\n+ tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, memop);\n gen_set_gpr(ctx, a->rs3, dest1);\n \n return true;\n@@ -69,6 +71,8 @@ static bool trans_ldp(DisasContext *ctx, arg_ldp *a)\n /* Load Word Pair. */\n static bool trans_lwp(DisasContext *ctx, arg_lwp *a)\n {\n+ MemOp memop = MO_SL | mo_endian(ctx);\n+\n REQUIRE_XMIPSLSP(ctx);\n \n TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);\n@@ -77,11 +81,11 @@ static bool trans_lwp(DisasContext *ctx, arg_lwp *a)\n TCGv addr = tcg_temp_new();\n \n tcg_gen_addi_tl(addr, src, a->imm_x);\n- tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TE | MO_SL);\n+ tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, memop);\n gen_set_gpr(ctx, a->rd, dest0);\n \n tcg_gen_addi_tl(addr, addr, 4);\n- tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TE | MO_SL);\n+ tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, memop);\n gen_set_gpr(ctx, a->rs3, dest1);\n \n return true;\n@@ -90,6 +94,8 @@ static bool trans_lwp(DisasContext *ctx, arg_lwp *a)\n /* Store Doubleword Pair. */\n static bool trans_sdp(DisasContext *ctx, arg_sdp *a)\n {\n+ MemOp memop = MO_UQ | mo_endian(ctx);\n+\n REQUIRE_XMIPSLSP(ctx);\n REQUIRE_64_OR_128BIT(ctx);\n \n@@ -99,10 +105,10 @@ static bool trans_sdp(DisasContext *ctx, arg_sdp *a)\n TCGv addr = tcg_temp_new();\n \n tcg_gen_addi_tl(addr, src, a->imm_w);\n- tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TE | MO_UQ);\n+ tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, memop);\n \n tcg_gen_addi_tl(addr, addr, 8);\n- tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TE | MO_UQ);\n+ tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, memop);\n \n return true;\n }\n@@ -110,6 +116,8 @@ static bool trans_sdp(DisasContext *ctx, arg_sdp *a)\n /* Store Word Pair. */\n static bool trans_swp(DisasContext *ctx, arg_swp *a)\n {\n+ MemOp memop = MO_SL | mo_endian(ctx);\n+\n REQUIRE_XMIPSLSP(ctx);\n \n TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);\n@@ -118,10 +126,10 @@ static bool trans_swp(DisasContext *ctx, arg_swp *a)\n TCGv addr = tcg_temp_new();\n \n tcg_gen_addi_tl(addr, src, a->imm_v);\n- tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TE | MO_SL);\n+ tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, memop);\n \n tcg_gen_addi_tl(addr, addr, 4);\n- tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TE | MO_SL);\n+ tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, memop);\n \n return true;\n }\n","prefixes":["PULL","14/51"]}