{"id":2230019,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230019/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-32-alistair.francis@wdc.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260429044752.4176397-32-alistair.francis@wdc.com>","date":"2026-04-29T04:47:32","name":"[PULL,31/51] target/riscv: Use the tb->cs_base as the extend tb flags","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"4b2c826db2b2ea6cc93a4e09a01f41151f085b82","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/1.1/people/64571/?format=json","name":"Alistair Francis","email":"alistair23@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-32-alistair.francis@wdc.com/mbox/","series":[{"id":501983,"url":"http://patchwork.ozlabs.org/api/1.1/series/501983/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501983","date":"2026-04-29T04:47:05","name":"[PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI","version":1,"mbox":"http://patchwork.ozlabs.org/series/501983/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230019/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230019/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=R/EqJdLM;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pl1-x62b.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Max Chou \n\nWe have more than 32-bits worth of state per TB, so use the\ntb->cs_base, which is otherwise unused for RISC-V, as the extend flag.\n\nReviewed-by: Daniel Henrique Barboza \nReviewed-by: Chao Liu \nSigned-off-by: Max Chou \nMessage-ID: <20260402125234.1371897-6-max.chou@sifive.com>\nSigned-off-by: Alistair Francis \n---\n include/exec/translation-block.h | 1 +\n target/riscv/cpu.h | 3 +++\n target/riscv/tcg/tcg-cpu.c | 7 ++++++-\n 3 files changed, 10 insertions(+), 1 deletion(-)","diff":"diff --git a/include/exec/translation-block.h b/include/exec/translation-block.h\nindex 4f83d5bec9..40cc699031 100644\n--- a/include/exec/translation-block.h\n+++ b/include/exec/translation-block.h\n@@ -65,6 +65,7 @@ struct TranslationBlock {\n * arm: an extension of tb->flags,\n * s390x: instruction data for EXECUTE,\n * sparc: the next pc of the instruction queue (for delay slots).\n+ * riscv: an extension of tb->flags,\n */\n uint64_t cs_base;\n \ndiff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\nindex 962cc45073..4c0676ed53 100644\n--- a/target/riscv/cpu.h\n+++ b/target/riscv/cpu.h\n@@ -703,6 +703,9 @@ FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1)\n FIELD(TB_FLAGS, PM_PMM, 29, 2)\n FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1)\n \n+FIELD(EXT_TB_FLAGS, MISA_EXT, 0, 32)\n+FIELD(EXT_TB_FLAGS, ALTFMT, 32, 1)\n+\n #ifdef TARGET_RISCV32\n #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)\n #else\ndiff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\nindex c4f7da7193..f3f7808895 100644\n--- a/target/riscv/tcg/tcg-cpu.c\n+++ b/target/riscv/tcg/tcg-cpu.c\n@@ -104,6 +104,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)\n RISCVCPU *cpu = env_archcpu(env);\n RISCVExtStatus fs, vs;\n uint32_t flags = 0;\n+ uint64_t ext_flags = 0;\n bool pm_signext = riscv_cpu_virt_mem_enabled(env);\n \n if (cpu->cfg.ext_zve32x) {\n@@ -118,6 +119,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)\n \n /* lmul encoded as in DisasContext::lmul */\n int8_t lmul = sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0, 3);\n+ uint8_t altfmt = FIELD_EX64(env->vtype, VTYPE, ALTFMT);\n uint32_t vsew = FIELD_EX64(env->vtype, VTYPE, VSEW);\n uint32_t vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul);\n uint32_t maxsz = vlmax << vsew;\n@@ -133,6 +135,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)\n flags = FIELD_DP32(flags, TB_FLAGS, VMA,\n FIELD_EX64(env->vtype, VTYPE, VMA));\n flags = FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart == 0);\n+ ext_flags = FIELD_DP64(ext_flags, EXT_TB_FLAGS, ALTFMT, altfmt);\n } else {\n flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);\n }\n@@ -189,10 +192,12 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *cs)\n flags = FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env));\n flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext);\n \n+ ext_flags = FIELD_DP64(ext_flags, EXT_TB_FLAGS, MISA_EXT, env->misa_ext);\n+\n return (TCGTBCPUState){\n .pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc,\n .flags = flags,\n- .cs_base = env->misa_ext,\n+ .cs_base = ext_flags,\n };\n }\n \n","prefixes":["PULL","31/51"]}