{"id":2230017,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230017/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-38-alistair.francis@wdc.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260429044752.4176397-38-alistair.francis@wdc.com>","date":"2026-04-29T04:47:38","name":"[PULL,37/51] target/riscv: tt-ascalon: Add Tenstorrent mvendorid","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"8ab04a5782c36cab4e7a8fe95a7d2411f736174a","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/1.1/people/64571/?format=json","name":"Alistair Francis","email":"alistair23@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-38-alistair.francis@wdc.com/mbox/","series":[{"id":501983,"url":"http://patchwork.ozlabs.org/api/1.1/series/501983/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501983","date":"2026-04-29T04:47:05","name":"[PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI","version":1,"mbox":"http://patchwork.ozlabs.org/series/501983/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230017/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230017/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=eu0bVTnI;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pl1-x631.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Joel Stanley \n\nJEP106 has two vendor IDs for Tenstorrent. We will use Bank 16, company 33:\n\n ((16 - 1) << 7) | 33 = 0x7a1\n\nAs JEP106 requires registration to download, the number can confirmed by\nlooking at the OpenOCD sources[1].\n\nAlternatively, referring to the JEDEC document the hex IDs are listed with the\nparity (MSB) bit added. Company 33 has hex 0xa1:\n\n ((16 - 1) << 7) | (0xa1 & ~0x80) = 0x7a1\n\nAdd it to the Ascalon CPU definition as the mvendorid CSR.\n\n[1] https://github.com/openocd-org/openocd/blob/1ebff3ab33c77e3f8fb4e1ddda262b606b572af1/src/helper/jep106.inc#L1935\n\nSigned-off-by: Joel Stanley \nReviewed-by: Daniel Henrique Barboza \nReviewed-by: Michael Ellerman \nMessage-ID: <20260114020516.982305-1-joel@jms.id.au>\nSigned-off-by: Alistair Francis \n---\n target/riscv/cpu_vendorid.h | 2 ++\n target/riscv/cpu.c | 2 ++\n 2 files changed, 4 insertions(+)","diff":"diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h\nindex f1ffc66542..751a13aace 100644\n--- a/target/riscv/cpu_vendorid.h\n+++ b/target/riscv/cpu_vendorid.h\n@@ -8,4 +8,6 @@\n #define VEYRON_V1_MIMPID 0x111\n #define VEYRON_V1_MVENDORID 0x61f\n \n+#define TENSTORRENT_VENDOR_ID 0x7a1\n+\n #endif /* TARGET_RISCV_CPU_VENDORID_H */\ndiff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex 38286b6b40..72c6f4f0f1 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -3207,6 +3207,8 @@ static const TypeInfo riscv_cpu_type_infos[] = {\n .cfg.ext_svnapot = true,\n .cfg.ext_svpbmt = true,\n \n+ .cfg.mvendorid = TENSTORRENT_VENDOR_ID,\n+\n .cfg.max_satp_mode = VM_1_10_SV57,\n ),\n \n","prefixes":["PULL","37/51"]}