{"id":2230015,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230015/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-47-alistair.francis@wdc.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260429044752.4176397-47-alistair.francis@wdc.com>","date":"2026-04-29T04:47:47","name":"[PULL,46/51] target/riscv: Add a helper to return the current effective priv mode","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"2b5dd71440da5634de81fc770fd2d3317da740ca","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/1.1/people/64571/?format=json","name":"Alistair Francis","email":"alistair23@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-47-alistair.francis@wdc.com/mbox/","series":[{"id":501983,"url":"http://patchwork.ozlabs.org/api/1.1/series/501983/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501983","date":"2026-04-29T04:47:05","name":"[PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI","version":1,"mbox":"http://patchwork.ozlabs.org/series/501983/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230015/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230015/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=Jnmftx9s;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pl1-x62d.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Frank Chang \n\nThis helper returns the current effective privilege mode.\n\nSigned-off-by: Frank Chang \nReviewed-by: Alistair Francis \nMessage-ID: <20260421093715.2995067-3-frank.chang@sifive.com>\nSigned-off-by: Alistair Francis \n---\n target/riscv/cpu.h | 37 +++++++++++++++++++++++++++++++++++++\n target/riscv/cpu_helper.c | 15 +++++----------\n 2 files changed, 42 insertions(+), 10 deletions(-)","diff":"diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\nindex 4c0676ed53..672f0dab0f 100644\n--- a/target/riscv/cpu.h\n+++ b/target/riscv/cpu.h\n@@ -806,6 +806,43 @@ static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)\n }\n #endif\n \n+/*\n+ * Returns the current effective privilege mode.\n+ *\n+ * @env: CPURISCVState\n+ * @priv: The returned effective privilege mode.\n+ * @virt: The returned effective virtualization mode.\n+ *\n+ * Returns true if the effective privilege mode is modified.\n+ */\n+static inline QEMU_ALWAYS_INLINE\n+bool riscv_cpu_eff_priv(CPURISCVState *env, int *priv, bool *virt)\n+{\n+ int mode = env->priv;\n+ bool virt_enabled = false;\n+ bool mode_modified = false;\n+\n+#ifndef CONFIG_USER_ONLY\n+ if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) {\n+ mode = get_field(env->mstatus, MSTATUS_MPP);\n+ virt_enabled = get_field(env->mstatus, MSTATUS_MPV) && (mode != PRV_M);\n+ mode_modified = true;\n+ } else {\n+ virt_enabled = env->virt_enabled;\n+ }\n+#endif\n+\n+ if (priv) {\n+ *priv = mode;\n+ }\n+\n+ if (virt) {\n+ *virt = virt_enabled;\n+ }\n+\n+ return mode_modified;\n+}\n+\n static inline bool riscv_cpu_allow_16bit_insn(const RISCVCPUConfig *cfg,\n target_long priv_ver,\n uint32_t misa_ext)\ndiff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c\nindex 659150c646..513bad21af 100644\n--- a/target/riscv/cpu_helper.c\n+++ b/target/riscv/cpu_helper.c\n@@ -45,19 +45,14 @@ int riscv_env_mmu_index(CPURISCVState *env, bool ifetch)\n #else\n bool virt = env->virt_enabled;\n int mode = env->priv;\n+ bool mode_modified = false;\n \n /* All priv -> mmu_idx mapping are here */\n if (!ifetch) {\n- uint64_t status = env->mstatus;\n-\n- if (mode == PRV_M && get_field(status, MSTATUS_MPRV)) {\n- mode = get_field(env->mstatus, MSTATUS_MPP);\n- virt = get_field(env->mstatus, MSTATUS_MPV) &&\n- (mode != PRV_M);\n- if (virt) {\n- status = env->vsstatus;\n- }\n- }\n+ mode_modified = riscv_cpu_eff_priv(env, &mode, &virt);\n+ uint64_t status = (mode_modified && virt) ? env->vsstatus :\n+ env->mstatus;\n+\n if (mode == PRV_S && get_field(status, MSTATUS_SUM)) {\n mode = MMUIdx_S_SUM;\n }\n","prefixes":["PULL","46/51"]}