{"id":2230002,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2230002/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-30-alistair.francis@wdc.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260429044752.4176397-30-alistair.francis@wdc.com>","date":"2026-04-29T04:47:30","name":"[PULL,29/51] target/riscv: rvv: Add new VTYPE CSR field - altfmt","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"978eb505bd9c7e26a8bd5453057100afab1f65de","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/1.1/people/64571/?format=json","name":"Alistair Francis","email":"alistair23@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-30-alistair.francis@wdc.com/mbox/","series":[{"id":501983,"url":"http://patchwork.ozlabs.org/api/1.1/series/501983/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501983","date":"2026-04-29T04:47:05","name":"[PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI","version":1,"mbox":"http://patchwork.ozlabs.org/series/501983/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2230002/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2230002/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=ewBP4u3e;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g54dl6W05z1xqf\n\tfor ; Wed, 29 Apr 2026 14:51:39 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wHwsk-0006fY-Fl; Wed, 29 Apr 2026 00:50:42 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wHwsi-0006WB-Fk\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 00:50:40 -0400","from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wHwsg-0000kx-CQ\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 00:50:40 -0400","by mail-pl1-x632.google.com with SMTP id\n d9443c01a7336-2ab232cc803so58614945ad.3\n for ; Tue, 28 Apr 2026 21:50:37 -0700 (PDT)","from toolbx.alistair23.me ([2403:581e:fdf9:0:6209:4521:6813:45b7])\n by smtp.gmail.com with ESMTPSA id\n d9443c01a7336-2b988772ae8sm7756145ad.7.2026.04.28.21.50.32\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Tue, 28 Apr 2026 21:50:36 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=gmail.com; s=20251104; t=1777438237; x=1778043037; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=fIZU8Gh7QJtlybesDgHA1mbz+UBZEFTfXaC0E836a7M=;\n b=ewBP4u3eD7/7QnlIV6VroJIcbezjiMMwWjr5HT+XeFEGFQ7AmLWlTSc4EKdevHl0/3\n f8uCUuDDETGFEG9W4NToU4oEfKRqFBFF2pCjBXqrFmRNT/Rfk4dUk3iZD6wYolzTomlN\n q5zwxF4ruUO2QNLXZhUEEnar5A8tXPgi/fY1431vNS92QjsOiJNaW6GS71ueIiDt90DM\n 6nMdNwy7NG2MQN3rUJh+yxIMUAMHBKxtVDPYGemt2yi/1byEPhpk/mw1eS4pvaznfL/P\n QSOhgDXbO/RFv6MWT2tlwzsapHfZB2XSsm8nUEQepaz+VTqWmhpKlyOeFco1J6vP6VMZ\n bfzw==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1777438237; x=1778043037;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=fIZU8Gh7QJtlybesDgHA1mbz+UBZEFTfXaC0E836a7M=;\n b=LmWUMrQ89w9so1rkVj2YtkfF0Gg41nkbQlXqkyobgXAuzLNUukU2JwQflYprawXtdc\n U2gDk9tKEnw3DT3pYdVdtVs+tFVFf69vfR93xJihqLiM3GLsZf+lhXn7KqkjEJs59vvD\n 9Ph+pzK9eDEulD8qfBFh2eixPjcGJV2ZxyorXjzdhCtRuaaPtgpiNplDLPbjso6zM84K\n 23HCt7quPoo5vGLx0U6Mgl7v85vNcUbpPiZLy5V2+67qZtszk6SHo4RrpcdR9keoBkcY\n NLrUq2mkMYcut1XVRYKUvaVKDRcJpz7Tlo8N3tahNXT15Y7z++Ea+o1PJKQlUyEoUTRw\n jQZw==","X-Forwarded-Encrypted":"i=1;\n AFNElJ84PjIRzriRe79At58clIF4Ap9+DI2mGBc8vyGEfHQJByTJGZc73vPBopWHYlmhId8mszpmlW54hNIx@nongnu.org","X-Gm-Message-State":"AOJu0YxX2h2zk3yOcEuKe2S/UDbdAbU+C5GHZ3TZQWpEkDqjLMB0Nyu6\n 4pnF28O1pwHJU5qHiEDNJzBv8Z4owVnch8AUsWOOswUnhU6qZxceleZZ","X-Gm-Gg":"AeBDietyXIce2MST4A6vZEpC5odiEvZR0uceeg9l0NoI7zBxm3HIbeIKwNLW19lYukC\n TgvUUpcO8s+hCPuCKeNrMRox5LQnrehUCADkq6r/iSR5qWL6Zny9SiebrRuLDdB78qi1Wb+XGwP\n dZDeAvSEyfQOiOvcdhYzsb8GjcS3JZep4yOWFOv6ndK9+sPzlmarTsJk1SAQqh2yt/SiczGvhON\n Btc1L3ENCIOMGO6xh9gHtkDBlzdUePUGGnAZ25+9LOw2p8T5YyvAzmFGKh8UYuurqgTevO6E6aj\n XfIh4Bho+wTIDW+/tkrUKEKkE72mKbln7ZdprhjWdzsYoxHEQsU5vEutfBfU4le1UBHRu8RAXdR\n XP1acSvNEn91KD2VqMxIJQ9i+hBxrU4ORnCVXEsxv3cAsb6QKrahj4kkZbGQqADdQWqt3uiuUbo\n /Pa6IfKACiJz/JYGGbtSLoOM5tG0nmz29YKatUysinxilLEq5Wqbs4","X-Received":"by 2002:a17:903:3c2f:b0:2b9:6453:389a with SMTP id\n d9443c01a7336-2b97c3cc0b3mr59380525ad.8.1777438236961;\n Tue, 28 Apr 2026 21:50:36 -0700 (PDT)","From":"alistair23@gmail.com","X-Google-Original-From":"alistair.francis@wdc.com","To":"palmer@dabbelt.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com,\n zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com,\n qemu-riscv@nongnu.org, qemu-devel@nongnu.org","Cc":"alistair23@gmail.com, Max Chou ,\n Daniel Henrique Barboza ,\n Nutty Liu ,\n Alistair Francis ","Subject":"[PULL 29/51] target/riscv: rvv: Add new VTYPE CSR field - altfmt","Date":"Wed, 29 Apr 2026 14:47:30 +1000","Message-ID":"<20260429044752.4176397-30-alistair.francis@wdc.com>","X-Mailer":"git-send-email 2.53.0","In-Reply-To":"<20260429044752.4176397-1-alistair.francis@wdc.com>","References":"<20260429044752.4176397-1-alistair.francis@wdc.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::632;\n envelope-from=alistair23@gmail.com; helo=mail-pl1-x632.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Max Chou \n\nAccording to the Zvfbfa ISA spec v0.1, the vtype CSR adds a new field:\naltfmt for BF16 support.\nThis update changes the layout of the vtype CSR fields.\n\n- Removed VEDIV field (bits 8-9) since EDIV extension is not planned to\n be part of the base V extension\n- Added ALTFMT field at bit 8\n- Changed RESERVED field to start from bit 9 instead of bit 10\n\nWhen Zvfbfa is disabled, bits 8+ are treated as reserved (preserving\nexisting behavior for altfmt bit). When Zvfbfa is enabled, only bits 9+\nare reserved.\n\nReference:\n- https://github.com/riscvarchive/riscv-v-spec/blob/master/ediv.adoc\n\nReviewed-by: Daniel Henrique Barboza \nReviewed-by: Chao Liu \nReviewed-by: Nutty Liu \nReviewed-by: Alistair Francis \nSigned-off-by: Max Chou \nMessage-ID: <20260402125234.1371897-4-max.chou@sifive.com>\nSigned-off-by: Alistair Francis \n---\n target/riscv/cpu.h | 4 ++--\n target/riscv/vector_helper.c | 39 +++++++++++++++++++++++++++++++-----\n 2 files changed, 36 insertions(+), 7 deletions(-)","diff":"diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\nindex 35d1f6362c..962cc45073 100644\n--- a/target/riscv/cpu.h\n+++ b/target/riscv/cpu.h\n@@ -191,8 +191,8 @@ FIELD(VTYPE, VLMUL, 0, 3)\n FIELD(VTYPE, VSEW, 3, 3)\n FIELD(VTYPE, VTA, 6, 1)\n FIELD(VTYPE, VMA, 7, 1)\n-FIELD(VTYPE, VEDIV, 8, 2)\n-FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)\n+FIELD(VTYPE, ALTFMT, 8, 1)\n+FIELD(VTYPE, RESERVED, 9, sizeof(target_ulong) * 8 - 10)\n \n typedef struct PMUCTRState {\n /* Current value of a counter */\ndiff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c\nindex 83dd26314d..63ca6fe16b 100644\n--- a/target/riscv/vector_helper.c\n+++ b/target/riscv/vector_helper.c\n@@ -33,6 +33,22 @@\n #include \"vector_internals.h\"\n #include \n \n+static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)\n+{\n+ int xlen = riscv_cpu_xlen(env);\n+ target_ulong reserved = 0;\n+\n+ if (riscv_cpu_cfg(env)->ext_zvfbfa) {\n+ reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,\n+ xlen - 1 - R_VTYPE_RESERVED_SHIFT);\n+ } else {\n+ reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_ALTFMT_SHIFT,\n+ xlen - 1 - R_VTYPE_ALTFMT_SHIFT);\n+ }\n+\n+ return reserved;\n+}\n+\n target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,\n target_ulong s2, target_ulong x0)\n {\n@@ -41,12 +57,10 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,\n uint64_t vlmul = FIELD_EX64(s2, VTYPE, VLMUL);\n uint8_t vsew = FIELD_EX64(s2, VTYPE, VSEW);\n uint16_t sew = 8 << vsew;\n- uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);\n+ uint8_t altfmt = FIELD_EX64(s2, VTYPE, ALTFMT);\n+ bool ill_altfmt = true;\n int xlen = riscv_cpu_xlen(env);\n bool vill = (s2 >> (xlen - 1)) & 0x1;\n- target_ulong reserved = s2 &\n- MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,\n- xlen - 1 - R_VTYPE_RESERVED_SHIFT);\n uint16_t vlen = cpu->cfg.vlenb << 3;\n int8_t lmul;\n \n@@ -63,7 +77,22 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,\n }\n }\n \n- if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {\n+ switch (vsew) {\n+ case MO_8:\n+ ill_altfmt &= !(cpu->cfg.ext_zvfbfa);\n+ break;\n+ case MO_16:\n+ ill_altfmt &= !(cpu->cfg.ext_zvfbfa);\n+ break;\n+ default:\n+ break;\n+ }\n+\n+ if (altfmt && ill_altfmt) {\n+ vill = true;\n+ }\n+\n+ if ((sew > cpu->cfg.elen) || vill || (vtype_reserved(env, s2) != 0)) {\n /* only set vill bit. */\n env->vill = 1;\n env->vtype = 0;\n","prefixes":["PULL","29/51"]}