{"id":2229996,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2229996/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-4-alistair.francis@wdc.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260429044752.4176397-4-alistair.francis@wdc.com>","date":"2026-04-29T04:47:04","name":"[PULL,03/51] target/riscv: add draft RISC-V Zbr ext as xbr0p93","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"05f753d6333ea10b36e515ebed2958652e7e12e9","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/1.1/people/64571/?format=json","name":"Alistair Francis","email":"alistair23@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-4-alistair.francis@wdc.com/mbox/","series":[{"id":501983,"url":"http://patchwork.ozlabs.org/api/1.1/series/501983/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501983","date":"2026-04-29T04:47:05","name":"[PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI","version":1,"mbox":"http://patchwork.ozlabs.org/series/501983/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2229996/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2229996/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=rDbdKA3G;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pg1-x536.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Emmanuel Blot \n\nThis extension was not ratified with the Zb[abcs] bitmanip extensions.\nThis is the latest draft version (0.93) as implemented by the Ibex core.\n\nThese instructions are in the reserved encoding space but have not been\nratified and could conflict with future ratified instructions. For this\nreason they are added as a vendor extension to support Ibex's impl.\n\nSigned-off-by: James Wainwright \nReviewed-by: Alistair Francis \nMessage-ID: <20260320134254.217123-3-james.wainwright@lowrisc.org>\nSigned-off-by: Alistair Francis \n---\n MAINTAINERS | 3 ++\n target/riscv/cpu_cfg.h | 1 +\n target/riscv/helper.h | 2 +\n target/riscv/cpu_cfg_fields.h.inc | 1 +\n target/riscv/xlrbr.decode | 30 +++++++++++\n target/riscv/bitmanip_helper.c | 20 +++++++\n target/riscv/cpu.c | 4 +-\n target/riscv/translate.c | 3 ++\n target/riscv/insn_trans/trans_xlrbr.c.inc | 45 ++++++++++++++++\n target/riscv/meson.build | 1 +\n tests/tcg/riscv64/Makefile.softmmu-target | 5 ++\n tests/tcg/riscv64/test-crc32.S | 64 +++++++++++++++++++++++\n 12 files changed, 178 insertions(+), 1 deletion(-)\n create mode 100644 target/riscv/xlrbr.decode\n create mode 100644 target/riscv/insn_trans/trans_xlrbr.c.inc\n create mode 100644 tests/tcg/riscv64/test-crc32.S","diff":"diff --git a/MAINTAINERS b/MAINTAINERS\nindex 49f9bce818..f7e835cf55 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -1729,6 +1729,9 @@ F: hw/riscv/opentitan.c\n F: hw/*/ibex_*.c\n F: include/hw/riscv/opentitan.h\n F: include/hw/*/ibex_*.h\n+F: target/riscv/insn_trans/trans_xthead.c.inc\n+F: target/riscv/xlrbr.decode\n+F: tests/tcg/riscv64/test-crc32.S\n \n Microchip PolarFire SoC Icicle Kit\n L: qemu-riscv@nongnu.org\ndiff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h\nindex cd1cba797c..211d0708ba 100644\n--- a/target/riscv/cpu_cfg.h\n+++ b/target/riscv/cpu_cfg.h\n@@ -69,5 +69,6 @@ MATERIALISE_EXT_PREDICATE(xtheadmemidx)\n MATERIALISE_EXT_PREDICATE(xtheadmempair)\n MATERIALISE_EXT_PREDICATE(xtheadsync)\n MATERIALISE_EXT_PREDICATE(XVentanaCondOps)\n+MATERIALISE_EXT_PREDICATE(xlrbr);\n \n #endif\ndiff --git a/target/riscv/helper.h b/target/riscv/helper.h\nindex b785456ee0..7722c590bd 100644\n--- a/target/riscv/helper.h\n+++ b/target/riscv/helper.h\n@@ -84,6 +84,8 @@ DEF_HELPER_FLAGS_1(unzip, TCG_CALL_NO_RWG_SE, tl, tl)\n DEF_HELPER_FLAGS_1(zip, TCG_CALL_NO_RWG_SE, tl, tl)\n DEF_HELPER_FLAGS_2(xperm4, TCG_CALL_NO_RWG_SE, tl, tl, tl)\n DEF_HELPER_FLAGS_2(xperm8, TCG_CALL_NO_RWG_SE, tl, tl, tl)\n+DEF_HELPER_FLAGS_2(crc32, TCG_CALL_NO_RWG_SE, tl, tl, tl)\n+DEF_HELPER_FLAGS_2(crc32c, TCG_CALL_NO_RWG_SE, tl, tl, tl)\n \n /* Floating Point - Half Precision */\n DEF_HELPER_FLAGS_3(fadd_h, TCG_CALL_NO_RWG, i64, env, i64, i64)\ndiff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc\nindex cd1a5ec56b..d4b7c880d4 100644\n--- a/target/riscv/cpu_cfg_fields.h.inc\n+++ b/target/riscv/cpu_cfg_fields.h.inc\n@@ -154,6 +154,7 @@ BOOL_FIELD(ext_XVentanaCondOps)\n BOOL_FIELD(ext_xmipscbop)\n BOOL_FIELD(ext_xmipscmov)\n BOOL_FIELD(ext_xmipslsp)\n+BOOL_FIELD(ext_xlrbr)\n \n BOOL_FIELD(mmu)\n BOOL_FIELD(pmp)\ndiff --git a/target/riscv/xlrbr.decode b/target/riscv/xlrbr.decode\nnew file mode 100644\nindex 0000000000..893ce6ec71\n--- /dev/null\n+++ b/target/riscv/xlrbr.decode\n@@ -0,0 +1,30 @@\n+#\n+# Translation routines for the instructions of the xlrbr ISA extension\n+# (matching the draft encodings in the standard reserved encoding space for the\n+# unratified Zbr CRC32 bitmanip extension version 0.93).\n+#\n+# Copyright (c) 2026 Rivos Inc.\n+#\n+# SPDX-License-Identifier: GPL-2.0-or-later\n+\n+# Fields:\n+%rs1 15:5\n+%rd 7:5\n+\n+# Argument sets:\n+&r2 rd rs1 !extern\n+\n+# Formats 32:\n+@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd\n+\n+# *** RV32 xlrbr extension ***\n+crc32_b 0110000 10000 ..... 001 ..... 0010011 @r2\n+crc32_h 0110000 10001 ..... 001 ..... 0010011 @r2\n+crc32_w 0110000 10010 ..... 001 ..... 0010011 @r2\n+crc32c_b 0110000 11000 ..... 001 ..... 0010011 @r2\n+crc32c_h 0110000 11001 ..... 001 ..... 0010011 @r2\n+crc32c_w 0110000 11010 ..... 001 ..... 0010011 @r2\n+\n+# *** RV64 xlrbr extension (in addition to RV32) ***\n+crc32_d 0110000 10011 ..... 001 ..... 0010011 @r2\n+crc32c_d 0110000 11011 ..... 001 ..... 0010011 @r2\ndiff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c\nindex e9c8d7f778..1156a87dd3 100644\n--- a/target/riscv/bitmanip_helper.c\n+++ b/target/riscv/bitmanip_helper.c\n@@ -23,6 +23,8 @@\n #include \"exec/target_long.h\"\n #include \"exec/helper-proto.h\"\n #include \"tcg/tcg.h\"\n+#include \"qemu/crc32.h\"\n+#include \"qemu/crc32c.h\"\n \n target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)\n {\n@@ -129,3 +131,21 @@ target_ulong HELPER(xperm8)(target_ulong rs1, target_ulong rs2)\n {\n return do_xperm(rs1, rs2, 3);\n }\n+\n+target_ulong HELPER(crc32)(target_ulong rs1, target_ulong sz)\n+{\n+ for (target_ulong i = 0; i < sz; i++) {\n+ rs1 = crc32_table[rs1 & 0xFF] ^ (rs1 >> 8);\n+ }\n+\n+ return rs1;\n+}\n+\n+target_ulong HELPER(crc32c)(target_ulong rs1, target_ulong sz)\n+{\n+ for (target_ulong i = 0; i < sz; i++) {\n+ rs1 = crc32c_table[rs1 & 0xFF] ^ (rs1 >> 8);\n+ }\n+\n+ return rs1;\n+}\ndiff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex 8ac935ac06..03a1bb075a 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -1373,6 +1373,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {\n MULTI_EXT_CFG_BOOL(\"xmipscbop\", ext_xmipscbop, false),\n MULTI_EXT_CFG_BOOL(\"xmipscmov\", ext_xmipscmov, false),\n MULTI_EXT_CFG_BOOL(\"xmipslsp\", ext_xmipslsp, false),\n+ MULTI_EXT_CFG_BOOL(\"xlrbr\", ext_xlrbr, false),\n \n { },\n };\n@@ -3059,7 +3060,8 @@ static const TypeInfo riscv_cpu_type_infos[] = {\n .cfg.ext_zba = true,\n .cfg.ext_zbb = true,\n .cfg.ext_zbc = true,\n- .cfg.ext_zbs = true\n+ .cfg.ext_zbs = true,\n+ .cfg.ext_xlrbr = true\n ),\n \n DEFINE_RISCV_CPU(TYPE_RISCV_CPU_SIFIVE_E31, TYPE_RISCV_CPU_SIFIVE_E,\ndiff --git a/target/riscv/translate.c b/target/riscv/translate.c\nindex f42e53df88..711080f3fd 100644\n--- a/target/riscv/translate.c\n+++ b/target/riscv/translate.c\n@@ -1213,9 +1213,11 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)\n #include \"insn_trans/trans_rvbf16.c.inc\"\n #include \"decode-xthead.c.inc\"\n #include \"decode-xmips.c.inc\"\n+#include \"decode-xlrbr.c.inc\"\n #include \"insn_trans/trans_xthead.c.inc\"\n #include \"insn_trans/trans_xventanacondops.c.inc\"\n #include \"insn_trans/trans_xmips.c.inc\"\n+#include \"insn_trans/trans_xlrbr.c.inc\"\n \n /* Include the auto-generated decoder for 16 bit insn */\n #include \"decode-insn16.c.inc\"\n@@ -1235,6 +1237,7 @@ const RISCVDecoder decoder_table[] = {\n { has_xmips_p, decode_xmips},\n { has_xthead_p, decode_xthead},\n { has_XVentanaCondOps_p, decode_XVentanaCodeOps},\n+ { has_xlrbr_p, decode_xlrbr},\n };\n \n const size_t decoder_table_size = ARRAY_SIZE(decoder_table);\ndiff --git a/target/riscv/insn_trans/trans_xlrbr.c.inc b/target/riscv/insn_trans/trans_xlrbr.c.inc\nnew file mode 100644\nindex 0000000000..01da2b6ce1\n--- /dev/null\n+++ b/target/riscv/insn_trans/trans_xlrbr.c.inc\n@@ -0,0 +1,45 @@\n+/*\n+ * RISC-V translation routines for xlrbr matching the unratified Zbr CRC32\n+ * bitmanip extension v0.93.\n+ *\n+ * Copyright (c) 2026 Rivos Inc.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#define REQUIRE_XLRBR(ctx) do { \\\n+ if (!ctx->cfg_ptr->ext_xlrbr) { \\\n+ return false; \\\n+ } \\\n+} while (0)\n+\n+static bool gen_crc(DisasContext *ctx, arg_r2 *a,\n+ void (*func)(TCGv, TCGv, TCGv), TCGv tsz)\n+{\n+ REQUIRE_XLRBR(ctx);\n+ TCGv dest = dest_gpr(ctx, a->rd);\n+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);\n+\n+ func(dest, src1, tsz);\n+ gen_set_gpr(ctx, a->rd, dest);\n+\n+ return true;\n+}\n+\n+#define TRANS_CRC32(NAME, SIZE) \\\n+ static bool trans_crc32_##NAME(DisasContext *ctx, arg_r2 *a) \\\n+ { if (SIZE == 8) { REQUIRE_64BIT(ctx); }; \\\n+ return gen_crc(ctx, a, gen_helper_crc32, tcg_constant_tl(SIZE)); }\n+#define TRANS_CRC32C(NAME, SIZE) \\\n+ static bool trans_crc32c_##NAME(DisasContext *ctx, arg_r2 *a) \\\n+ { if (SIZE == 8) { REQUIRE_64BIT(ctx); }; \\\n+ return gen_crc(ctx, a, gen_helper_crc32c, tcg_constant_tl(SIZE)); }\n+\n+TRANS_CRC32(b, 1);\n+TRANS_CRC32(h, 2);\n+TRANS_CRC32(w, 4);\n+TRANS_CRC32(d, 8);\n+TRANS_CRC32C(b, 1);\n+TRANS_CRC32C(h, 2);\n+TRANS_CRC32C(w, 4);\n+TRANS_CRC32C(d, 8);\ndiff --git a/target/riscv/meson.build b/target/riscv/meson.build\nindex 3842c7c1a8..79f36abd63 100644\n--- a/target/riscv/meson.build\n+++ b/target/riscv/meson.build\n@@ -5,6 +5,7 @@ gen = [\n decodetree.process('xthead.decode', extra_args: '--static-decode=decode_xthead'),\n decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decode=decode_XVentanaCodeOps'),\n decodetree.process('xmips.decode', extra_args: '--static-decode=decode_xmips'),\n+ decodetree.process('xlrbr.decode', extra_args: '--static-decode=decode_xlrbr'),\n ]\n \n riscv_ss = ss.source_set()\ndiff --git a/tests/tcg/riscv64/Makefile.softmmu-target b/tests/tcg/riscv64/Makefile.softmmu-target\nindex eb1ce6504a..82be8a2c91 100644\n--- a/tests/tcg/riscv64/Makefile.softmmu-target\n+++ b/tests/tcg/riscv64/Makefile.softmmu-target\n@@ -36,5 +36,10 @@ run-plugin-interruptedmemory: interruptedmemory\n \t $(QEMU) -plugin ../plugins/libdiscons.so -d plugin -D $<.pout \\\n \t $(QEMU_OPTS)$<)\n \n+EXTRA_RUNS += run-test-crc32\n+comma:= ,\n+run-test-crc32: test-crc32\n+\t$(call run-test, $<, $(QEMU) -cpu rv64$(comma)xlrbr=true $(QEMU_OPTS)$<)\n+\n # We don't currently support the multiarch system tests\n undefine MULTIARCH_TESTS\ndiff --git a/tests/tcg/riscv64/test-crc32.S b/tests/tcg/riscv64/test-crc32.S\nnew file mode 100644\nindex 0000000000..70d70b16a9\n--- /dev/null\n+++ b/tests/tcg/riscv64/test-crc32.S\n@@ -0,0 +1,64 @@\n+/*\n+ * Copyright (c) 2026 lowRISC CIC\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#define crc32(op, rd, rs1) .insn r 19, 1, 48, rd, rs1, x##op\n+\n+#define crc32_b(rd, rs1) crc32(16, rd, rs1)\n+#define crc32_h(rd, rs1) crc32(17, rd, rs1)\n+#define crc32_w(rd, rs1) crc32(18, rd, rs1)\n+#define crc32_d(rd, rs1) crc32(19, rd, rs1)\n+#define crc32c_b(rd, rs1) crc32(24, rd, rs1)\n+#define crc32c_h(rd, rs1) crc32(25, rd, rs1)\n+#define crc32c_w(rd, rs1) crc32(26, rd, rs1)\n+#define crc32c_d(rd, rs1) crc32(27, rd, rs1)\n+\n+\t.option norvc\n+\n+\t.text\n+\t.globl _start\n+_start:\n+\tlla t0, trap\n+\tcsrw mtvec, t0\n+\n+\tli\tt0, 0x34e24a2cd65650d4\n+\n+\tcrc32_b \t(t0, t0)\n+\tcrc32_h \t(t0, t0)\n+\tcrc32_w \t(t0, t0)\n+\tcrc32_d \t(t0, t0)\n+\tcrc32c_b\t(t0, t0)\n+\tcrc32c_h\t(t0, t0)\n+\tcrc32c_w\t(t0, t0)\n+\tcrc32c_d\t(t0, t0)\n+\n+\tli\tt1, 0x68167e78\n+\n+\tli\ta0, 0\n+\tbeq\tt0, t1, _exit\n+fail:\n+\tli\ta0, 1\n+_exit:\n+\tlla\ta1, semiargs\n+\tli\tt0, 0x20026\t# ADP_Stopped_ApplicationExit\n+\tsd\tt0, 0(a1)\n+\tsd\ta0, 8(a1)\n+\tli\ta0, 0x20\t# TARGET_SYS_EXIT_EXTENDED\n+\n+\t# Semihosting call sequence\n+\t.balign\t16\n+\tslli\tzero, zero, 0x1f\n+\tebreak\n+\tsrai\tzero, zero, 0x7\n+\tj\t.\n+\n+\t.data\n+\t.balign\t16\n+semiargs:\n+\t.space\t16\n+\n+trap:\n+\tcsrr t0, mepc\n+\taddi t0, t0, 4\n+\tmret\n","prefixes":["PULL","03/51"]}