{"id":2229995,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2229995/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-19-alistair.francis@wdc.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260429044752.4176397-19-alistair.francis@wdc.com>","date":"2026-04-29T04:47:19","name":"[PULL,18/51] target/riscv: Use MO_LE for instruction fetch","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"29ac6d49a29bb9427b2ae9319b488e9b6cfc48eb","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/1.1/people/64571/?format=json","name":"Alistair Francis","email":"alistair23@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-19-alistair.francis@wdc.com/mbox/","series":[{"id":501983,"url":"http://patchwork.ozlabs.org/api/1.1/series/501983/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501983","date":"2026-04-29T04:47:05","name":"[PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI","version":1,"mbox":"http://patchwork.ozlabs.org/series/501983/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2229995/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2229995/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=VRY9+Cyo;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::535;\n envelope-from=alistair23@gmail.com; helo=mail-pg1-x535.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Djordje Todorovic \n\nRISC-V instructions are always little-endian regardless of the data\nendianness mode configured via mstatus SBE/MBE/UBE bits.\n\nCurrently, instruction fetches in decode_opc() and the page boundary\ncheck use mo_endian(ctx), which returns MO_TE. This happens to work\ntoday because RISC-V targets are little-endian only, but is\nsemantically incorrect and will break once mo_endian() is updated to\nrespect runtime data endianness for big-endian support.\n\nUse MO_LE explicitly for all instruction fetch paths. Data memory\noperations (AMOs, loads/stores via mxl_memop) continue to use\nmo_endian(ctx) as they should respect the configured data endianness.\n\nNot-Signed-off-by: Djordje Todorovic \nReviewed-by: Alistair Francis \nMessage-ID: <20260311115910.564481-3-djordje.todorovic@htecgroup.com>\nSigned-off-by: Philippe Mathieu-Daudé \nMessage-ID: <20260318103122.97244-16-philmd@linaro.org>\nSigned-off-by: Alistair Francis \n---\n target/riscv/translate.c | 8 ++++----\n 1 file changed, 4 insertions(+), 4 deletions(-)","diff":"diff --git a/target/riscv/translate.c b/target/riscv/translate.c\nindex 1a25c517a2..f6b915a7fb 100644\n--- a/target/riscv/translate.c\n+++ b/target/riscv/translate.c\n@@ -1258,7 +1258,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx)\n * additional page fault.\n */\n opcode = translator_ldl_end(env, &ctx->base, ctx->base.pc_next,\n- mo_endian(ctx));\n+ MO_LE);\n } else {\n /*\n * For unaligned pc, instruction preload may trigger additional\n@@ -1266,7 +1266,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx)\n */\n opcode = (uint32_t) translator_lduw_end(env, &ctx->base,\n ctx->base.pc_next,\n- mo_endian(ctx));\n+ MO_LE);\n }\n ctx->ol = ctx->xl;\n \n@@ -1288,7 +1288,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx)\n opcode = deposit32(opcode, 16, 16,\n translator_lduw_end(env, &ctx->base,\n ctx->base.pc_next + 2,\n- mo_endian(ctx)));\n+ MO_LE));\n }\n ctx->opcode = opcode;\n \n@@ -1404,7 +1404,7 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) {\n uint16_t next_insn =\n translator_lduw_end(env, &ctx->base, ctx->base.pc_next,\n- mo_endian(ctx));\n+ MO_LE);\n int len = insn_len(next_insn);\n \n if (!translator_is_same_page(&ctx->base, ctx->base.pc_next + len - 1)) {\n","prefixes":["PULL","18/51"]}