{"id":2229992,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2229992/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-12-alistair.francis@wdc.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260429044752.4176397-12-alistair.francis@wdc.com>","date":"2026-04-29T04:47:12","name":"[PULL,11/51] target/riscv: Simplify riscv_cpu_gdb_write_register()","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f9d9cdc767887846191a8bf375b6eb9ac6d121b2","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/1.1/people/64571/?format=json","name":"Alistair Francis","email":"alistair23@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-12-alistair.francis@wdc.com/mbox/","series":[{"id":501983,"url":"http://patchwork.ozlabs.org/api/1.1/series/501983/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501983","date":"2026-04-29T04:47:05","name":"[PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI","version":1,"mbox":"http://patchwork.ozlabs.org/series/501983/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2229992/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2229992/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=R2uXS83b;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::633;\n envelope-from=alistair23@gmail.com; helo=mail-pl1-x633.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Philippe Mathieu-Daudé \n\nUse a single ldn() call, sign-extend once.\n\nSigned-off-by: Philippe Mathieu-Daudé \nReviewed-by: Alistair Francis \nMessage-ID: <20260318103122.97244-9-philmd@linaro.org>\nSigned-off-by: Alistair Francis \n---\n target/riscv/gdbstub.c | 25 ++++++-------------------\n 1 file changed, 6 insertions(+), 19 deletions(-)","diff":"diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c\nindex be42566bcc..a5c1263878 100644\n--- a/target/riscv/gdbstub.c\n+++ b/target/riscv/gdbstub.c\n@@ -84,33 +84,20 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);\n RISCVCPU *cpu = RISCV_CPU(cs);\n CPURISCVState *env = &cpu->env;\n- int length = 0;\n- uint64_t tmp;\n+ const size_t regsize = mcc->def->misa_mxl_max == MXL_RV32 ? 4 : 8;\n+ uint64_t tmp = ldn(env, mem_buf, regsize);\n \n- switch (mcc->def->misa_mxl_max) {\n- case MXL_RV32:\n- tmp = (int32_t)ldn(env, mem_buf, 4);\n- length = 4;\n- break;\n- case MXL_RV64:\n- case MXL_RV128:\n- if (env->xl < MXL_RV64) {\n- tmp = (int32_t)ldn(env, mem_buf, 8);\n- } else {\n- tmp = ldn(env, mem_buf, 8);\n- }\n- length = 8;\n- break;\n- default:\n- g_assert_not_reached();\n+ if (env->xl < MXL_RV64) {\n+ tmp = (int32_t)tmp;\n }\n+\n if (n > 0 && n < 32) {\n env->gpr[n] = tmp;\n } else if (n == 32) {\n env->pc = tmp;\n }\n \n- return length;\n+ return regsize;\n }\n \n static int riscv_gdb_get_fpu(CPUState *cs, GByteArray *buf, int n)\n","prefixes":["PULL","11/51"]}