{"id":2229991,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2229991/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-11-alistair.francis@wdc.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260429044752.4176397-11-alistair.francis@wdc.com>","date":"2026-04-29T04:47:11","name":"[PULL,10/51] target/riscv: Factor tiny ldn() helper in gdbstub","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"35194335528aaa4e4205dbcb2b6c9928a2a5e078","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/1.1/people/64571/?format=json","name":"Alistair Francis","email":"alistair23@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-11-alistair.francis@wdc.com/mbox/","series":[{"id":501983,"url":"http://patchwork.ozlabs.org/api/1.1/series/501983/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501983","date":"2026-04-29T04:47:05","name":"[PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI","version":1,"mbox":"http://patchwork.ozlabs.org/series/501983/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2229991/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2229991/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=ENeIIFyB;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::62d;\n envelope-from=alistair23@gmail.com; helo=mail-pl1-x62d.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Philippe Mathieu-Daudé \n\nIn preparation of having this helper handle CPU runtime\nendianness changes, factor the ldn() helper out.\n\nSigned-off-by: Philippe Mathieu-Daudé \nReviewed-by: Alistair Francis \nMessage-ID: <20260318103122.97244-8-philmd@linaro.org>\nSigned-off-by: Alistair Francis \n---\n target/riscv/gdbstub.c | 22 +++++++++++++---------\n 1 file changed, 13 insertions(+), 9 deletions(-)","diff":"diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c\nindex 6a5b7a82fd..be42566bcc 100644\n--- a/target/riscv/gdbstub.c\n+++ b/target/riscv/gdbstub.c\n@@ -47,6 +47,11 @@ static const struct TypeSize vec_lanes[] = {\n { \"uint8\", \"bytes\", 8, 'b' },\n };\n \n+static uint64_t ldn(CPURISCVState *env, uint8_t *mem_buf, size_t regsz)\n+{\n+ return ldn_p(mem_buf, regsz);\n+}\n+\n int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)\n {\n RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);\n@@ -84,15 +89,15 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n \n switch (mcc->def->misa_mxl_max) {\n case MXL_RV32:\n- tmp = (int32_t)ldl_p(mem_buf);\n+ tmp = (int32_t)ldn(env, mem_buf, 4);\n length = 4;\n break;\n case MXL_RV64:\n case MXL_RV128:\n if (env->xl < MXL_RV64) {\n- tmp = (int32_t)ldq_p(mem_buf);\n+ tmp = (int32_t)ldn(env, mem_buf, 8);\n } else {\n- tmp = ldq_p(mem_buf);\n+ tmp = ldn(env, mem_buf, 8);\n }\n length = 8;\n break;\n@@ -130,7 +135,7 @@ static int riscv_gdb_set_fpu(CPUState *cs, uint8_t *mem_buf, int n)\n CPURISCVState *env = &cpu->env;\n \n if (n < 32) {\n- env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */\n+ env->fpr[n] = ldn(env, mem_buf, 8); /* always 64-bit */\n return sizeof(uint64_t);\n }\n return 0;\n@@ -162,7 +167,7 @@ static int riscv_gdb_set_vector(CPUState *cs, uint8_t *mem_buf, int n)\n if (n < 32) {\n int i;\n for (i = 0; i < vlenb; i += 8) {\n- env->vreg[(n * vlenb + i) / 8] = ldq_p(mem_buf + i);\n+ env->vreg[(n * vlenb + i) / 8] = ldn(env, mem_buf + i, 8);\n }\n return vlenb;\n }\n@@ -194,7 +199,7 @@ static int riscv_gdb_set_csr(CPUState *cs, uint8_t *mem_buf, int n)\n const unsigned regsz = riscv_cpu_is_32bit(cpu) ? 4 : 8;\n \n if (n < CSR_TABLE_SIZE) {\n- uint64_t val = ldn_p(mem_buf, regsz);\n+ uint64_t val = ldn(env, mem_buf, regsz);\n int result;\n \n result = riscv_csrrw_debug(env, n, NULL, val, -1);\n@@ -230,8 +235,7 @@ static int riscv_gdb_set_virtual(CPUState *cs, uint8_t *mem_buf, int n)\n const unsigned regsz = riscv_cpu_is_32bit(cpu) ? 4 : 8;\n #ifndef CONFIG_USER_ONLY\n CPURISCVState *env = &cpu->env;\n-\n- target_ulong new_priv = ldn_p(mem_buf, regsz) & 0x3;\n+ uint64_t new_priv = ldn(env, mem_buf, regsz) & 0x3;\n bool new_virt = 0;\n \n if (new_priv == PRV_RESERVED) {\n@@ -239,7 +243,7 @@ static int riscv_gdb_set_virtual(CPUState *cs, uint8_t *mem_buf, int n)\n }\n \n if (new_priv != PRV_M) {\n- new_virt = (ldn_p(mem_buf, regsz) & BIT(2)) >> 2;\n+ new_virt = (ldn(env, mem_buf, regsz) & BIT(2)) >> 2;\n }\n \n if (riscv_has_ext(env, RVH) && new_virt != env->virt_enabled) {\n","prefixes":["PULL","10/51"]}