{"id":2229940,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2229940/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/927da1bd-f02e-4188-9221-efd240c596b9@oss.qualcomm.com/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/1.1/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<927da1bd-f02e-4188-9221-efd240c596b9@oss.qualcomm.com>","date":"2026-04-28T23:09:15","name":"[to-be-committed,V2,RISC-V,PR,rtl-optimization/96692] Improve xor+xor+ior sequence when possible","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"dabd42050682760def0ecd5870ea1fbe09d2f797","submitter":{"id":92310,"url":"http://patchwork.ozlabs.org/api/1.1/people/92310/?format=json","name":"Jeffrey Law","email":"jeffrey.law@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/927da1bd-f02e-4188-9221-efd240c596b9@oss.qualcomm.com/mbox/","series":[{"id":501949,"url":"http://patchwork.ozlabs.org/api/1.1/series/501949/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=501949","date":"2026-04-28T23:09:15","name":"[to-be-committed,V2,RISC-V,PR,rtl-optimization/96692] Improve xor+xor+ior sequence when possible","version":2,"mbox":"http://patchwork.ozlabs.org/series/501949/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2229940/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2229940/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=GaJzQumd;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=jT7xABDk;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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boundary=\"------------eL8vbUdhzKDzT2sY6vJYaMmt\"","Message-ID":"<927da1bd-f02e-4188-9221-efd240c596b9@oss.qualcomm.com>","Date":"Tue, 28 Apr 2026 17:09:15 -0600","MIME-Version":"1.0","User-Agent":"Mozilla Thunderbird","Content-Language":"en-US","To":"'GCC Patches' ","From":"Jeffrey Law ","Subject":"[to-be-committed][V2][RISC-V][PR rtl-optimization/96692] Improve\n xor+xor+ior sequence when possible","X-Authority-Analysis":"v=2.4 cv=a/0AM0SF c=1 sm=1 tr=0 ts=69f13e1f cx=c_pps\n a=bS7HVuBVfinNPG3f6cIo3Q==:117 a=asGLMfRmzhnGNxaIYohjRg==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=r77TgQKjGQsHNAKrUKIA:9\n a=00i765lXaEkKCoayYukA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10\n a=zgiPjhLxNE0A:10 a=dchKkLRZ2pBP7s9pDGoA:9 a=B2y7HmGcmWMA:10\n a=vBUdepa8ALXHeOFLBtFW:22","X-Proofpoint-ORIG-GUID":"qkraz-BwnIOtNlNdlCcBUJoGdIYzfXYp","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDI4MDIyNyBTYWx0ZWRfX8s1RAtK1F610\n CzdZ+P3Rk9VyFRyyj38AlGdG4AyvJhkHoO34LQj0lENDAiR0NW4Oa/2TpE8E55I6I3zzvLSGHlD\n DeCBj5bTc8lHC4a6vbHyhD/pEGRzT54WHm4ny6yUBjDf+hZrtrCLkK3kZrGTL0LA+N419DqHdWE\n DAvTNdYWv20Y1OAqTbcltNDt2T/y17JhOCKmMtA3qoBzo3n/NK1UkP3Uqye8ATEfGPxHMXqeZs+\n 2F9ceUNhwfWQ1BvTksU1poTSYwxGUkA69ydgUnRlTqpdTr7GuC6df4zZSAa3pIddF0rhmJ0ofM8\n cA0LomRNpcO5qvTwzXoS8QrLizbQ8slsy1R9HS1HqTyTgGjLPz+k3+cOrYSphW3mePEzWmPeItV\n bRlfg362/NZz7BS/n8JDjoyWa74K8ka8LbngboZbl/s28NUJQPYRgLWhDpXmpMM5CI1Pmz21a9S\n iaI0TpEwDDFfYbBpHEg==","X-Proofpoint-GUID":"qkraz-BwnIOtNlNdlCcBUJoGdIYzfXYp","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-28_05,2026-04-28_01,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n impostorscore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0\n spamscore=0 clxscore=1015 phishscore=0 bulkscore=0 priorityscore=1501\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604280227","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"So this is an update to a patch I posted yesterday that the pre-commit \nCI system didn't pick up.  All that has changed is the context for the \ndiff to account for changes in bitmanip.md that have landed in the last \n24 hours.\n\n--\n\nConsider this code:\n\nint f(int a, int b, int c)\n{\n     return (a ^ b) ^ (a | c);\n}\n\n\nFor RISC-V we generate something like this:\n\n         xor     a1,a0,a1\n         or      a0,a0,a2\n         xor     a0,a1,a0\n\nBut this would be better:\n\n         andn    a0,a2,a0\n         xor     a0,a0,a1\n\nIt looks like Roger tackled this earlier with splitters for x86. I'd \nhave leaned more towards simplify-rtx, but there may be secondary \nconcerns at play.  So I'll attack in the RISC-V target files in a \nsimilar manner.\n\nThe patch, but not the testcase, have been in my tester for a while, so \nit's been bootstrapped and regression tested on the Pioneer and BPI-F3 \nboard and regression tested on riscv32-elf and riscv64-elf. Obviously \nI'll wait for pre-commit CI before moving forward.\n\nJeff\nPR rtl-optimization/96692\ngcc/\n\t* config/riscv/bitmanip.md (xor+xor+ior splitters): New splitters\n\tthat ultimately generate andn+xor when possible.\n\ngcc/testsuite\n\n\t* gcc.target/riscv/pr96692.c: New test.","diff":"diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md\nindex c9561b0b622..79ab17b6a60 100644\n--- a/gcc/config/riscv/bitmanip.md\n+++ b/gcc/config/riscv/bitmanip.md\n@@ -1441,3 +1441,26 @@ (define_split\n operands[3] = gen_lowpart (DImode, operands[3]);\n operands[6] = gen_lowpart (SImode, operands[5]);\n })\n+\n+(define_split\n+ [(set (match_operand:X 0 \"register_operand\")\n+ (xor:X (xor:X (ior:X (match_operand:X 1 \"register_operand\")\n+ (match_operand:X 2 \"register_operand\"))\n+ (match_dup 1))\n+ (match_operand:X 3 \"register_operand\")))\n+ (clobber (match_operand:X 4 \"register_operand\"))]\n+ \"TARGET_ZBB || TARGET_ZBKB\"\n+ [(set (match_dup 4) (and:X (not:X (match_dup 1)) (match_dup 2)))\n+ (set (match_dup 0) (xor:X (match_dup 4) (match_dup 3)))])\n+\n+(define_split\n+ [(set (match_operand:X 0 \"register_operand\")\n+ (xor:X (xor:X (ior:X (match_operand:X 1 \"register_operand\")\n+ (match_operand:X 2 \"register_operand\"))\n+ (match_dup 2))\n+ (match_operand:X 3 \"register_operand\")))\n+ (clobber (match_operand:X 4 \"register_operand\"))]\n+ \"TARGET_ZBB || TARGET_ZBKB\"\n+ [(set (match_dup 4) (and:X (not:X (match_dup 2)) (match_dup 1)))\n+ (set (match_dup 0) (xor:X (match_dup 4) (match_dup 3)))])\n+\ndiff --git a/gcc/testsuite/gcc.target/riscv/pr96692.c b/gcc/testsuite/gcc.target/riscv/pr96692.c\nnew file mode 100644\nindex 00000000000..650f4f0f80d\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/pr96692.c\n@@ -0,0 +1,12 @@\n+/* { dg-do compile } */\n+/* { dg-additional-options \"-march=rv64gcb_zicond -mabi=lp64d\" { target rv64 } } */\n+/* { dg-additional-options \"-march=rv32gcb_zicond -mabi=ilp32\" { target rv32 } } */\n+/* { dg-skip-if \"\" { *-*-* } { \"-O0\" \"-Og\" } } */\n+\n+int f(int a, int b, int c)\n+{\n+ return (a ^ b) ^ (a | c);\n+}\n+\n+/* { dg-final { scan-assembler-times \"xor\\t\" 1 } } */\n+/* { dg-final { scan-assembler-times \"andn\\t\" 1 } } */\n","prefixes":["to-be-committed","V2","RISC-V","PR","rtl-optimization/96692"]}